1 /* 2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/arm/fsl-imx6.h" 25 #include "hw/usb/imx-usb-phy.h" 26 #include "hw/boards.h" 27 #include "hw/qdev-properties.h" 28 #include "sysemu/sysemu.h" 29 #include "chardev/char.h" 30 #include "qemu/error-report.h" 31 #include "qemu/module.h" 32 #include "target/arm/cpu-qom.h" 33 34 #define IMX6_ESDHC_CAPABILITIES 0x057834b4 35 36 #define NAME_SIZE 20 37 38 static void fsl_imx6_init(Object *obj) 39 { 40 MachineState *ms = MACHINE(qdev_get_machine()); 41 FslIMX6State *s = FSL_IMX6(obj); 42 char name[NAME_SIZE]; 43 int i; 44 45 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) { 46 snprintf(name, NAME_SIZE, "cpu%d", i); 47 object_initialize_child(obj, name, &s->cpu[i], 48 ARM_CPU_TYPE_NAME("cortex-a9")); 49 } 50 51 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 52 53 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM); 54 55 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC); 56 57 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); 58 59 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 60 snprintf(name, NAME_SIZE, "uart%d", i + 1); 61 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); 62 } 63 64 object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT); 65 66 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 67 snprintf(name, NAME_SIZE, "epit%d", i + 1); 68 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT); 69 } 70 71 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 72 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 73 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); 74 } 75 76 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 77 snprintf(name, NAME_SIZE, "gpio%d", i + 1); 78 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); 79 } 80 81 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 82 snprintf(name, NAME_SIZE, "sdhc%d", i + 1); 83 object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC); 84 } 85 86 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { 87 snprintf(name, NAME_SIZE, "usbphy%d", i); 88 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); 89 } 90 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { 91 snprintf(name, NAME_SIZE, "usb%d", i); 92 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); 93 } 94 95 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 96 snprintf(name, NAME_SIZE, "spi%d", i + 1); 97 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); 98 } 99 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { 100 snprintf(name, NAME_SIZE, "wdt%d", i); 101 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); 102 } 103 104 105 object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET); 106 } 107 108 static void fsl_imx6_realize(DeviceState *dev, Error **errp) 109 { 110 MachineState *ms = MACHINE(qdev_get_machine()); 111 FslIMX6State *s = FSL_IMX6(dev); 112 uint16_t i; 113 unsigned int smp_cpus = ms->smp.cpus; 114 115 if (smp_cpus > FSL_IMX6_NUM_CPUS) { 116 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", 117 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus); 118 return; 119 } 120 121 for (i = 0; i < smp_cpus; i++) { 122 123 /* On uniprocessor, the CBAR is set to 0 */ 124 if (smp_cpus > 1) { 125 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 126 FSL_IMX6_A9MPCORE_ADDR, &error_abort); 127 } 128 129 /* All CPU but CPU 0 start in power off mode */ 130 if (i) { 131 object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off", 132 true, &error_abort); 133 } 134 135 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 136 return; 137 } 138 } 139 140 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus, 141 &error_abort); 142 143 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", 144 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort); 145 146 if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) { 147 return; 148 } 149 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); 150 151 for (i = 0; i < smp_cpus; i++) { 152 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 153 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 154 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, 155 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 156 } 157 158 /* L2 cache controller */ 159 sysbus_create_simple("l2x0", FSL_IMX6_PL310_ADDR, NULL); 160 161 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { 162 return; 163 } 164 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); 165 166 if (!sysbus_realize(SYS_BUS_DEVICE(&s->src), errp)) { 167 return; 168 } 169 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR); 170 171 /* Initialize all UARTs */ 172 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 173 static const struct { 174 hwaddr addr; 175 unsigned int irq; 176 } serial_table[FSL_IMX6_NUM_UARTS] = { 177 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ }, 178 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ }, 179 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ }, 180 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ }, 181 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, 182 }; 183 184 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 185 186 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 187 return; 188 } 189 190 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 191 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 192 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 193 serial_table[i].irq)); 194 } 195 196 s->gpt.ccm = IMX_CCM(&s->ccm); 197 198 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) { 199 return; 200 } 201 202 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); 203 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 204 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 205 FSL_IMX6_GPT_IRQ)); 206 207 /* Initialize all EPIT timers */ 208 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 209 static const struct { 210 hwaddr addr; 211 unsigned int irq; 212 } epit_table[FSL_IMX6_NUM_EPITS] = { 213 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ }, 214 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ }, 215 }; 216 217 s->epit[i].ccm = IMX_CCM(&s->ccm); 218 219 if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) { 220 return; 221 } 222 223 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 224 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 225 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 226 epit_table[i].irq)); 227 } 228 229 /* Initialize all I2C */ 230 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 231 static const struct { 232 hwaddr addr; 233 unsigned int irq; 234 } i2c_table[FSL_IMX6_NUM_I2CS] = { 235 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ }, 236 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ }, 237 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ } 238 }; 239 240 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) { 241 return; 242 } 243 244 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 245 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 246 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 247 i2c_table[i].irq)); 248 } 249 250 /* Initialize all GPIOs */ 251 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 252 static const struct { 253 hwaddr addr; 254 unsigned int irq_low; 255 unsigned int irq_high; 256 } gpio_table[FSL_IMX6_NUM_GPIOS] = { 257 { 258 FSL_IMX6_GPIO1_ADDR, 259 FSL_IMX6_GPIO1_LOW_IRQ, 260 FSL_IMX6_GPIO1_HIGH_IRQ 261 }, 262 { 263 FSL_IMX6_GPIO2_ADDR, 264 FSL_IMX6_GPIO2_LOW_IRQ, 265 FSL_IMX6_GPIO2_HIGH_IRQ 266 }, 267 { 268 FSL_IMX6_GPIO3_ADDR, 269 FSL_IMX6_GPIO3_LOW_IRQ, 270 FSL_IMX6_GPIO3_HIGH_IRQ 271 }, 272 { 273 FSL_IMX6_GPIO4_ADDR, 274 FSL_IMX6_GPIO4_LOW_IRQ, 275 FSL_IMX6_GPIO4_HIGH_IRQ 276 }, 277 { 278 FSL_IMX6_GPIO5_ADDR, 279 FSL_IMX6_GPIO5_LOW_IRQ, 280 FSL_IMX6_GPIO5_HIGH_IRQ 281 }, 282 { 283 FSL_IMX6_GPIO6_ADDR, 284 FSL_IMX6_GPIO6_LOW_IRQ, 285 FSL_IMX6_GPIO6_HIGH_IRQ 286 }, 287 { 288 FSL_IMX6_GPIO7_ADDR, 289 FSL_IMX6_GPIO7_LOW_IRQ, 290 FSL_IMX6_GPIO7_HIGH_IRQ 291 }, 292 }; 293 294 object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, 295 &error_abort); 296 object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", 297 true, &error_abort); 298 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { 299 return; 300 } 301 302 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 303 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 304 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 305 gpio_table[i].irq_low)); 306 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 307 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 308 gpio_table[i].irq_high)); 309 } 310 311 /* Initialize all SDHC */ 312 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 313 static const struct { 314 hwaddr addr; 315 unsigned int irq; 316 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = { 317 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ }, 318 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ }, 319 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ }, 320 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ }, 321 }; 322 323 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */ 324 object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 3, 325 &error_abort); 326 object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", 327 IMX6_ESDHC_CAPABILITIES, &error_abort); 328 object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", 329 SDHCI_VENDOR_IMX, &error_abort); 330 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) { 331 return; 332 } 333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); 334 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, 335 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 336 esdhc_table[i].irq)); 337 } 338 339 /* USB */ 340 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { 341 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); 342 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, 343 FSL_IMX6_USBPHY1_ADDR + i * 0x1000); 344 } 345 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { 346 static const int FSL_IMX6_USBn_IRQ[] = { 347 FSL_IMX6_USB_OTG_IRQ, 348 FSL_IMX6_USB_HOST1_IRQ, 349 FSL_IMX6_USB_HOST2_IRQ, 350 FSL_IMX6_USB_HOST3_IRQ, 351 }; 352 353 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); 354 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 355 FSL_IMX6_USBOH3_USB_ADDR + i * 0x200); 356 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, 357 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 358 FSL_IMX6_USBn_IRQ[i])); 359 } 360 361 /* Initialize all ECSPI */ 362 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 363 static const struct { 364 hwaddr addr; 365 unsigned int irq; 366 } spi_table[FSL_IMX6_NUM_ECSPIS] = { 367 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ }, 368 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ }, 369 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ }, 370 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ }, 371 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ }, 372 }; 373 374 /* Initialize the SPI */ 375 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 376 return; 377 } 378 379 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); 380 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 381 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 382 spi_table[i].irq)); 383 } 384 385 object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, 386 &error_abort); 387 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); 388 if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) { 389 return; 390 } 391 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); 392 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, 393 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 394 FSL_IMX6_ENET_MAC_IRQ)); 395 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, 396 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 397 FSL_IMX6_ENET_MAC_1588_IRQ)); 398 399 /* 400 * SNVS 401 */ 402 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); 403 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6_SNVSHP_ADDR); 404 405 /* 406 * Watchdog 407 */ 408 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { 409 static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = { 410 FSL_IMX6_WDOG1_ADDR, 411 FSL_IMX6_WDOG2_ADDR, 412 }; 413 static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = { 414 FSL_IMX6_WDOG1_IRQ, 415 FSL_IMX6_WDOG2_IRQ, 416 }; 417 418 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", 419 true, &error_abort); 420 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 421 422 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]); 423 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, 424 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 425 FSL_IMX6_WDOGn_IRQ[i])); 426 } 427 428 /* ROM memory */ 429 if (!memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom", 430 FSL_IMX6_ROM_SIZE, errp)) { 431 return; 432 } 433 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR, 434 &s->rom); 435 436 /* CAAM memory */ 437 if (!memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam", 438 FSL_IMX6_CAAM_MEM_SIZE, errp)) { 439 return; 440 } 441 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR, 442 &s->caam); 443 444 /* OCRAM memory */ 445 if (!memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", 446 FSL_IMX6_OCRAM_SIZE, errp)) { 447 return; 448 } 449 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR, 450 &s->ocram); 451 452 /* internal OCRAM (256 KB) is aliased over 1 MB */ 453 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias", 454 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE); 455 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR, 456 &s->ocram_alias); 457 } 458 459 static Property fsl_imx6_properties[] = { 460 DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0), 461 DEFINE_PROP_END_OF_LIST(), 462 }; 463 464 static void fsl_imx6_class_init(ObjectClass *oc, void *data) 465 { 466 DeviceClass *dc = DEVICE_CLASS(oc); 467 468 device_class_set_props(dc, fsl_imx6_properties); 469 dc->realize = fsl_imx6_realize; 470 dc->desc = "i.MX6 SOC"; 471 /* Reason: Uses serial_hd() in the realize() function */ 472 dc->user_creatable = false; 473 } 474 475 static const TypeInfo fsl_imx6_type_info = { 476 .name = TYPE_FSL_IMX6, 477 .parent = TYPE_DEVICE, 478 .instance_size = sizeof(FslIMX6State), 479 .instance_init = fsl_imx6_init, 480 .class_init = fsl_imx6_class_init, 481 }; 482 483 static void fsl_imx6_register_types(void) 484 { 485 type_register_static(&fsl_imx6_type_info); 486 } 487 488 type_init(fsl_imx6_register_types) 489