1 /* 2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/arm/fsl-imx6.h" 25 #include "hw/usb/imx-usb-phy.h" 26 #include "hw/boards.h" 27 #include "hw/qdev-properties.h" 28 #include "sysemu/sysemu.h" 29 #include "chardev/char.h" 30 #include "qemu/error-report.h" 31 #include "qemu/module.h" 32 33 #define IMX6_ESDHC_CAPABILITIES 0x057834b4 34 35 #define NAME_SIZE 20 36 37 static void fsl_imx6_init(Object *obj) 38 { 39 MachineState *ms = MACHINE(qdev_get_machine()); 40 FslIMX6State *s = FSL_IMX6(obj); 41 char name[NAME_SIZE]; 42 int i; 43 44 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) { 45 snprintf(name, NAME_SIZE, "cpu%d", i); 46 object_initialize_child(obj, name, &s->cpu[i], 47 ARM_CPU_TYPE_NAME("cortex-a9")); 48 } 49 50 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 51 52 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM); 53 54 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC); 55 56 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); 57 58 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 59 snprintf(name, NAME_SIZE, "uart%d", i + 1); 60 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); 61 } 62 63 object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT); 64 65 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 66 snprintf(name, NAME_SIZE, "epit%d", i + 1); 67 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT); 68 } 69 70 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 71 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 72 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); 73 } 74 75 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 76 snprintf(name, NAME_SIZE, "gpio%d", i + 1); 77 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); 78 } 79 80 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 81 snprintf(name, NAME_SIZE, "sdhc%d", i + 1); 82 object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC); 83 } 84 85 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { 86 snprintf(name, NAME_SIZE, "usbphy%d", i); 87 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); 88 } 89 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { 90 snprintf(name, NAME_SIZE, "usb%d", i); 91 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); 92 } 93 94 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 95 snprintf(name, NAME_SIZE, "spi%d", i + 1); 96 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); 97 } 98 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { 99 snprintf(name, NAME_SIZE, "wdt%d", i); 100 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); 101 } 102 103 104 object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET); 105 } 106 107 static void fsl_imx6_realize(DeviceState *dev, Error **errp) 108 { 109 MachineState *ms = MACHINE(qdev_get_machine()); 110 FslIMX6State *s = FSL_IMX6(dev); 111 uint16_t i; 112 Error *err = NULL; 113 unsigned int smp_cpus = ms->smp.cpus; 114 115 if (smp_cpus > FSL_IMX6_NUM_CPUS) { 116 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", 117 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus); 118 return; 119 } 120 121 for (i = 0; i < smp_cpus; i++) { 122 123 /* On uniprocessor, the CBAR is set to 0 */ 124 if (smp_cpus > 1) { 125 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 126 FSL_IMX6_A9MPCORE_ADDR, &error_abort); 127 } 128 129 /* All CPU but CPU 0 start in power off mode */ 130 if (i) { 131 object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off", 132 true, &error_abort); 133 } 134 135 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 136 return; 137 } 138 } 139 140 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus, 141 &error_abort); 142 143 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", 144 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort); 145 146 if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) { 147 return; 148 } 149 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); 150 151 for (i = 0; i < smp_cpus; i++) { 152 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 153 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 154 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, 155 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 156 } 157 158 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { 159 return; 160 } 161 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); 162 163 if (!sysbus_realize(SYS_BUS_DEVICE(&s->src), errp)) { 164 return; 165 } 166 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR); 167 168 /* Initialize all UARTs */ 169 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 170 static const struct { 171 hwaddr addr; 172 unsigned int irq; 173 } serial_table[FSL_IMX6_NUM_UARTS] = { 174 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ }, 175 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ }, 176 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ }, 177 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ }, 178 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, 179 }; 180 181 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 182 183 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 184 return; 185 } 186 187 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 188 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 189 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 190 serial_table[i].irq)); 191 } 192 193 s->gpt.ccm = IMX_CCM(&s->ccm); 194 195 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) { 196 return; 197 } 198 199 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); 200 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 201 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 202 FSL_IMX6_GPT_IRQ)); 203 204 /* Initialize all EPIT timers */ 205 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 206 static const struct { 207 hwaddr addr; 208 unsigned int irq; 209 } epit_table[FSL_IMX6_NUM_EPITS] = { 210 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ }, 211 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ }, 212 }; 213 214 s->epit[i].ccm = IMX_CCM(&s->ccm); 215 216 if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) { 217 return; 218 } 219 220 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 221 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 222 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 223 epit_table[i].irq)); 224 } 225 226 /* Initialize all I2C */ 227 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 228 static const struct { 229 hwaddr addr; 230 unsigned int irq; 231 } i2c_table[FSL_IMX6_NUM_I2CS] = { 232 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ }, 233 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ }, 234 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ } 235 }; 236 237 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) { 238 return; 239 } 240 241 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 242 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 243 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 244 i2c_table[i].irq)); 245 } 246 247 /* Initialize all GPIOs */ 248 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 249 static const struct { 250 hwaddr addr; 251 unsigned int irq_low; 252 unsigned int irq_high; 253 } gpio_table[FSL_IMX6_NUM_GPIOS] = { 254 { 255 FSL_IMX6_GPIO1_ADDR, 256 FSL_IMX6_GPIO1_LOW_IRQ, 257 FSL_IMX6_GPIO1_HIGH_IRQ 258 }, 259 { 260 FSL_IMX6_GPIO2_ADDR, 261 FSL_IMX6_GPIO2_LOW_IRQ, 262 FSL_IMX6_GPIO2_HIGH_IRQ 263 }, 264 { 265 FSL_IMX6_GPIO3_ADDR, 266 FSL_IMX6_GPIO3_LOW_IRQ, 267 FSL_IMX6_GPIO3_HIGH_IRQ 268 }, 269 { 270 FSL_IMX6_GPIO4_ADDR, 271 FSL_IMX6_GPIO4_LOW_IRQ, 272 FSL_IMX6_GPIO4_HIGH_IRQ 273 }, 274 { 275 FSL_IMX6_GPIO5_ADDR, 276 FSL_IMX6_GPIO5_LOW_IRQ, 277 FSL_IMX6_GPIO5_HIGH_IRQ 278 }, 279 { 280 FSL_IMX6_GPIO6_ADDR, 281 FSL_IMX6_GPIO6_LOW_IRQ, 282 FSL_IMX6_GPIO6_HIGH_IRQ 283 }, 284 { 285 FSL_IMX6_GPIO7_ADDR, 286 FSL_IMX6_GPIO7_LOW_IRQ, 287 FSL_IMX6_GPIO7_HIGH_IRQ 288 }, 289 }; 290 291 object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, 292 &error_abort); 293 object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", 294 true, &error_abort); 295 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { 296 return; 297 } 298 299 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 300 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 301 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 302 gpio_table[i].irq_low)); 303 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 304 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 305 gpio_table[i].irq_high)); 306 } 307 308 /* Initialize all SDHC */ 309 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 310 static const struct { 311 hwaddr addr; 312 unsigned int irq; 313 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = { 314 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ }, 315 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ }, 316 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ }, 317 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ }, 318 }; 319 320 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */ 321 object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 3, 322 &error_abort); 323 object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", 324 IMX6_ESDHC_CAPABILITIES, &error_abort); 325 object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", 326 SDHCI_VENDOR_IMX, &error_abort); 327 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) { 328 return; 329 } 330 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); 331 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, 332 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 333 esdhc_table[i].irq)); 334 } 335 336 /* USB */ 337 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { 338 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); 339 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, 340 FSL_IMX6_USBPHY1_ADDR + i * 0x1000); 341 } 342 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { 343 static const int FSL_IMX6_USBn_IRQ[] = { 344 FSL_IMX6_USB_OTG_IRQ, 345 FSL_IMX6_USB_HOST1_IRQ, 346 FSL_IMX6_USB_HOST2_IRQ, 347 FSL_IMX6_USB_HOST3_IRQ, 348 }; 349 350 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); 351 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 352 FSL_IMX6_USBOH3_USB_ADDR + i * 0x200); 353 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, 354 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 355 FSL_IMX6_USBn_IRQ[i])); 356 } 357 358 /* Initialize all ECSPI */ 359 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 360 static const struct { 361 hwaddr addr; 362 unsigned int irq; 363 } spi_table[FSL_IMX6_NUM_ECSPIS] = { 364 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ }, 365 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ }, 366 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ }, 367 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ }, 368 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ }, 369 }; 370 371 /* Initialize the SPI */ 372 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 373 return; 374 } 375 376 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); 377 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 378 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 379 spi_table[i].irq)); 380 } 381 382 object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err); 383 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); 384 if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) { 385 return; 386 } 387 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); 388 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, 389 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 390 FSL_IMX6_ENET_MAC_IRQ)); 391 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, 392 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 393 FSL_IMX6_ENET_MAC_1588_IRQ)); 394 395 /* 396 * SNVS 397 */ 398 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); 399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6_SNVSHP_ADDR); 400 401 /* 402 * Watchdog 403 */ 404 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { 405 static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = { 406 FSL_IMX6_WDOG1_ADDR, 407 FSL_IMX6_WDOG2_ADDR, 408 }; 409 static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = { 410 FSL_IMX6_WDOG1_IRQ, 411 FSL_IMX6_WDOG2_IRQ, 412 }; 413 414 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", 415 true, &error_abort); 416 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 417 418 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]); 419 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, 420 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 421 FSL_IMX6_WDOGn_IRQ[i])); 422 } 423 424 /* ROM memory */ 425 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom", 426 FSL_IMX6_ROM_SIZE, &err); 427 if (err) { 428 error_propagate(errp, err); 429 return; 430 } 431 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR, 432 &s->rom); 433 434 /* CAAM memory */ 435 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam", 436 FSL_IMX6_CAAM_MEM_SIZE, &err); 437 if (err) { 438 error_propagate(errp, err); 439 return; 440 } 441 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR, 442 &s->caam); 443 444 /* OCRAM memory */ 445 memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE, 446 &err); 447 if (err) { 448 error_propagate(errp, err); 449 return; 450 } 451 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR, 452 &s->ocram); 453 454 /* internal OCRAM (256 KB) is aliased over 1 MB */ 455 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias", 456 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE); 457 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR, 458 &s->ocram_alias); 459 } 460 461 static Property fsl_imx6_properties[] = { 462 DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0), 463 DEFINE_PROP_END_OF_LIST(), 464 }; 465 466 static void fsl_imx6_class_init(ObjectClass *oc, void *data) 467 { 468 DeviceClass *dc = DEVICE_CLASS(oc); 469 470 device_class_set_props(dc, fsl_imx6_properties); 471 dc->realize = fsl_imx6_realize; 472 dc->desc = "i.MX6 SOC"; 473 /* Reason: Uses serial_hd() in the realize() function */ 474 dc->user_creatable = false; 475 } 476 477 static const TypeInfo fsl_imx6_type_info = { 478 .name = TYPE_FSL_IMX6, 479 .parent = TYPE_DEVICE, 480 .instance_size = sizeof(FslIMX6State), 481 .instance_init = fsl_imx6_init, 482 .class_init = fsl_imx6_class_init, 483 }; 484 485 static void fsl_imx6_register_types(void) 486 { 487 type_register_static(&fsl_imx6_type_info); 488 } 489 490 type_init(fsl_imx6_register_types) 491