1 /* 2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/arm/fsl-imx6.h" 25 #include "sysemu/sysemu.h" 26 #include "chardev/char.h" 27 #include "qemu/error-report.h" 28 #include "qemu/module.h" 29 30 #define IMX6_ESDHC_CAPABILITIES 0x057834b4 31 32 #define NAME_SIZE 20 33 34 static void fsl_imx6_init(Object *obj) 35 { 36 FslIMX6State *s = FSL_IMX6(obj); 37 char name[NAME_SIZE]; 38 int i; 39 40 for (i = 0; i < MIN(smp_cpus, FSL_IMX6_NUM_CPUS); i++) { 41 snprintf(name, NAME_SIZE, "cpu%d", i); 42 object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]), 43 "cortex-a9-" TYPE_ARM_CPU, &error_abort, NULL); 44 } 45 46 sysbus_init_child_obj(obj, "a9mpcore", &s->a9mpcore, sizeof(s->a9mpcore), 47 TYPE_A9MPCORE_PRIV); 48 49 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM); 50 51 sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC); 52 53 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 54 snprintf(name, NAME_SIZE, "uart%d", i + 1); 55 sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]), 56 TYPE_IMX_SERIAL); 57 } 58 59 sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT); 60 61 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 62 snprintf(name, NAME_SIZE, "epit%d", i + 1); 63 sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]), 64 TYPE_IMX_EPIT); 65 } 66 67 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 68 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 69 sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]), 70 TYPE_IMX_I2C); 71 } 72 73 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 74 snprintf(name, NAME_SIZE, "gpio%d", i + 1); 75 sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]), 76 TYPE_IMX_GPIO); 77 } 78 79 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 80 snprintf(name, NAME_SIZE, "sdhc%d", i + 1); 81 sysbus_init_child_obj(obj, name, &s->esdhc[i], sizeof(s->esdhc[i]), 82 TYPE_IMX_USDHC); 83 } 84 85 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 86 snprintf(name, NAME_SIZE, "spi%d", i + 1); 87 sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]), 88 TYPE_IMX_SPI); 89 } 90 91 sysbus_init_child_obj(obj, "eth", &s->eth, sizeof(s->eth), TYPE_IMX_ENET); 92 } 93 94 static void fsl_imx6_realize(DeviceState *dev, Error **errp) 95 { 96 FslIMX6State *s = FSL_IMX6(dev); 97 uint16_t i; 98 Error *err = NULL; 99 100 if (smp_cpus > FSL_IMX6_NUM_CPUS) { 101 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", 102 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus); 103 return; 104 } 105 106 for (i = 0; i < smp_cpus; i++) { 107 108 /* On uniprocessor, the CBAR is set to 0 */ 109 if (smp_cpus > 1) { 110 object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR, 111 "reset-cbar", &error_abort); 112 } 113 114 /* All CPU but CPU 0 start in power off mode */ 115 if (i) { 116 object_property_set_bool(OBJECT(&s->cpu[i]), true, 117 "start-powered-off", &error_abort); 118 } 119 120 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 121 if (err) { 122 error_propagate(errp, err); 123 return; 124 } 125 } 126 127 object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu", 128 &error_abort); 129 130 object_property_set_int(OBJECT(&s->a9mpcore), 131 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq", 132 &error_abort); 133 134 object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err); 135 if (err) { 136 error_propagate(errp, err); 137 return; 138 } 139 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); 140 141 for (i = 0; i < smp_cpus; i++) { 142 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 143 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 144 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, 145 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 146 } 147 148 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 149 if (err) { 150 error_propagate(errp, err); 151 return; 152 } 153 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); 154 155 object_property_set_bool(OBJECT(&s->src), true, "realized", &err); 156 if (err) { 157 error_propagate(errp, err); 158 return; 159 } 160 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR); 161 162 /* Initialize all UARTs */ 163 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 164 static const struct { 165 hwaddr addr; 166 unsigned int irq; 167 } serial_table[FSL_IMX6_NUM_UARTS] = { 168 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ }, 169 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ }, 170 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ }, 171 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ }, 172 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, 173 }; 174 175 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 176 177 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 178 if (err) { 179 error_propagate(errp, err); 180 return; 181 } 182 183 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 184 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 185 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 186 serial_table[i].irq)); 187 } 188 189 s->gpt.ccm = IMX_CCM(&s->ccm); 190 191 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); 192 if (err) { 193 error_propagate(errp, err); 194 return; 195 } 196 197 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); 198 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 199 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 200 FSL_IMX6_GPT_IRQ)); 201 202 /* Initialize all EPIT timers */ 203 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 204 static const struct { 205 hwaddr addr; 206 unsigned int irq; 207 } epit_table[FSL_IMX6_NUM_EPITS] = { 208 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ }, 209 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ }, 210 }; 211 212 s->epit[i].ccm = IMX_CCM(&s->ccm); 213 214 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 215 if (err) { 216 error_propagate(errp, err); 217 return; 218 } 219 220 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 221 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 222 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 223 epit_table[i].irq)); 224 } 225 226 /* Initialize all I2C */ 227 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 228 static const struct { 229 hwaddr addr; 230 unsigned int irq; 231 } i2c_table[FSL_IMX6_NUM_I2CS] = { 232 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ }, 233 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ }, 234 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ } 235 }; 236 237 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 238 if (err) { 239 error_propagate(errp, err); 240 return; 241 } 242 243 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 244 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 245 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 246 i2c_table[i].irq)); 247 } 248 249 /* Initialize all GPIOs */ 250 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 251 static const struct { 252 hwaddr addr; 253 unsigned int irq_low; 254 unsigned int irq_high; 255 } gpio_table[FSL_IMX6_NUM_GPIOS] = { 256 { 257 FSL_IMX6_GPIO1_ADDR, 258 FSL_IMX6_GPIO1_LOW_IRQ, 259 FSL_IMX6_GPIO1_HIGH_IRQ 260 }, 261 { 262 FSL_IMX6_GPIO2_ADDR, 263 FSL_IMX6_GPIO2_LOW_IRQ, 264 FSL_IMX6_GPIO2_HIGH_IRQ 265 }, 266 { 267 FSL_IMX6_GPIO3_ADDR, 268 FSL_IMX6_GPIO3_LOW_IRQ, 269 FSL_IMX6_GPIO3_HIGH_IRQ 270 }, 271 { 272 FSL_IMX6_GPIO4_ADDR, 273 FSL_IMX6_GPIO4_LOW_IRQ, 274 FSL_IMX6_GPIO4_HIGH_IRQ 275 }, 276 { 277 FSL_IMX6_GPIO5_ADDR, 278 FSL_IMX6_GPIO5_LOW_IRQ, 279 FSL_IMX6_GPIO5_HIGH_IRQ 280 }, 281 { 282 FSL_IMX6_GPIO6_ADDR, 283 FSL_IMX6_GPIO6_LOW_IRQ, 284 FSL_IMX6_GPIO6_HIGH_IRQ 285 }, 286 { 287 FSL_IMX6_GPIO7_ADDR, 288 FSL_IMX6_GPIO7_LOW_IRQ, 289 FSL_IMX6_GPIO7_HIGH_IRQ 290 }, 291 }; 292 293 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel", 294 &error_abort); 295 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq", 296 &error_abort); 297 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); 298 if (err) { 299 error_propagate(errp, err); 300 return; 301 } 302 303 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 304 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 305 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 306 gpio_table[i].irq_low)); 307 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 308 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 309 gpio_table[i].irq_high)); 310 } 311 312 /* Initialize all SDHC */ 313 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 314 static const struct { 315 hwaddr addr; 316 unsigned int irq; 317 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = { 318 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ }, 319 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ }, 320 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ }, 321 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ }, 322 }; 323 324 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */ 325 object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version", 326 &err); 327 object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES, 328 "capareg", &err); 329 object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err); 330 if (err) { 331 error_propagate(errp, err); 332 return; 333 } 334 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); 335 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, 336 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 337 esdhc_table[i].irq)); 338 } 339 340 /* Initialize all ECSPI */ 341 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 342 static const struct { 343 hwaddr addr; 344 unsigned int irq; 345 } spi_table[FSL_IMX6_NUM_ECSPIS] = { 346 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ }, 347 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ }, 348 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ }, 349 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ }, 350 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ }, 351 }; 352 353 /* Initialize the SPI */ 354 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 355 if (err) { 356 error_propagate(errp, err); 357 return; 358 } 359 360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); 361 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 362 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 363 spi_table[i].irq)); 364 } 365 366 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); 367 object_property_set_bool(OBJECT(&s->eth), true, "realized", &err); 368 if (err) { 369 error_propagate(errp, err); 370 return; 371 } 372 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); 373 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, 374 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 375 FSL_IMX6_ENET_MAC_IRQ)); 376 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, 377 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 378 FSL_IMX6_ENET_MAC_1588_IRQ)); 379 380 /* ROM memory */ 381 memory_region_init_rom(&s->rom, NULL, "imx6.rom", 382 FSL_IMX6_ROM_SIZE, &err); 383 if (err) { 384 error_propagate(errp, err); 385 return; 386 } 387 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR, 388 &s->rom); 389 390 /* CAAM memory */ 391 memory_region_init_rom(&s->caam, NULL, "imx6.caam", 392 FSL_IMX6_CAAM_MEM_SIZE, &err); 393 if (err) { 394 error_propagate(errp, err); 395 return; 396 } 397 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR, 398 &s->caam); 399 400 /* OCRAM memory */ 401 memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE, 402 &err); 403 if (err) { 404 error_propagate(errp, err); 405 return; 406 } 407 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR, 408 &s->ocram); 409 410 /* internal OCRAM (256 KB) is aliased over 1 MB */ 411 memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias", 412 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE); 413 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR, 414 &s->ocram_alias); 415 } 416 417 static void fsl_imx6_class_init(ObjectClass *oc, void *data) 418 { 419 DeviceClass *dc = DEVICE_CLASS(oc); 420 421 dc->realize = fsl_imx6_realize; 422 dc->desc = "i.MX6 SOC"; 423 /* Reason: Uses serial_hd() in the realize() function */ 424 dc->user_creatable = false; 425 } 426 427 static const TypeInfo fsl_imx6_type_info = { 428 .name = TYPE_FSL_IMX6, 429 .parent = TYPE_DEVICE, 430 .instance_size = sizeof(FslIMX6State), 431 .instance_init = fsl_imx6_init, 432 .class_init = fsl_imx6_class_init, 433 }; 434 435 static void fsl_imx6_register_types(void) 436 { 437 type_register_static(&fsl_imx6_type_info); 438 } 439 440 type_init(fsl_imx6_register_types) 441