1 /* 2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX31 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu-common.h" 25 #include "cpu.h" 26 #include "hw/arm/fsl-imx31.h" 27 #include "sysemu/sysemu.h" 28 #include "exec/address-spaces.h" 29 #include "hw/boards.h" 30 #include "chardev/char.h" 31 32 static void fsl_imx31_init(Object *obj) 33 { 34 FslIMX31State *s = FSL_IMX31(obj); 35 int i; 36 37 object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU); 38 39 object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC); 40 qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default()); 41 42 object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM); 43 qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default()); 44 45 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { 46 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); 47 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 48 } 49 50 object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT); 51 qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default()); 52 53 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { 54 object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); 55 qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); 56 } 57 58 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { 59 object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); 60 qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); 61 } 62 63 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { 64 object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); 65 qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default()); 66 } 67 } 68 69 static void fsl_imx31_realize(DeviceState *dev, Error **errp) 70 { 71 FslIMX31State *s = FSL_IMX31(dev); 72 uint16_t i; 73 Error *err = NULL; 74 75 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 76 if (err) { 77 error_propagate(errp, err); 78 return; 79 } 80 81 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); 82 if (err) { 83 error_propagate(errp, err); 84 return; 85 } 86 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR); 87 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, 88 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 89 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, 90 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 91 92 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 93 if (err) { 94 error_propagate(errp, err); 95 return; 96 } 97 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR); 98 99 /* Initialize all UARTS */ 100 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { 101 static const struct { 102 hwaddr addr; 103 unsigned int irq; 104 } serial_table[FSL_IMX31_NUM_UARTS] = { 105 { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ }, 106 { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ }, 107 }; 108 109 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 110 111 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 112 if (err) { 113 error_propagate(errp, err); 114 return; 115 } 116 117 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 118 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 119 qdev_get_gpio_in(DEVICE(&s->avic), 120 serial_table[i].irq)); 121 } 122 123 s->gpt.ccm = IMX_CCM(&s->ccm); 124 125 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); 126 if (err) { 127 error_propagate(errp, err); 128 return; 129 } 130 131 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR); 132 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 133 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ)); 134 135 /* Initialize all EPIT timers */ 136 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { 137 static const struct { 138 hwaddr addr; 139 unsigned int irq; 140 } epit_table[FSL_IMX31_NUM_EPITS] = { 141 { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ }, 142 { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ }, 143 }; 144 145 s->epit[i].ccm = IMX_CCM(&s->ccm); 146 147 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 148 if (err) { 149 error_propagate(errp, err); 150 return; 151 } 152 153 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 154 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 155 qdev_get_gpio_in(DEVICE(&s->avic), 156 epit_table[i].irq)); 157 } 158 159 /* Initialize all I2C */ 160 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { 161 static const struct { 162 hwaddr addr; 163 unsigned int irq; 164 } i2c_table[FSL_IMX31_NUM_I2CS] = { 165 { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ }, 166 { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ }, 167 { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ } 168 }; 169 170 /* Initialize the I2C */ 171 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 172 if (err) { 173 error_propagate(errp, err); 174 return; 175 } 176 /* Map I2C memory */ 177 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 178 /* Connect I2C IRQ to PIC */ 179 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 180 qdev_get_gpio_in(DEVICE(&s->avic), 181 i2c_table[i].irq)); 182 } 183 184 /* Initialize all GPIOs */ 185 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { 186 static const struct { 187 hwaddr addr; 188 unsigned int irq; 189 } gpio_table[FSL_IMX31_NUM_GPIOS] = { 190 { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ }, 191 { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ }, 192 { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ } 193 }; 194 195 object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel", 196 &error_abort); 197 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); 198 if (err) { 199 error_propagate(errp, err); 200 return; 201 } 202 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 203 /* Connect GPIO IRQ to PIC */ 204 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 205 qdev_get_gpio_in(DEVICE(&s->avic), 206 gpio_table[i].irq)); 207 } 208 209 /* On a real system, the first 16k is a `secure boot rom' */ 210 memory_region_init_rom(&s->secure_rom, NULL, "imx31.secure_rom", 211 FSL_IMX31_SECURE_ROM_SIZE, &err); 212 if (err) { 213 error_propagate(errp, err); 214 return; 215 } 216 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR, 217 &s->secure_rom); 218 219 /* There is also a 16k ROM */ 220 memory_region_init_rom(&s->rom, NULL, "imx31.rom", 221 FSL_IMX31_ROM_SIZE, &err); 222 if (err) { 223 error_propagate(errp, err); 224 return; 225 } 226 memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR, 227 &s->rom); 228 229 /* initialize internal RAM (16 KB) */ 230 memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE, 231 &err); 232 if (err) { 233 error_propagate(errp, err); 234 return; 235 } 236 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR, 237 &s->iram); 238 239 /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */ 240 memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias", 241 &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE); 242 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR, 243 &s->iram_alias); 244 } 245 246 static void fsl_imx31_class_init(ObjectClass *oc, void *data) 247 { 248 DeviceClass *dc = DEVICE_CLASS(oc); 249 250 dc->realize = fsl_imx31_realize; 251 dc->desc = "i.MX31 SOC"; 252 /* 253 * Reason: uses serial_hds in realize and the kzm board does not 254 * support multiple CPUs 255 */ 256 dc->user_creatable = false; 257 } 258 259 static const TypeInfo fsl_imx31_type_info = { 260 .name = TYPE_FSL_IMX31, 261 .parent = TYPE_DEVICE, 262 .instance_size = sizeof(FslIMX31State), 263 .instance_init = fsl_imx31_init, 264 .class_init = fsl_imx31_class_init, 265 }; 266 267 static void fsl_imx31_register_types(void) 268 { 269 type_register_static(&fsl_imx31_type_info); 270 } 271 272 type_init(fsl_imx31_register_types) 273