1 /* 2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX31 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/arm/fsl-imx31.h" 25 #include "sysemu/sysemu.h" 26 #include "exec/address-spaces.h" 27 #include "hw/qdev-properties.h" 28 #include "chardev/char.h" 29 30 static void fsl_imx31_init(Object *obj) 31 { 32 FslIMX31State *s = FSL_IMX31(obj); 33 int i; 34 35 object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm1136")); 36 37 object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC); 38 39 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX31_CCM); 40 41 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { 42 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL); 43 } 44 45 object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX31_GPT); 46 47 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { 48 object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT); 49 } 50 51 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { 52 object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C); 53 } 54 55 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { 56 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO); 57 } 58 59 object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT); 60 } 61 62 static void fsl_imx31_realize(DeviceState *dev, Error **errp) 63 { 64 FslIMX31State *s = FSL_IMX31(dev); 65 uint16_t i; 66 67 if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { 68 return; 69 } 70 71 if (!sysbus_realize(SYS_BUS_DEVICE(&s->avic), errp)) { 72 return; 73 } 74 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR); 75 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, 76 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 77 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, 78 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 79 80 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { 81 return; 82 } 83 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR); 84 85 /* Initialize all UARTS */ 86 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { 87 static const struct { 88 hwaddr addr; 89 unsigned int irq; 90 } serial_table[FSL_IMX31_NUM_UARTS] = { 91 { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ }, 92 { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ }, 93 }; 94 95 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 96 97 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 98 return; 99 } 100 101 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 102 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 103 qdev_get_gpio_in(DEVICE(&s->avic), 104 serial_table[i].irq)); 105 } 106 107 s->gpt.ccm = IMX_CCM(&s->ccm); 108 109 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) { 110 return; 111 } 112 113 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR); 114 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 115 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ)); 116 117 /* Initialize all EPIT timers */ 118 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { 119 static const struct { 120 hwaddr addr; 121 unsigned int irq; 122 } epit_table[FSL_IMX31_NUM_EPITS] = { 123 { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ }, 124 { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ }, 125 }; 126 127 s->epit[i].ccm = IMX_CCM(&s->ccm); 128 129 if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) { 130 return; 131 } 132 133 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 134 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 135 qdev_get_gpio_in(DEVICE(&s->avic), 136 epit_table[i].irq)); 137 } 138 139 /* Initialize all I2C */ 140 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { 141 static const struct { 142 hwaddr addr; 143 unsigned int irq; 144 } i2c_table[FSL_IMX31_NUM_I2CS] = { 145 { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ }, 146 { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ }, 147 { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ } 148 }; 149 150 /* Initialize the I2C */ 151 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) { 152 return; 153 } 154 /* Map I2C memory */ 155 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 156 /* Connect I2C IRQ to PIC */ 157 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 158 qdev_get_gpio_in(DEVICE(&s->avic), 159 i2c_table[i].irq)); 160 } 161 162 /* Initialize all GPIOs */ 163 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { 164 static const struct { 165 hwaddr addr; 166 unsigned int irq; 167 } gpio_table[FSL_IMX31_NUM_GPIOS] = { 168 { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ }, 169 { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ }, 170 { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ } 171 }; 172 173 object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", false, 174 &error_abort); 175 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { 176 return; 177 } 178 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 179 /* Connect GPIO IRQ to PIC */ 180 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 181 qdev_get_gpio_in(DEVICE(&s->avic), 182 gpio_table[i].irq)); 183 } 184 185 /* Watchdog */ 186 sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort); 187 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR); 188 189 /* On a real system, the first 16k is a `secure boot rom' */ 190 if (!memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom", 191 FSL_IMX31_SECURE_ROM_SIZE, errp)) { 192 return; 193 } 194 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR, 195 &s->secure_rom); 196 197 /* There is also a 16k ROM */ 198 if (!memory_region_init_rom(&s->rom, OBJECT(dev), "imx31.rom", 199 FSL_IMX31_ROM_SIZE, errp)) { 200 return; 201 } 202 memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR, 203 &s->rom); 204 205 /* initialize internal RAM (16 KB) */ 206 if (!memory_region_init_ram(&s->iram, NULL, "imx31.iram", 207 FSL_IMX31_IRAM_SIZE, errp)) { 208 return; 209 } 210 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR, 211 &s->iram); 212 213 /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */ 214 memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx31.iram_alias", 215 &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE); 216 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR, 217 &s->iram_alias); 218 } 219 220 static void fsl_imx31_class_init(ObjectClass *oc, void *data) 221 { 222 DeviceClass *dc = DEVICE_CLASS(oc); 223 224 dc->realize = fsl_imx31_realize; 225 dc->desc = "i.MX31 SOC"; 226 /* 227 * Reason: uses serial_hds in realize and the kzm board does not 228 * support multiple CPUs 229 */ 230 dc->user_creatable = false; 231 } 232 233 static const TypeInfo fsl_imx31_type_info = { 234 .name = TYPE_FSL_IMX31, 235 .parent = TYPE_DEVICE, 236 .instance_size = sizeof(FslIMX31State), 237 .instance_init = fsl_imx31_init, 238 .class_init = fsl_imx31_class_init, 239 }; 240 241 static void fsl_imx31_register_types(void) 242 { 243 type_register_static(&fsl_imx31_type_info); 244 } 245 246 type_init(fsl_imx31_register_types) 247