1 /* 2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX31 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "hw/arm/fsl-imx31.h" 23 #include "sysemu/sysemu.h" 24 #include "exec/address-spaces.h" 25 #include "hw/boards.h" 26 #include "sysemu/char.h" 27 28 static void fsl_imx31_init(Object *obj) 29 { 30 FslIMX31State *s = FSL_IMX31(obj); 31 int i; 32 33 object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU); 34 35 object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC); 36 qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default()); 37 38 object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX_CCM); 39 qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default()); 40 41 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { 42 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); 43 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 44 } 45 46 object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT); 47 qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default()); 48 49 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { 50 object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); 51 qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); 52 } 53 54 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { 55 object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); 56 qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); 57 } 58 59 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { 60 object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); 61 qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default()); 62 } 63 } 64 65 static void fsl_imx31_realize(DeviceState *dev, Error **errp) 66 { 67 FslIMX31State *s = FSL_IMX31(dev); 68 uint16_t i; 69 Error *err = NULL; 70 71 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 72 if (err) { 73 error_propagate(errp, err); 74 return; 75 } 76 77 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); 78 if (err) { 79 error_propagate(errp, err); 80 return; 81 } 82 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR); 83 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, 84 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 85 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, 86 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 87 88 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 89 if (err) { 90 error_propagate(errp, err); 91 return; 92 } 93 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR); 94 95 /* Initialize all UARTS */ 96 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { 97 static const struct { 98 hwaddr addr; 99 unsigned int irq; 100 } serial_table[FSL_IMX31_NUM_UARTS] = { 101 { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ }, 102 { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ }, 103 }; 104 105 if (i < MAX_SERIAL_PORTS) { 106 CharDriverState *chr; 107 108 chr = serial_hds[i]; 109 110 if (!chr) { 111 char label[20]; 112 snprintf(label, sizeof(label), "imx31.uart%d", i); 113 chr = qemu_chr_new(label, "null", NULL); 114 } 115 116 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); 117 } 118 119 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 120 if (err) { 121 error_propagate(errp, err); 122 return; 123 } 124 125 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 126 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 127 qdev_get_gpio_in(DEVICE(&s->avic), 128 serial_table[i].irq)); 129 } 130 131 s->gpt.ccm = DEVICE(&s->ccm); 132 133 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); 134 if (err) { 135 error_propagate(errp, err); 136 return; 137 } 138 139 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR); 140 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 141 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ)); 142 143 /* Initialize all EPIT timers */ 144 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { 145 static const struct { 146 hwaddr addr; 147 unsigned int irq; 148 } epit_table[FSL_IMX31_NUM_EPITS] = { 149 { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ }, 150 { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ }, 151 }; 152 153 s->epit[i].ccm = DEVICE(&s->ccm); 154 155 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 156 if (err) { 157 error_propagate(errp, err); 158 return; 159 } 160 161 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 162 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 163 qdev_get_gpio_in(DEVICE(&s->avic), 164 epit_table[i].irq)); 165 } 166 167 /* Initialize all I2C */ 168 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { 169 static const struct { 170 hwaddr addr; 171 unsigned int irq; 172 } i2c_table[FSL_IMX31_NUM_I2CS] = { 173 { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ }, 174 { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ }, 175 { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ } 176 }; 177 178 /* Initialize the I2C */ 179 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 180 if (err) { 181 error_propagate(errp, err); 182 return; 183 } 184 /* Map I2C memory */ 185 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 186 /* Connect I2C IRQ to PIC */ 187 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 188 qdev_get_gpio_in(DEVICE(&s->avic), 189 i2c_table[i].irq)); 190 } 191 192 /* Initialize all GPIOs */ 193 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { 194 static const struct { 195 hwaddr addr; 196 unsigned int irq; 197 } gpio_table[FSL_IMX31_NUM_GPIOS] = { 198 { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ }, 199 { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ }, 200 { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ } 201 }; 202 203 object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel", 204 &error_abort); 205 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); 206 if (err) { 207 error_propagate(errp, err); 208 return; 209 } 210 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 211 /* Connect GPIO IRQ to PIC */ 212 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 213 qdev_get_gpio_in(DEVICE(&s->avic), 214 gpio_table[i].irq)); 215 } 216 217 /* On a real system, the first 16k is a `secure boot rom' */ 218 memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL, 219 "imx31.secure_rom", 220 FSL_IMX31_SECURE_ROM_SIZE, &err); 221 if (err) { 222 error_propagate(errp, err); 223 return; 224 } 225 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR, 226 &s->secure_rom); 227 228 /* There is also a 16k ROM */ 229 memory_region_init_rom_device(&s->rom, NULL, NULL, NULL, "imx31.rom", 230 FSL_IMX31_ROM_SIZE, &err); 231 if (err) { 232 error_propagate(errp, err); 233 return; 234 } 235 memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR, 236 &s->rom); 237 238 /* initialize internal RAM (16 KB) */ 239 memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE, 240 &err); 241 if (err) { 242 error_propagate(errp, err); 243 return; 244 } 245 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR, 246 &s->iram); 247 vmstate_register_ram_global(&s->iram); 248 249 /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */ 250 memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias", 251 &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE); 252 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR, 253 &s->iram_alias); 254 } 255 256 static void fsl_imx31_class_init(ObjectClass *oc, void *data) 257 { 258 DeviceClass *dc = DEVICE_CLASS(oc); 259 260 dc->realize = fsl_imx31_realize; 261 262 /* 263 * Reason: creates an ARM CPU, thus use after free(), see 264 * arm_cpu_class_init() 265 */ 266 dc->cannot_destroy_with_object_finalize_yet = true; 267 } 268 269 static const TypeInfo fsl_imx31_type_info = { 270 .name = TYPE_FSL_IMX31, 271 .parent = TYPE_DEVICE, 272 .instance_size = sizeof(FslIMX31State), 273 .instance_init = fsl_imx31_init, 274 .class_init = fsl_imx31_class_init, 275 }; 276 277 static void fsl_imx31_register_types(void) 278 { 279 type_register_static(&fsl_imx31_type_info); 280 } 281 282 type_init(fsl_imx31_register_types) 283