1 /* 2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX31 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "hw/arm/fsl-imx31.h" 26 #include "sysemu/sysemu.h" 27 #include "exec/address-spaces.h" 28 #include "hw/qdev-properties.h" 29 #include "chardev/char.h" 30 31 static void fsl_imx31_init(Object *obj) 32 { 33 FslIMX31State *s = FSL_IMX31(obj); 34 int i; 35 36 object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), 37 ARM_CPU_TYPE_NAME("arm1136"), 38 &error_abort, NULL); 39 40 sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), 41 TYPE_IMX_AVIC); 42 43 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM); 44 45 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { 46 sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]), 47 TYPE_IMX_SERIAL); 48 } 49 50 sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT); 51 52 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { 53 sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]), 54 TYPE_IMX_EPIT); 55 } 56 57 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { 58 sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]), 59 TYPE_IMX_I2C); 60 } 61 62 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { 63 sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]), 64 TYPE_IMX_GPIO); 65 } 66 67 sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT); 68 } 69 70 static void fsl_imx31_realize(DeviceState *dev, Error **errp) 71 { 72 FslIMX31State *s = FSL_IMX31(dev); 73 uint16_t i; 74 Error *err = NULL; 75 76 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 77 if (err) { 78 error_propagate(errp, err); 79 return; 80 } 81 82 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); 83 if (err) { 84 error_propagate(errp, err); 85 return; 86 } 87 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR); 88 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, 89 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 90 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, 91 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 92 93 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 94 if (err) { 95 error_propagate(errp, err); 96 return; 97 } 98 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR); 99 100 /* Initialize all UARTS */ 101 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { 102 static const struct { 103 hwaddr addr; 104 unsigned int irq; 105 } serial_table[FSL_IMX31_NUM_UARTS] = { 106 { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ }, 107 { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ }, 108 }; 109 110 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 111 112 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 113 if (err) { 114 error_propagate(errp, err); 115 return; 116 } 117 118 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 119 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 120 qdev_get_gpio_in(DEVICE(&s->avic), 121 serial_table[i].irq)); 122 } 123 124 s->gpt.ccm = IMX_CCM(&s->ccm); 125 126 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); 127 if (err) { 128 error_propagate(errp, err); 129 return; 130 } 131 132 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR); 133 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 134 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ)); 135 136 /* Initialize all EPIT timers */ 137 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { 138 static const struct { 139 hwaddr addr; 140 unsigned int irq; 141 } epit_table[FSL_IMX31_NUM_EPITS] = { 142 { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ }, 143 { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ }, 144 }; 145 146 s->epit[i].ccm = IMX_CCM(&s->ccm); 147 148 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 149 if (err) { 150 error_propagate(errp, err); 151 return; 152 } 153 154 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 155 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 156 qdev_get_gpio_in(DEVICE(&s->avic), 157 epit_table[i].irq)); 158 } 159 160 /* Initialize all I2C */ 161 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { 162 static const struct { 163 hwaddr addr; 164 unsigned int irq; 165 } i2c_table[FSL_IMX31_NUM_I2CS] = { 166 { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ }, 167 { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ }, 168 { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ } 169 }; 170 171 /* Initialize the I2C */ 172 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 173 if (err) { 174 error_propagate(errp, err); 175 return; 176 } 177 /* Map I2C memory */ 178 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 179 /* Connect I2C IRQ to PIC */ 180 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 181 qdev_get_gpio_in(DEVICE(&s->avic), 182 i2c_table[i].irq)); 183 } 184 185 /* Initialize all GPIOs */ 186 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { 187 static const struct { 188 hwaddr addr; 189 unsigned int irq; 190 } gpio_table[FSL_IMX31_NUM_GPIOS] = { 191 { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ }, 192 { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ }, 193 { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ } 194 }; 195 196 object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel", 197 &error_abort); 198 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); 199 if (err) { 200 error_propagate(errp, err); 201 return; 202 } 203 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 204 /* Connect GPIO IRQ to PIC */ 205 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 206 qdev_get_gpio_in(DEVICE(&s->avic), 207 gpio_table[i].irq)); 208 } 209 210 /* Watchdog */ 211 object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort); 212 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR); 213 214 /* On a real system, the first 16k is a `secure boot rom' */ 215 memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom", 216 FSL_IMX31_SECURE_ROM_SIZE, &err); 217 if (err) { 218 error_propagate(errp, err); 219 return; 220 } 221 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR, 222 &s->secure_rom); 223 224 /* There is also a 16k ROM */ 225 memory_region_init_rom(&s->rom, OBJECT(dev), "imx31.rom", 226 FSL_IMX31_ROM_SIZE, &err); 227 if (err) { 228 error_propagate(errp, err); 229 return; 230 } 231 memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR, 232 &s->rom); 233 234 /* initialize internal RAM (16 KB) */ 235 memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE, 236 &err); 237 if (err) { 238 error_propagate(errp, err); 239 return; 240 } 241 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR, 242 &s->iram); 243 244 /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */ 245 memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx31.iram_alias", 246 &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE); 247 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR, 248 &s->iram_alias); 249 } 250 251 static void fsl_imx31_class_init(ObjectClass *oc, void *data) 252 { 253 DeviceClass *dc = DEVICE_CLASS(oc); 254 255 dc->realize = fsl_imx31_realize; 256 dc->desc = "i.MX31 SOC"; 257 /* 258 * Reason: uses serial_hds in realize and the kzm board does not 259 * support multiple CPUs 260 */ 261 dc->user_creatable = false; 262 } 263 264 static const TypeInfo fsl_imx31_type_info = { 265 .name = TYPE_FSL_IMX31, 266 .parent = TYPE_DEVICE, 267 .instance_size = sizeof(FslIMX31State), 268 .instance_init = fsl_imx31_init, 269 .class_init = fsl_imx31_class_init, 270 }; 271 272 static void fsl_imx31_register_types(void) 273 { 274 type_register_static(&fsl_imx31_type_info); 275 } 276 277 type_init(fsl_imx31_register_types) 278