1 /* 2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX31 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "hw/arm/fsl-imx31.h" 23 #include "sysemu/sysemu.h" 24 #include "exec/address-spaces.h" 25 #include "hw/boards.h" 26 #include "sysemu/char.h" 27 28 static void fsl_imx31_init(Object *obj) 29 { 30 FslIMX31State *s = FSL_IMX31(obj); 31 int i; 32 33 object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU); 34 35 object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC); 36 qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default()); 37 38 object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX_CCM); 39 qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default()); 40 41 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { 42 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); 43 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 44 } 45 46 object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT); 47 qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default()); 48 49 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { 50 object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); 51 qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); 52 } 53 } 54 55 static void fsl_imx31_realize(DeviceState *dev, Error **errp) 56 { 57 FslIMX31State *s = FSL_IMX31(dev); 58 uint16_t i; 59 Error *err = NULL; 60 61 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 62 if (err) { 63 error_propagate(errp, err); 64 return; 65 } 66 67 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); 68 if (err) { 69 error_propagate(errp, err); 70 return; 71 } 72 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR); 73 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, 74 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 75 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, 76 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 77 78 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 79 if (err) { 80 error_propagate(errp, err); 81 return; 82 } 83 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR); 84 85 /* Initialize all UARTS */ 86 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { 87 static const struct { 88 hwaddr addr; 89 unsigned int irq; 90 } serial_table[FSL_IMX31_NUM_UARTS] = { 91 { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ }, 92 { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ }, 93 }; 94 95 if (i < MAX_SERIAL_PORTS) { 96 CharDriverState *chr; 97 98 chr = serial_hds[i]; 99 100 if (!chr) { 101 char label[20]; 102 snprintf(label, sizeof(label), "imx31.uart%d", i); 103 chr = qemu_chr_new(label, "null", NULL); 104 } 105 106 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); 107 } 108 109 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 110 if (err) { 111 error_propagate(errp, err); 112 return; 113 } 114 115 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 116 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 117 qdev_get_gpio_in(DEVICE(&s->avic), 118 serial_table[i].irq)); 119 } 120 121 s->gpt.ccm = DEVICE(&s->ccm); 122 123 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); 124 if (err) { 125 error_propagate(errp, err); 126 return; 127 } 128 129 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR); 130 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 131 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ)); 132 133 /* Initialize all EPIT timers */ 134 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { 135 static const struct { 136 hwaddr addr; 137 unsigned int irq; 138 } epit_table[FSL_IMX31_NUM_EPITS] = { 139 { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ }, 140 { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ }, 141 }; 142 143 s->epit[i].ccm = DEVICE(&s->ccm); 144 145 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 146 if (err) { 147 error_propagate(errp, err); 148 return; 149 } 150 151 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 152 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 153 qdev_get_gpio_in(DEVICE(&s->avic), 154 epit_table[i].irq)); 155 } 156 157 /* On a real system, the first 16k is a `secure boot rom' */ 158 memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL, 159 "imx31.secure_rom", 160 FSL_IMX31_SECURE_ROM_SIZE, &err); 161 if (err) { 162 error_propagate(errp, err); 163 return; 164 } 165 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR, 166 &s->secure_rom); 167 168 /* There is also a 16k ROM */ 169 memory_region_init_rom_device(&s->rom, NULL, NULL, NULL, "imx31.rom", 170 FSL_IMX31_ROM_SIZE, &err); 171 if (err) { 172 error_propagate(errp, err); 173 return; 174 } 175 memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR, 176 &s->rom); 177 178 /* initialize internal RAM (16 KB) */ 179 memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE, 180 &err); 181 if (err) { 182 error_propagate(errp, err); 183 return; 184 } 185 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR, 186 &s->iram); 187 vmstate_register_ram_global(&s->iram); 188 189 /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */ 190 memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias", 191 &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE); 192 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR, 193 &s->iram_alias); 194 } 195 196 static void fsl_imx31_class_init(ObjectClass *oc, void *data) 197 { 198 DeviceClass *dc = DEVICE_CLASS(oc); 199 200 dc->realize = fsl_imx31_realize; 201 } 202 203 static const TypeInfo fsl_imx31_type_info = { 204 .name = TYPE_FSL_IMX31, 205 .parent = TYPE_DEVICE, 206 .instance_size = sizeof(FslIMX31State), 207 .instance_init = fsl_imx31_init, 208 .class_init = fsl_imx31_class_init, 209 }; 210 211 static void fsl_imx31_register_types(void) 212 { 213 type_register_static(&fsl_imx31_type_info); 214 } 215 216 type_init(fsl_imx31_register_types) 217