1 /* 2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX25 SOC emulation. 5 * 6 * Based on hw/arm/xlnx-zynqmp.c 7 * 8 * Copyright (C) 2015 Xilinx Inc 9 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 19 * for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "hw/arm/fsl-imx25.h" 26 #include "sysemu/sysemu.h" 27 #include "exec/address-spaces.h" 28 #include "hw/boards.h" 29 #include "sysemu/char.h" 30 31 static void fsl_imx25_init(Object *obj) 32 { 33 FslIMX25State *s = FSL_IMX25(obj); 34 int i; 35 36 object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU); 37 38 object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC); 39 qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default()); 40 41 object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX_CCM); 42 qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default()); 43 44 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { 45 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); 46 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 47 } 48 49 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { 50 object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX_GPT); 51 qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default()); 52 } 53 54 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { 55 object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); 56 qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); 57 } 58 59 object_initialize(&s->fec, sizeof(s->fec), TYPE_IMX_FEC); 60 qdev_set_parent_bus(DEVICE(&s->fec), sysbus_get_default()); 61 62 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { 63 object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); 64 qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); 65 } 66 } 67 68 static void fsl_imx25_realize(DeviceState *dev, Error **errp) 69 { 70 FslIMX25State *s = FSL_IMX25(dev); 71 uint8_t i; 72 Error *err = NULL; 73 74 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 75 if (err) { 76 error_propagate(errp, err); 77 return; 78 } 79 80 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); 81 if (err) { 82 error_propagate(errp, err); 83 return; 84 } 85 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR); 86 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, 87 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 88 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, 89 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 90 91 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 92 if (err) { 93 error_propagate(errp, err); 94 return; 95 } 96 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR); 97 98 /* Initialize all UARTs */ 99 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { 100 static const struct { 101 hwaddr addr; 102 unsigned int irq; 103 } serial_table[FSL_IMX25_NUM_UARTS] = { 104 { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ }, 105 { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ }, 106 { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ }, 107 { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ }, 108 { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ } 109 }; 110 111 if (i < MAX_SERIAL_PORTS) { 112 CharDriverState *chr; 113 114 chr = serial_hds[i]; 115 116 if (!chr) { 117 char label[20]; 118 snprintf(label, sizeof(label), "imx31.uart%d", i); 119 chr = qemu_chr_new(label, "null", NULL); 120 } 121 122 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); 123 } 124 125 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 126 if (err) { 127 error_propagate(errp, err); 128 return; 129 } 130 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 131 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 132 qdev_get_gpio_in(DEVICE(&s->avic), 133 serial_table[i].irq)); 134 } 135 136 /* Initialize all GPT timers */ 137 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { 138 static const struct { 139 hwaddr addr; 140 unsigned int irq; 141 } gpt_table[FSL_IMX25_NUM_GPTS] = { 142 { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ }, 143 { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ }, 144 { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ }, 145 { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ } 146 }; 147 148 s->gpt[i].ccm = DEVICE(&s->ccm); 149 150 object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err); 151 if (err) { 152 error_propagate(errp, err); 153 return; 154 } 155 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr); 156 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, 157 qdev_get_gpio_in(DEVICE(&s->avic), 158 gpt_table[i].irq)); 159 } 160 161 /* Initialize all EPIT timers */ 162 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { 163 static const struct { 164 hwaddr addr; 165 unsigned int irq; 166 } epit_table[FSL_IMX25_NUM_EPITS] = { 167 { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ }, 168 { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ } 169 }; 170 171 s->epit[i].ccm = DEVICE(&s->ccm); 172 173 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 174 if (err) { 175 error_propagate(errp, err); 176 return; 177 } 178 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 179 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 180 qdev_get_gpio_in(DEVICE(&s->avic), 181 epit_table[i].irq)); 182 } 183 184 qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]); 185 object_property_set_bool(OBJECT(&s->fec), true, "realized", &err); 186 if (err) { 187 error_propagate(errp, err); 188 return; 189 } 190 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR); 191 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0, 192 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ)); 193 194 195 /* Initialize all I2C */ 196 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { 197 static const struct { 198 hwaddr addr; 199 unsigned int irq; 200 } i2c_table[FSL_IMX25_NUM_I2CS] = { 201 { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ }, 202 { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ }, 203 { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ } 204 }; 205 206 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 207 if (err) { 208 error_propagate(errp, err); 209 return; 210 } 211 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 212 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 213 qdev_get_gpio_in(DEVICE(&s->avic), 214 i2c_table[i].irq)); 215 } 216 217 /* initialize 2 x 16 KB ROM */ 218 memory_region_init_rom_device(&s->rom[0], NULL, NULL, NULL, 219 "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err); 220 if (err) { 221 error_propagate(errp, err); 222 return; 223 } 224 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR, 225 &s->rom[0]); 226 memory_region_init_rom_device(&s->rom[1], NULL, NULL, NULL, 227 "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err); 228 if (err) { 229 error_propagate(errp, err); 230 return; 231 } 232 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR, 233 &s->rom[1]); 234 235 /* initialize internal RAM (128 KB) */ 236 memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE, 237 &err); 238 if (err) { 239 error_propagate(errp, err); 240 return; 241 } 242 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR, 243 &s->iram); 244 vmstate_register_ram_global(&s->iram); 245 246 /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */ 247 memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias", 248 &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE); 249 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR, 250 &s->iram_alias); 251 } 252 253 static void fsl_imx25_class_init(ObjectClass *oc, void *data) 254 { 255 DeviceClass *dc = DEVICE_CLASS(oc); 256 257 dc->realize = fsl_imx25_realize; 258 } 259 260 static const TypeInfo fsl_imx25_type_info = { 261 .name = TYPE_FSL_IMX25, 262 .parent = TYPE_DEVICE, 263 .instance_size = sizeof(FslIMX25State), 264 .instance_init = fsl_imx25_init, 265 .class_init = fsl_imx25_class_init, 266 }; 267 268 static void fsl_imx25_register_types(void) 269 { 270 type_register_static(&fsl_imx25_type_info); 271 } 272 273 type_init(fsl_imx25_register_types) 274