1 /* 2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX25 SOC emulation. 5 * 6 * Based on hw/arm/xlnx-zynqmp.c 7 * 8 * Copyright (C) 2015 Xilinx Inc 9 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 19 * for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "cpu.h" 28 #include "hw/arm/fsl-imx25.h" 29 #include "sysemu/sysemu.h" 30 #include "exec/address-spaces.h" 31 #include "hw/qdev-properties.h" 32 #include "chardev/char.h" 33 34 #define IMX25_ESDHC_CAPABILITIES 0x07e20000 35 36 static void fsl_imx25_init(Object *obj) 37 { 38 FslIMX25State *s = FSL_IMX25(obj); 39 int i; 40 41 object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), 42 ARM_CPU_TYPE_NAME("arm926"), 43 &error_abort, NULL); 44 45 sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), 46 TYPE_IMX_AVIC); 47 48 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM); 49 50 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { 51 sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]), 52 TYPE_IMX_SERIAL); 53 } 54 55 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { 56 sysbus_init_child_obj(obj, "gpt[*]", &s->gpt[i], sizeof(s->gpt[i]), 57 TYPE_IMX25_GPT); 58 } 59 60 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { 61 sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]), 62 TYPE_IMX_EPIT); 63 } 64 65 sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC); 66 67 sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc), 68 TYPE_IMX_RNGC); 69 70 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { 71 sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]), 72 TYPE_IMX_I2C); 73 } 74 75 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { 76 sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]), 77 TYPE_IMX_GPIO); 78 } 79 80 for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { 81 sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]), 82 TYPE_IMX_USDHC); 83 } 84 85 for (i = 0; i < FSL_IMX25_NUM_USBS; i++) { 86 sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]), 87 TYPE_CHIPIDEA); 88 } 89 90 } 91 92 static void fsl_imx25_realize(DeviceState *dev, Error **errp) 93 { 94 FslIMX25State *s = FSL_IMX25(dev); 95 uint8_t i; 96 Error *err = NULL; 97 98 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 99 if (err) { 100 error_propagate(errp, err); 101 return; 102 } 103 104 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); 105 if (err) { 106 error_propagate(errp, err); 107 return; 108 } 109 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR); 110 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, 111 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 112 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, 113 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 114 115 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 116 if (err) { 117 error_propagate(errp, err); 118 return; 119 } 120 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR); 121 122 /* Initialize all UARTs */ 123 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { 124 static const struct { 125 hwaddr addr; 126 unsigned int irq; 127 } serial_table[FSL_IMX25_NUM_UARTS] = { 128 { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ }, 129 { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ }, 130 { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ }, 131 { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ }, 132 { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ } 133 }; 134 135 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 136 137 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 138 if (err) { 139 error_propagate(errp, err); 140 return; 141 } 142 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 143 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 144 qdev_get_gpio_in(DEVICE(&s->avic), 145 serial_table[i].irq)); 146 } 147 148 /* Initialize all GPT timers */ 149 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { 150 static const struct { 151 hwaddr addr; 152 unsigned int irq; 153 } gpt_table[FSL_IMX25_NUM_GPTS] = { 154 { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ }, 155 { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ }, 156 { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ }, 157 { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ } 158 }; 159 160 s->gpt[i].ccm = IMX_CCM(&s->ccm); 161 162 object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err); 163 if (err) { 164 error_propagate(errp, err); 165 return; 166 } 167 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr); 168 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, 169 qdev_get_gpio_in(DEVICE(&s->avic), 170 gpt_table[i].irq)); 171 } 172 173 /* Initialize all EPIT timers */ 174 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { 175 static const struct { 176 hwaddr addr; 177 unsigned int irq; 178 } epit_table[FSL_IMX25_NUM_EPITS] = { 179 { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ }, 180 { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ } 181 }; 182 183 s->epit[i].ccm = IMX_CCM(&s->ccm); 184 185 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 186 if (err) { 187 error_propagate(errp, err); 188 return; 189 } 190 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 191 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 192 qdev_get_gpio_in(DEVICE(&s->avic), 193 epit_table[i].irq)); 194 } 195 196 qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]); 197 198 object_property_set_bool(OBJECT(&s->fec), true, "realized", &err); 199 if (err) { 200 error_propagate(errp, err); 201 return; 202 } 203 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR); 204 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0, 205 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ)); 206 207 object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err); 208 if (err) { 209 error_propagate(errp, err); 210 return; 211 } 212 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR); 213 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0, 214 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ)); 215 216 /* Initialize all I2C */ 217 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { 218 static const struct { 219 hwaddr addr; 220 unsigned int irq; 221 } i2c_table[FSL_IMX25_NUM_I2CS] = { 222 { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ }, 223 { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ }, 224 { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ } 225 }; 226 227 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 228 if (err) { 229 error_propagate(errp, err); 230 return; 231 } 232 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 233 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 234 qdev_get_gpio_in(DEVICE(&s->avic), 235 i2c_table[i].irq)); 236 } 237 238 /* Initialize all GPIOs */ 239 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { 240 static const struct { 241 hwaddr addr; 242 unsigned int irq; 243 } gpio_table[FSL_IMX25_NUM_GPIOS] = { 244 { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ }, 245 { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ }, 246 { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ }, 247 { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ } 248 }; 249 250 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); 251 if (err) { 252 error_propagate(errp, err); 253 return; 254 } 255 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 256 /* Connect GPIO IRQ to PIC */ 257 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 258 qdev_get_gpio_in(DEVICE(&s->avic), 259 gpio_table[i].irq)); 260 } 261 262 /* Initialize all SDHC */ 263 for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { 264 static const struct { 265 hwaddr addr; 266 unsigned int irq; 267 } esdhc_table[FSL_IMX25_NUM_ESDHCS] = { 268 { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ }, 269 { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ }, 270 }; 271 272 object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version", 273 &err); 274 object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES, 275 "capareg", &err); 276 object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err); 277 if (err) { 278 error_propagate(errp, err); 279 return; 280 } 281 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); 282 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, 283 qdev_get_gpio_in(DEVICE(&s->avic), 284 esdhc_table[i].irq)); 285 } 286 287 /* USB */ 288 for (i = 0; i < FSL_IMX25_NUM_USBS; i++) { 289 static const struct { 290 hwaddr addr; 291 unsigned int irq; 292 } usb_table[FSL_IMX25_NUM_USBS] = { 293 { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ }, 294 { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ }, 295 }; 296 297 object_property_set_bool(OBJECT(&s->usb[i]), true, "realized", 298 &error_abort); 299 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr); 300 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, 301 qdev_get_gpio_in(DEVICE(&s->avic), 302 usb_table[i].irq)); 303 } 304 305 /* initialize 2 x 16 KB ROM */ 306 memory_region_init_rom(&s->rom[0], NULL, 307 "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err); 308 if (err) { 309 error_propagate(errp, err); 310 return; 311 } 312 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR, 313 &s->rom[0]); 314 memory_region_init_rom(&s->rom[1], NULL, 315 "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err); 316 if (err) { 317 error_propagate(errp, err); 318 return; 319 } 320 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR, 321 &s->rom[1]); 322 323 /* initialize internal RAM (128 KB) */ 324 memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE, 325 &err); 326 if (err) { 327 error_propagate(errp, err); 328 return; 329 } 330 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR, 331 &s->iram); 332 333 /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */ 334 memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias", 335 &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE); 336 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR, 337 &s->iram_alias); 338 } 339 340 static void fsl_imx25_class_init(ObjectClass *oc, void *data) 341 { 342 DeviceClass *dc = DEVICE_CLASS(oc); 343 344 dc->realize = fsl_imx25_realize; 345 dc->desc = "i.MX25 SOC"; 346 /* 347 * Reason: uses serial_hds in realize and the imx25 board does not 348 * support multiple CPUs 349 */ 350 dc->user_creatable = false; 351 } 352 353 static const TypeInfo fsl_imx25_type_info = { 354 .name = TYPE_FSL_IMX25, 355 .parent = TYPE_DEVICE, 356 .instance_size = sizeof(FslIMX25State), 357 .instance_init = fsl_imx25_init, 358 .class_init = fsl_imx25_class_init, 359 }; 360 361 static void fsl_imx25_register_types(void) 362 { 363 type_register_static(&fsl_imx25_type_info); 364 } 365 366 type_init(fsl_imx25_register_types) 367