1 /* 2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX25 SOC emulation. 5 * 6 * Based on hw/arm/xlnx-zynqmp.c 7 * 8 * Copyright (C) 2015 Xilinx Inc 9 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 19 * for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "cpu.h" 28 #include "hw/arm/fsl-imx25.h" 29 #include "sysemu/sysemu.h" 30 #include "exec/address-spaces.h" 31 #include "hw/qdev-properties.h" 32 #include "chardev/char.h" 33 34 static void fsl_imx25_init(Object *obj) 35 { 36 FslIMX25State *s = FSL_IMX25(obj); 37 int i; 38 39 object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), 40 ARM_CPU_TYPE_NAME("arm926"), 41 &error_abort, NULL); 42 43 sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), 44 TYPE_IMX_AVIC); 45 46 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM); 47 48 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { 49 sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]), 50 TYPE_IMX_SERIAL); 51 } 52 53 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { 54 sysbus_init_child_obj(obj, "gpt[*]", &s->gpt[i], sizeof(s->gpt[i]), 55 TYPE_IMX25_GPT); 56 } 57 58 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { 59 sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]), 60 TYPE_IMX_EPIT); 61 } 62 63 sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC); 64 65 sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc), 66 TYPE_IMX_RNGC); 67 68 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { 69 sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]), 70 TYPE_IMX_I2C); 71 } 72 73 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { 74 sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]), 75 TYPE_IMX_GPIO); 76 } 77 } 78 79 static void fsl_imx25_realize(DeviceState *dev, Error **errp) 80 { 81 FslIMX25State *s = FSL_IMX25(dev); 82 uint8_t i; 83 Error *err = NULL; 84 85 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 86 if (err) { 87 error_propagate(errp, err); 88 return; 89 } 90 91 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); 92 if (err) { 93 error_propagate(errp, err); 94 return; 95 } 96 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR); 97 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, 98 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 99 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, 100 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 101 102 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 103 if (err) { 104 error_propagate(errp, err); 105 return; 106 } 107 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR); 108 109 /* Initialize all UARTs */ 110 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { 111 static const struct { 112 hwaddr addr; 113 unsigned int irq; 114 } serial_table[FSL_IMX25_NUM_UARTS] = { 115 { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ }, 116 { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ }, 117 { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ }, 118 { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ }, 119 { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ } 120 }; 121 122 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 123 124 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 125 if (err) { 126 error_propagate(errp, err); 127 return; 128 } 129 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 130 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 131 qdev_get_gpio_in(DEVICE(&s->avic), 132 serial_table[i].irq)); 133 } 134 135 /* Initialize all GPT timers */ 136 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { 137 static const struct { 138 hwaddr addr; 139 unsigned int irq; 140 } gpt_table[FSL_IMX25_NUM_GPTS] = { 141 { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ }, 142 { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ }, 143 { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ }, 144 { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ } 145 }; 146 147 s->gpt[i].ccm = IMX_CCM(&s->ccm); 148 149 object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err); 150 if (err) { 151 error_propagate(errp, err); 152 return; 153 } 154 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr); 155 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, 156 qdev_get_gpio_in(DEVICE(&s->avic), 157 gpt_table[i].irq)); 158 } 159 160 /* Initialize all EPIT timers */ 161 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { 162 static const struct { 163 hwaddr addr; 164 unsigned int irq; 165 } epit_table[FSL_IMX25_NUM_EPITS] = { 166 { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ }, 167 { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ } 168 }; 169 170 s->epit[i].ccm = IMX_CCM(&s->ccm); 171 172 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 173 if (err) { 174 error_propagate(errp, err); 175 return; 176 } 177 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 178 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 179 qdev_get_gpio_in(DEVICE(&s->avic), 180 epit_table[i].irq)); 181 } 182 183 qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]); 184 185 object_property_set_bool(OBJECT(&s->fec), true, "realized", &err); 186 if (err) { 187 error_propagate(errp, err); 188 return; 189 } 190 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR); 191 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0, 192 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ)); 193 194 object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err); 195 if (err) { 196 error_propagate(errp, err); 197 return; 198 } 199 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR); 200 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0, 201 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ)); 202 203 /* Initialize all I2C */ 204 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { 205 static const struct { 206 hwaddr addr; 207 unsigned int irq; 208 } i2c_table[FSL_IMX25_NUM_I2CS] = { 209 { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ }, 210 { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ }, 211 { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ } 212 }; 213 214 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 215 if (err) { 216 error_propagate(errp, err); 217 return; 218 } 219 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 220 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 221 qdev_get_gpio_in(DEVICE(&s->avic), 222 i2c_table[i].irq)); 223 } 224 225 /* Initialize all GPIOs */ 226 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { 227 static const struct { 228 hwaddr addr; 229 unsigned int irq; 230 } gpio_table[FSL_IMX25_NUM_GPIOS] = { 231 { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ }, 232 { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ }, 233 { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ }, 234 { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ } 235 }; 236 237 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); 238 if (err) { 239 error_propagate(errp, err); 240 return; 241 } 242 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 243 /* Connect GPIO IRQ to PIC */ 244 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 245 qdev_get_gpio_in(DEVICE(&s->avic), 246 gpio_table[i].irq)); 247 } 248 249 /* initialize 2 x 16 KB ROM */ 250 memory_region_init_rom(&s->rom[0], NULL, 251 "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err); 252 if (err) { 253 error_propagate(errp, err); 254 return; 255 } 256 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR, 257 &s->rom[0]); 258 memory_region_init_rom(&s->rom[1], NULL, 259 "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err); 260 if (err) { 261 error_propagate(errp, err); 262 return; 263 } 264 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR, 265 &s->rom[1]); 266 267 /* initialize internal RAM (128 KB) */ 268 memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE, 269 &err); 270 if (err) { 271 error_propagate(errp, err); 272 return; 273 } 274 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR, 275 &s->iram); 276 277 /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */ 278 memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias", 279 &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE); 280 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR, 281 &s->iram_alias); 282 } 283 284 static void fsl_imx25_class_init(ObjectClass *oc, void *data) 285 { 286 DeviceClass *dc = DEVICE_CLASS(oc); 287 288 dc->realize = fsl_imx25_realize; 289 dc->desc = "i.MX25 SOC"; 290 /* 291 * Reason: uses serial_hds in realize and the imx25 board does not 292 * support multiple CPUs 293 */ 294 dc->user_creatable = false; 295 } 296 297 static const TypeInfo fsl_imx25_type_info = { 298 .name = TYPE_FSL_IMX25, 299 .parent = TYPE_DEVICE, 300 .instance_size = sizeof(FslIMX25State), 301 .instance_init = fsl_imx25_init, 302 .class_init = fsl_imx25_class_init, 303 }; 304 305 static void fsl_imx25_register_types(void) 306 { 307 type_register_static(&fsl_imx25_type_info); 308 } 309 310 type_init(fsl_imx25_register_types) 311