1 /* 2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX25 SOC emulation. 5 * 6 * Based on hw/arm/xlnx-zynqmp.c 7 * 8 * Copyright (C) 2015 Xilinx Inc 9 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 19 * for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "cpu.h" 28 #include "hw/arm/fsl-imx25.h" 29 #include "sysemu/sysemu.h" 30 #include "exec/address-spaces.h" 31 #include "hw/qdev-properties.h" 32 #include "chardev/char.h" 33 34 static void fsl_imx25_init(Object *obj) 35 { 36 FslIMX25State *s = FSL_IMX25(obj); 37 int i; 38 39 object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU); 40 41 sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), 42 TYPE_IMX_AVIC); 43 44 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM); 45 46 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { 47 sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]), 48 TYPE_IMX_SERIAL); 49 } 50 51 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { 52 sysbus_init_child_obj(obj, "gpt[*]", &s->gpt[i], sizeof(s->gpt[i]), 53 TYPE_IMX25_GPT); 54 } 55 56 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { 57 sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]), 58 TYPE_IMX_EPIT); 59 } 60 61 sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC); 62 63 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { 64 sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]), 65 TYPE_IMX_I2C); 66 } 67 68 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { 69 sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]), 70 TYPE_IMX_GPIO); 71 } 72 } 73 74 static void fsl_imx25_realize(DeviceState *dev, Error **errp) 75 { 76 FslIMX25State *s = FSL_IMX25(dev); 77 uint8_t i; 78 Error *err = NULL; 79 80 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 81 if (err) { 82 error_propagate(errp, err); 83 return; 84 } 85 86 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); 87 if (err) { 88 error_propagate(errp, err); 89 return; 90 } 91 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR); 92 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, 93 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 94 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, 95 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 96 97 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 98 if (err) { 99 error_propagate(errp, err); 100 return; 101 } 102 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR); 103 104 /* Initialize all UARTs */ 105 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { 106 static const struct { 107 hwaddr addr; 108 unsigned int irq; 109 } serial_table[FSL_IMX25_NUM_UARTS] = { 110 { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ }, 111 { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ }, 112 { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ }, 113 { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ }, 114 { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ } 115 }; 116 117 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 118 119 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 120 if (err) { 121 error_propagate(errp, err); 122 return; 123 } 124 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 125 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 126 qdev_get_gpio_in(DEVICE(&s->avic), 127 serial_table[i].irq)); 128 } 129 130 /* Initialize all GPT timers */ 131 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { 132 static const struct { 133 hwaddr addr; 134 unsigned int irq; 135 } gpt_table[FSL_IMX25_NUM_GPTS] = { 136 { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ }, 137 { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ }, 138 { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ }, 139 { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ } 140 }; 141 142 s->gpt[i].ccm = IMX_CCM(&s->ccm); 143 144 object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err); 145 if (err) { 146 error_propagate(errp, err); 147 return; 148 } 149 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr); 150 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, 151 qdev_get_gpio_in(DEVICE(&s->avic), 152 gpt_table[i].irq)); 153 } 154 155 /* Initialize all EPIT timers */ 156 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { 157 static const struct { 158 hwaddr addr; 159 unsigned int irq; 160 } epit_table[FSL_IMX25_NUM_EPITS] = { 161 { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ }, 162 { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ } 163 }; 164 165 s->epit[i].ccm = IMX_CCM(&s->ccm); 166 167 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 168 if (err) { 169 error_propagate(errp, err); 170 return; 171 } 172 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 173 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 174 qdev_get_gpio_in(DEVICE(&s->avic), 175 epit_table[i].irq)); 176 } 177 178 qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]); 179 180 object_property_set_bool(OBJECT(&s->fec), true, "realized", &err); 181 if (err) { 182 error_propagate(errp, err); 183 return; 184 } 185 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR); 186 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0, 187 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ)); 188 189 190 /* Initialize all I2C */ 191 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { 192 static const struct { 193 hwaddr addr; 194 unsigned int irq; 195 } i2c_table[FSL_IMX25_NUM_I2CS] = { 196 { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ }, 197 { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ }, 198 { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ } 199 }; 200 201 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 202 if (err) { 203 error_propagate(errp, err); 204 return; 205 } 206 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 207 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 208 qdev_get_gpio_in(DEVICE(&s->avic), 209 i2c_table[i].irq)); 210 } 211 212 /* Initialize all GPIOs */ 213 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { 214 static const struct { 215 hwaddr addr; 216 unsigned int irq; 217 } gpio_table[FSL_IMX25_NUM_GPIOS] = { 218 { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ }, 219 { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ }, 220 { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ }, 221 { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ } 222 }; 223 224 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); 225 if (err) { 226 error_propagate(errp, err); 227 return; 228 } 229 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 230 /* Connect GPIO IRQ to PIC */ 231 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 232 qdev_get_gpio_in(DEVICE(&s->avic), 233 gpio_table[i].irq)); 234 } 235 236 /* initialize 2 x 16 KB ROM */ 237 memory_region_init_rom(&s->rom[0], NULL, 238 "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err); 239 if (err) { 240 error_propagate(errp, err); 241 return; 242 } 243 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR, 244 &s->rom[0]); 245 memory_region_init_rom(&s->rom[1], NULL, 246 "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err); 247 if (err) { 248 error_propagate(errp, err); 249 return; 250 } 251 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR, 252 &s->rom[1]); 253 254 /* initialize internal RAM (128 KB) */ 255 memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE, 256 &err); 257 if (err) { 258 error_propagate(errp, err); 259 return; 260 } 261 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR, 262 &s->iram); 263 264 /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */ 265 memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias", 266 &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE); 267 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR, 268 &s->iram_alias); 269 } 270 271 static void fsl_imx25_class_init(ObjectClass *oc, void *data) 272 { 273 DeviceClass *dc = DEVICE_CLASS(oc); 274 275 dc->realize = fsl_imx25_realize; 276 dc->desc = "i.MX25 SOC"; 277 /* 278 * Reason: uses serial_hds in realize and the imx25 board does not 279 * support multiple CPUs 280 */ 281 dc->user_creatable = false; 282 } 283 284 static const TypeInfo fsl_imx25_type_info = { 285 .name = TYPE_FSL_IMX25, 286 .parent = TYPE_DEVICE, 287 .instance_size = sizeof(FslIMX25State), 288 .instance_init = fsl_imx25_init, 289 .class_init = fsl_imx25_class_init, 290 }; 291 292 static void fsl_imx25_register_types(void) 293 { 294 type_register_static(&fsl_imx25_type_info); 295 } 296 297 type_init(fsl_imx25_register_types) 298