1 /* 2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX25 SOC emulation. 5 * 6 * Based on hw/arm/xlnx-zynqmp.c 7 * 8 * Copyright (C) 2015 Xilinx Inc 9 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 19 * for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "cpu.h" 28 #include "hw/arm/fsl-imx25.h" 29 #include "sysemu/sysemu.h" 30 #include "exec/address-spaces.h" 31 #include "hw/qdev-properties.h" 32 #include "chardev/char.h" 33 34 #define IMX25_ESDHC_CAPABILITIES 0x07e20000 35 36 static void fsl_imx25_init(Object *obj) 37 { 38 FslIMX25State *s = FSL_IMX25(obj); 39 int i; 40 41 object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm926")); 42 43 object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC); 44 45 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX25_CCM); 46 47 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { 48 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL); 49 } 50 51 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { 52 object_initialize_child(obj, "gpt[*]", &s->gpt[i], TYPE_IMX25_GPT); 53 } 54 55 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { 56 object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT); 57 } 58 59 object_initialize_child(obj, "fec", &s->fec, TYPE_IMX_FEC); 60 61 object_initialize_child(obj, "rngc", &s->rngc, TYPE_IMX_RNGC); 62 63 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { 64 object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C); 65 } 66 67 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { 68 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO); 69 } 70 71 for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { 72 object_initialize_child(obj, "sdhc[*]", &s->esdhc[i], TYPE_IMX_USDHC); 73 } 74 75 for (i = 0; i < FSL_IMX25_NUM_USBS; i++) { 76 object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_CHIPIDEA); 77 } 78 79 object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT); 80 } 81 82 static void fsl_imx25_realize(DeviceState *dev, Error **errp) 83 { 84 FslIMX25State *s = FSL_IMX25(dev); 85 uint8_t i; 86 Error *err = NULL; 87 88 if (!qdev_realize(DEVICE(&s->cpu), NULL, &err)) { 89 error_propagate(errp, err); 90 return; 91 } 92 93 if (!sysbus_realize(SYS_BUS_DEVICE(&s->avic), &err)) { 94 error_propagate(errp, err); 95 return; 96 } 97 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR); 98 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, 99 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 100 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, 101 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 102 103 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err)) { 104 error_propagate(errp, err); 105 return; 106 } 107 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR); 108 109 /* Initialize all UARTs */ 110 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { 111 static const struct { 112 hwaddr addr; 113 unsigned int irq; 114 } serial_table[FSL_IMX25_NUM_UARTS] = { 115 { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ }, 116 { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ }, 117 { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ }, 118 { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ }, 119 { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ } 120 }; 121 122 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 123 124 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err)) { 125 error_propagate(errp, err); 126 return; 127 } 128 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 129 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 130 qdev_get_gpio_in(DEVICE(&s->avic), 131 serial_table[i].irq)); 132 } 133 134 /* Initialize all GPT timers */ 135 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { 136 static const struct { 137 hwaddr addr; 138 unsigned int irq; 139 } gpt_table[FSL_IMX25_NUM_GPTS] = { 140 { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ }, 141 { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ }, 142 { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ }, 143 { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ } 144 }; 145 146 s->gpt[i].ccm = IMX_CCM(&s->ccm); 147 148 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &err)) { 149 error_propagate(errp, err); 150 return; 151 } 152 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr); 153 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, 154 qdev_get_gpio_in(DEVICE(&s->avic), 155 gpt_table[i].irq)); 156 } 157 158 /* Initialize all EPIT timers */ 159 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { 160 static const struct { 161 hwaddr addr; 162 unsigned int irq; 163 } epit_table[FSL_IMX25_NUM_EPITS] = { 164 { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ }, 165 { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ } 166 }; 167 168 s->epit[i].ccm = IMX_CCM(&s->ccm); 169 170 if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err)) { 171 error_propagate(errp, err); 172 return; 173 } 174 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 175 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 176 qdev_get_gpio_in(DEVICE(&s->avic), 177 epit_table[i].irq)); 178 } 179 180 qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]); 181 182 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fec), &err)) { 183 error_propagate(errp, err); 184 return; 185 } 186 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR); 187 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0, 188 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ)); 189 190 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rngc), &err)) { 191 error_propagate(errp, err); 192 return; 193 } 194 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR); 195 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0, 196 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ)); 197 198 /* Initialize all I2C */ 199 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { 200 static const struct { 201 hwaddr addr; 202 unsigned int irq; 203 } i2c_table[FSL_IMX25_NUM_I2CS] = { 204 { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ }, 205 { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ }, 206 { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ } 207 }; 208 209 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err)) { 210 error_propagate(errp, err); 211 return; 212 } 213 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 214 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 215 qdev_get_gpio_in(DEVICE(&s->avic), 216 i2c_table[i].irq)); 217 } 218 219 /* Initialize all GPIOs */ 220 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { 221 static const struct { 222 hwaddr addr; 223 unsigned int irq; 224 } gpio_table[FSL_IMX25_NUM_GPIOS] = { 225 { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ }, 226 { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ }, 227 { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ }, 228 { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ } 229 }; 230 231 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err)) { 232 error_propagate(errp, err); 233 return; 234 } 235 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 236 /* Connect GPIO IRQ to PIC */ 237 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 238 qdev_get_gpio_in(DEVICE(&s->avic), 239 gpio_table[i].irq)); 240 } 241 242 /* Initialize all SDHC */ 243 for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { 244 static const struct { 245 hwaddr addr; 246 unsigned int irq; 247 } esdhc_table[FSL_IMX25_NUM_ESDHCS] = { 248 { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ }, 249 { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ }, 250 }; 251 252 object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version", 253 &error_abort); 254 object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES, 255 "capareg", 256 &error_abort); 257 object_property_set_uint(OBJECT(&s->esdhc[i]), SDHCI_VENDOR_IMX, 258 "vendor", 259 &error_abort); 260 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err)) { 261 error_propagate(errp, err); 262 return; 263 } 264 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); 265 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, 266 qdev_get_gpio_in(DEVICE(&s->avic), 267 esdhc_table[i].irq)); 268 } 269 270 /* USB */ 271 for (i = 0; i < FSL_IMX25_NUM_USBS; i++) { 272 static const struct { 273 hwaddr addr; 274 unsigned int irq; 275 } usb_table[FSL_IMX25_NUM_USBS] = { 276 { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ }, 277 { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ }, 278 }; 279 280 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); 281 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr); 282 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, 283 qdev_get_gpio_in(DEVICE(&s->avic), 284 usb_table[i].irq)); 285 } 286 287 /* Watchdog */ 288 object_property_set_bool(OBJECT(&s->wdt), true, "pretimeout-support", 289 &error_abort); 290 sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort); 291 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR); 292 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0, 293 qdev_get_gpio_in(DEVICE(&s->avic), 294 FSL_IMX25_WDT_IRQ)); 295 296 /* initialize 2 x 16 KB ROM */ 297 memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0", 298 FSL_IMX25_ROM0_SIZE, &err); 299 if (err) { 300 error_propagate(errp, err); 301 return; 302 } 303 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR, 304 &s->rom[0]); 305 memory_region_init_rom(&s->rom[1], OBJECT(dev), "imx25.rom1", 306 FSL_IMX25_ROM1_SIZE, &err); 307 if (err) { 308 error_propagate(errp, err); 309 return; 310 } 311 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR, 312 &s->rom[1]); 313 314 /* initialize internal RAM (128 KB) */ 315 memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE, 316 &err); 317 if (err) { 318 error_propagate(errp, err); 319 return; 320 } 321 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR, 322 &s->iram); 323 324 /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */ 325 memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx25.iram_alias", 326 &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE); 327 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR, 328 &s->iram_alias); 329 } 330 331 static void fsl_imx25_class_init(ObjectClass *oc, void *data) 332 { 333 DeviceClass *dc = DEVICE_CLASS(oc); 334 335 dc->realize = fsl_imx25_realize; 336 dc->desc = "i.MX25 SOC"; 337 /* 338 * Reason: uses serial_hds in realize and the imx25 board does not 339 * support multiple CPUs 340 */ 341 dc->user_creatable = false; 342 } 343 344 static const TypeInfo fsl_imx25_type_info = { 345 .name = TYPE_FSL_IMX25, 346 .parent = TYPE_DEVICE, 347 .instance_size = sizeof(FslIMX25State), 348 .instance_init = fsl_imx25_init, 349 .class_init = fsl_imx25_class_init, 350 }; 351 352 static void fsl_imx25_register_types(void) 353 { 354 type_register_static(&fsl_imx25_type_info); 355 } 356 357 type_init(fsl_imx25_register_types) 358