1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "hw/cpu/a9mpcore.h" 28 #include "hw/irq.h" 29 #include "sysemu/blockdev.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/sysbus.h" 32 #include "hw/arm/boot.h" 33 #include "hw/loader.h" 34 #include "hw/qdev-properties.h" 35 #include "hw/arm/exynos4210.h" 36 #include "hw/sd/sdhci.h" 37 #include "hw/usb/hcd-ehci.h" 38 39 #define EXYNOS4210_CHIPID_ADDR 0x10000000 40 41 /* PWM */ 42 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 43 44 /* RTC */ 45 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 46 47 /* MCT */ 48 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 49 50 /* I2C */ 51 #define EXYNOS4210_I2C_SHIFT 0x00010000 52 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 53 /* Interrupt Group of External Interrupt Combiner for I2C */ 54 #define EXYNOS4210_I2C_INTG 27 55 #define EXYNOS4210_HDMI_INTG 16 56 57 /* UART's definitions */ 58 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 59 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 60 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 61 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 62 #define EXYNOS4210_UART0_FIFO_SIZE 256 63 #define EXYNOS4210_UART1_FIFO_SIZE 64 64 #define EXYNOS4210_UART2_FIFO_SIZE 16 65 #define EXYNOS4210_UART3_FIFO_SIZE 16 66 /* Interrupt Group of External Interrupt Combiner for UART */ 67 #define EXYNOS4210_UART_INT_GRP 26 68 69 /* External GIC */ 70 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 71 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 72 73 /* Combiner */ 74 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 75 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 76 77 /* SD/MMC host controllers */ 78 #define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 79 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 80 #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ 81 0x00010000 * (n)) 82 #define EXYNOS4210_SDHCI_NUMBER 4 83 84 /* PMU SFR base address */ 85 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 86 87 /* Clock controller SFR base address */ 88 #define EXYNOS4210_CLK_BASE_ADDR 0x10030000 89 90 /* PRNG/HASH SFR base address */ 91 #define EXYNOS4210_RNG_BASE_ADDR 0x10830400 92 93 /* Display controllers (FIMD) */ 94 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 95 96 /* EHCI */ 97 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 98 99 /* DMA */ 100 #define EXYNOS4210_PL330_BASE0_ADDR 0x12680000 101 #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 102 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 103 104 enum ExtGicId { 105 EXT_GIC_ID_MDMA_LCD0 = 66, 106 EXT_GIC_ID_PDMA0, 107 EXT_GIC_ID_PDMA1, 108 EXT_GIC_ID_TIMER0, 109 EXT_GIC_ID_TIMER1, 110 EXT_GIC_ID_TIMER2, 111 EXT_GIC_ID_TIMER3, 112 EXT_GIC_ID_TIMER4, 113 EXT_GIC_ID_MCT_L0, 114 EXT_GIC_ID_WDT, 115 EXT_GIC_ID_RTC_ALARM, 116 EXT_GIC_ID_RTC_TIC, 117 EXT_GIC_ID_GPIO_XB, 118 EXT_GIC_ID_GPIO_XA, 119 EXT_GIC_ID_MCT_L1, 120 EXT_GIC_ID_IEM_APC, 121 EXT_GIC_ID_IEM_IEC, 122 EXT_GIC_ID_NFC, 123 EXT_GIC_ID_UART0, 124 EXT_GIC_ID_UART1, 125 EXT_GIC_ID_UART2, 126 EXT_GIC_ID_UART3, 127 EXT_GIC_ID_UART4, 128 EXT_GIC_ID_MCT_G0, 129 EXT_GIC_ID_I2C0, 130 EXT_GIC_ID_I2C1, 131 EXT_GIC_ID_I2C2, 132 EXT_GIC_ID_I2C3, 133 EXT_GIC_ID_I2C4, 134 EXT_GIC_ID_I2C5, 135 EXT_GIC_ID_I2C6, 136 EXT_GIC_ID_I2C7, 137 EXT_GIC_ID_SPI0, 138 EXT_GIC_ID_SPI1, 139 EXT_GIC_ID_SPI2, 140 EXT_GIC_ID_MCT_G1, 141 EXT_GIC_ID_USB_HOST, 142 EXT_GIC_ID_USB_DEVICE, 143 EXT_GIC_ID_MODEMIF, 144 EXT_GIC_ID_HSMMC0, 145 EXT_GIC_ID_HSMMC1, 146 EXT_GIC_ID_HSMMC2, 147 EXT_GIC_ID_HSMMC3, 148 EXT_GIC_ID_SDMMC, 149 EXT_GIC_ID_MIPI_CSI_4LANE, 150 EXT_GIC_ID_MIPI_DSI_4LANE, 151 EXT_GIC_ID_MIPI_CSI_2LANE, 152 EXT_GIC_ID_MIPI_DSI_2LANE, 153 EXT_GIC_ID_ONENAND_AUDI, 154 EXT_GIC_ID_ROTATOR, 155 EXT_GIC_ID_FIMC0, 156 EXT_GIC_ID_FIMC1, 157 EXT_GIC_ID_FIMC2, 158 EXT_GIC_ID_FIMC3, 159 EXT_GIC_ID_JPEG, 160 EXT_GIC_ID_2D, 161 EXT_GIC_ID_PCIe, 162 EXT_GIC_ID_MIXER, 163 EXT_GIC_ID_HDMI, 164 EXT_GIC_ID_HDMI_I2C, 165 EXT_GIC_ID_MFC, 166 EXT_GIC_ID_TVENC, 167 }; 168 169 enum ExtInt { 170 EXT_GIC_ID_EXTINT0 = 48, 171 EXT_GIC_ID_EXTINT1, 172 EXT_GIC_ID_EXTINT2, 173 EXT_GIC_ID_EXTINT3, 174 EXT_GIC_ID_EXTINT4, 175 EXT_GIC_ID_EXTINT5, 176 EXT_GIC_ID_EXTINT6, 177 EXT_GIC_ID_EXTINT7, 178 EXT_GIC_ID_EXTINT8, 179 EXT_GIC_ID_EXTINT9, 180 EXT_GIC_ID_EXTINT10, 181 EXT_GIC_ID_EXTINT11, 182 EXT_GIC_ID_EXTINT12, 183 EXT_GIC_ID_EXTINT13, 184 EXT_GIC_ID_EXTINT14, 185 EXT_GIC_ID_EXTINT15 186 }; 187 188 /* 189 * External GIC sources which are not from External Interrupt Combiner or 190 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, 191 * which is INTG16 in Internal Interrupt Combiner. 192 */ 193 194 static const uint32_t 195 combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { 196 /* int combiner groups 16-19 */ 197 { }, { }, { }, { }, 198 /* int combiner group 20 */ 199 { 0, EXT_GIC_ID_MDMA_LCD0 }, 200 /* int combiner group 21 */ 201 { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, 202 /* int combiner group 22 */ 203 { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, 204 EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, 205 /* int combiner group 23 */ 206 { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, 207 /* int combiner group 24 */ 208 { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, 209 /* int combiner group 25 */ 210 { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, 211 /* int combiner group 26 */ 212 { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, 213 EXT_GIC_ID_UART4 }, 214 /* int combiner group 27 */ 215 { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, 216 EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, 217 EXT_GIC_ID_I2C7 }, 218 /* int combiner group 28 */ 219 { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, 220 /* int combiner group 29 */ 221 { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, 222 EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, 223 /* int combiner group 30 */ 224 { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, 225 /* int combiner group 31 */ 226 { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, 227 /* int combiner group 32 */ 228 { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, 229 /* int combiner group 33 */ 230 { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, 231 /* int combiner group 34 */ 232 { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, 233 /* int combiner group 35 */ 234 { 0, 0, 0, EXT_GIC_ID_MCT_L1 }, 235 /* int combiner group 36 */ 236 { EXT_GIC_ID_MIXER }, 237 /* int combiner group 37 */ 238 { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, 239 EXT_GIC_ID_EXTINT7 }, 240 /* groups 38-50 */ 241 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, 242 /* int combiner group 51 */ 243 { EXT_GIC_ID_MCT_L0 }, 244 /* group 52 */ 245 { }, 246 /* int combiner group 53 */ 247 { EXT_GIC_ID_WDT }, 248 /* groups 54-63 */ 249 { }, { }, { }, { }, { }, { }, { }, { }, { }, { } 250 }; 251 252 #define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit)) 253 #define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) 254 #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ 255 ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) 256 257 /* 258 * Some interrupt lines go to multiple combiner inputs. 259 * This data structure defines those: each array element is 260 * a list of combiner inputs which are connected together; 261 * the one with the smallest interrupt ID value must be first. 262 * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being 263 * wired to anything so we can use 0 as a terminator. 264 */ 265 #define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B) 266 #define IRQNONE 0 267 268 #define COMBINERMAP_SIZE 16 269 270 static const int combinermap[COMBINERMAP_SIZE][6] = { 271 /* MDNIE_LCD1 */ 272 { IRQNO(0, 4), IRQNO(1, 0), IRQNONE }, 273 { IRQNO(0, 5), IRQNO(1, 1), IRQNONE }, 274 { IRQNO(0, 6), IRQNO(1, 2), IRQNONE }, 275 { IRQNO(0, 7), IRQNO(1, 3), IRQNONE }, 276 /* TMU */ 277 { IRQNO(2, 4), IRQNO(3, 4), IRQNONE }, 278 { IRQNO(2, 5), IRQNO(3, 5), IRQNONE }, 279 { IRQNO(2, 6), IRQNO(3, 6), IRQNONE }, 280 { IRQNO(2, 7), IRQNO(3, 7), IRQNONE }, 281 /* LCD1 */ 282 { IRQNO(11, 4), IRQNO(12, 0), IRQNONE }, 283 { IRQNO(11, 5), IRQNO(12, 1), IRQNONE }, 284 { IRQNO(11, 6), IRQNO(12, 2), IRQNONE }, 285 { IRQNO(11, 7), IRQNO(12, 3), IRQNONE }, 286 /* Multi-core timer */ 287 { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE }, 288 { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE }, 289 { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE }, 290 { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE }, 291 }; 292 293 #undef IRQNO 294 295 static const int *combinermap_entry(int irq) 296 { 297 /* 298 * If the interrupt number passed in is the first entry in some 299 * line of the combinermap, return a pointer to that line; 300 * otherwise return NULL. 301 */ 302 int i; 303 for (i = 0; i < COMBINERMAP_SIZE; i++) { 304 if (combinermap[i][0] == irq) { 305 return combinermap[i]; 306 } 307 } 308 return NULL; 309 } 310 311 static int mapline_size(const int *mapline) 312 { 313 /* Return number of entries in this mapline in total */ 314 int i = 0; 315 316 if (!mapline) { 317 /* Not in the map? IRQ goes to exactly one combiner input */ 318 return 1; 319 } 320 while (*mapline != IRQNONE) { 321 mapline++; 322 i++; 323 } 324 return i; 325 } 326 327 /* 328 * Initialize board IRQs. 329 * These IRQs contain splitted Int/External Combiner and External Gic IRQs. 330 */ 331 static void exynos4210_init_board_irqs(Exynos4210State *s) 332 { 333 uint32_t grp, bit, irq_id, n; 334 DeviceState *extgicdev = DEVICE(&s->ext_gic); 335 DeviceState *intcdev = DEVICE(&s->int_combiner); 336 DeviceState *extcdev = DEVICE(&s->ext_combiner); 337 int splitcount = 0; 338 DeviceState *splitter; 339 const int *mapline; 340 int numlines, splitin, in; 341 342 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { 343 irq_id = 0; 344 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) { 345 /* MCT_G0 is passed to External GIC */ 346 irq_id = EXT_GIC_ID_MCT_G0; 347 } 348 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) { 349 /* MCT_G1 is passed to External and GIC */ 350 irq_id = EXT_GIC_ID_MCT_G1; 351 } 352 353 if (s->irq_table[n]) { 354 /* 355 * This must be some non-first entry in a combinermap line, 356 * and we've already filled it in. 357 */ 358 continue; 359 } 360 mapline = combinermap_entry(n); 361 /* 362 * We need to connect the IRQ to multiple inputs on both combiners 363 * and possibly also to the external GIC. 364 */ 365 numlines = 2 * mapline_size(mapline); 366 if (irq_id) { 367 numlines++; 368 } 369 assert(splitcount < EXYNOS4210_NUM_SPLITTERS); 370 splitter = DEVICE(&s->splitter[splitcount]); 371 qdev_prop_set_uint16(splitter, "num-lines", numlines); 372 qdev_realize(splitter, NULL, &error_abort); 373 splitcount++; 374 375 in = n; 376 splitin = 0; 377 for (;;) { 378 s->irq_table[in] = qdev_get_gpio_in(splitter, 0); 379 qdev_connect_gpio_out(splitter, splitin, 380 qdev_get_gpio_in(intcdev, in)); 381 qdev_connect_gpio_out(splitter, splitin + 1, 382 qdev_get_gpio_in(extcdev, in)); 383 splitin += 2; 384 if (!mapline) { 385 break; 386 } 387 mapline++; 388 in = *mapline; 389 if (in == IRQNONE) { 390 break; 391 } 392 } 393 if (irq_id) { 394 qdev_connect_gpio_out(splitter, splitin, 395 qdev_get_gpio_in(extgicdev, irq_id - 32)); 396 } 397 } 398 for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { 399 /* these IDs are passed to Internal Combiner and External GIC */ 400 grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); 401 bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); 402 irq_id = combiner_grp_to_gic_id[grp - 403 EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; 404 405 if (s->irq_table[n]) { 406 /* 407 * This must be some non-first entry in a combinermap line, 408 * and we've already filled it in. 409 */ 410 continue; 411 } 412 413 if (irq_id) { 414 assert(splitcount < EXYNOS4210_NUM_SPLITTERS); 415 splitter = DEVICE(&s->splitter[splitcount]); 416 qdev_prop_set_uint16(splitter, "num-lines", 2); 417 qdev_realize(splitter, NULL, &error_abort); 418 splitcount++; 419 s->irq_table[n] = qdev_get_gpio_in(splitter, 0); 420 qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n)); 421 qdev_connect_gpio_out(splitter, 1, 422 qdev_get_gpio_in(extgicdev, irq_id - 32)); 423 } else { 424 s->irq_table[n] = qdev_get_gpio_in(intcdev, n); 425 } 426 } 427 /* 428 * We check this here to avoid a more obscure assert later when 429 * qdev_assert_realized_properly() checks that we realized every 430 * child object we initialized. 431 */ 432 assert(splitcount == EXYNOS4210_NUM_SPLITTERS); 433 } 434 435 /* 436 * Get IRQ number from exynos4210 IRQ subsystem stub. 437 * To identify IRQ source use internal combiner group and bit number 438 * grp - group number 439 * bit - bit number inside group 440 */ 441 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) 442 { 443 return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); 444 } 445 446 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 447 0x09, 0x00, 0x00, 0x00 }; 448 449 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 450 unsigned size) 451 { 452 assert(offset < sizeof(chipid_and_omr)); 453 return chipid_and_omr[offset]; 454 } 455 456 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 457 uint64_t value, unsigned size) 458 { 459 return; 460 } 461 462 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 463 .read = exynos4210_chipid_and_omr_read, 464 .write = exynos4210_chipid_and_omr_write, 465 .endianness = DEVICE_NATIVE_ENDIAN, 466 .impl = { 467 .max_access_size = 1, 468 } 469 }; 470 471 void exynos4210_write_secondary(ARMCPU *cpu, 472 const struct arm_boot_info *info) 473 { 474 int n; 475 uint32_t smpboot[] = { 476 0xe59f3034, /* ldr r3, External gic_cpu_if */ 477 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 478 0xe59f0034, /* ldr r0, startaddr */ 479 0xe3a01001, /* mov r1, #1 */ 480 0xe5821000, /* str r1, [r2] */ 481 0xe5831000, /* str r1, [r3] */ 482 0xe3a010ff, /* mov r1, #0xff */ 483 0xe5821004, /* str r1, [r2, #4] */ 484 0xe5831004, /* str r1, [r3, #4] */ 485 0xf57ff04f, /* dsb */ 486 0xe320f003, /* wfi */ 487 0xe5901000, /* ldr r1, [r0] */ 488 0xe1110001, /* tst r1, r1 */ 489 0x0afffffb, /* beq <wfi> */ 490 0xe12fff11, /* bx r1 */ 491 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 492 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 493 0 /* bootreg: Boot register address is held here */ 494 }; 495 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 496 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 497 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 498 smpboot[n] = tswap32(smpboot[n]); 499 } 500 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 501 info->smp_loader_start); 502 } 503 504 static uint64_t exynos4210_calc_affinity(int cpu) 505 { 506 /* Exynos4210 has 0x9 as cluster ID */ 507 return (0x9 << ARM_AFF1_SHIFT) | cpu; 508 } 509 510 static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate, 511 qemu_irq irq, int nreq, int nevents, int width) 512 { 513 SysBusDevice *busdev; 514 DeviceState *dev; 515 int i; 516 517 dev = qdev_new("pl330"); 518 object_property_set_link(OBJECT(dev), "memory", 519 OBJECT(get_system_memory()), 520 &error_fatal); 521 qdev_prop_set_uint8(dev, "num_events", nevents); 522 qdev_prop_set_uint8(dev, "num_chnls", 8); 523 qdev_prop_set_uint8(dev, "num_periph_req", nreq); 524 525 qdev_prop_set_uint8(dev, "wr_cap", 4); 526 qdev_prop_set_uint8(dev, "wr_q_dep", 8); 527 qdev_prop_set_uint8(dev, "rd_cap", 4); 528 qdev_prop_set_uint8(dev, "rd_q_dep", 8); 529 qdev_prop_set_uint8(dev, "data_width", width); 530 qdev_prop_set_uint16(dev, "data_buffer_dep", width); 531 busdev = SYS_BUS_DEVICE(dev); 532 sysbus_realize_and_unref(busdev, &error_fatal); 533 sysbus_mmio_map(busdev, 0, base); 534 535 object_property_set_int(OBJECT(orgate), "num-lines", nevents + 1, 536 &error_abort); 537 qdev_realize(DEVICE(orgate), NULL, &error_abort); 538 539 for (i = 0; i < nevents + 1; i++) { 540 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i)); 541 } 542 qdev_connect_gpio_out(DEVICE(orgate), 0, irq); 543 return dev; 544 } 545 546 static void exynos4210_realize(DeviceState *socdev, Error **errp) 547 { 548 Exynos4210State *s = EXYNOS4210_SOC(socdev); 549 MemoryRegion *system_mem = get_system_memory(); 550 SysBusDevice *busdev; 551 DeviceState *dev, *uart[4], *pl330[3]; 552 int i, n; 553 554 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 555 Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); 556 557 /* By default A9 CPUs have EL3 enabled. This board does not currently 558 * support EL3 so the CPU EL3 property is disabled before realization. 559 */ 560 if (object_property_find(cpuobj, "has_el3")) { 561 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 562 } 563 564 s->cpu[n] = ARM_CPU(cpuobj); 565 object_property_set_int(cpuobj, "mp-affinity", 566 exynos4210_calc_affinity(n), &error_abort); 567 object_property_set_int(cpuobj, "reset-cbar", 568 EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 569 &error_abort); 570 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 571 } 572 573 /* IRQ Gate */ 574 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 575 DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); 576 object_property_set_int(OBJECT(orgate), "num-lines", 577 EXYNOS4210_IRQ_GATE_NINPUTS, 578 &error_abort); 579 qdev_realize(orgate, NULL, &error_abort); 580 qdev_connect_gpio_out(orgate, 0, 581 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 582 } 583 584 /* Private memory region and Internal GIC */ 585 qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); 586 busdev = SYS_BUS_DEVICE(&s->a9mpcore); 587 sysbus_realize(busdev, &error_fatal); 588 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 589 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 590 sysbus_connect_irq(busdev, n, 591 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); 592 } 593 594 /* Cache controller */ 595 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 596 597 /* External GIC */ 598 qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS); 599 busdev = SYS_BUS_DEVICE(&s->ext_gic); 600 sysbus_realize(busdev, &error_fatal); 601 /* Map CPU interface */ 602 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 603 /* Map Distributer interface */ 604 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 605 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 606 sysbus_connect_irq(busdev, n, 607 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); 608 } 609 610 /* Internal Interrupt Combiner */ 611 busdev = SYS_BUS_DEVICE(&s->int_combiner); 612 sysbus_realize(busdev, &error_fatal); 613 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 614 sysbus_connect_irq(busdev, n, 615 qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); 616 } 617 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 618 619 /* External Interrupt Combiner */ 620 qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1); 621 busdev = SYS_BUS_DEVICE(&s->ext_combiner); 622 sysbus_realize(busdev, &error_fatal); 623 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 624 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); 625 } 626 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 627 628 /* Initialize board IRQs. */ 629 exynos4210_init_board_irqs(s); 630 631 /*** Memory ***/ 632 633 /* Chip-ID and OMR */ 634 memory_region_init_io(&s->chipid_mem, OBJECT(socdev), 635 &exynos4210_chipid_and_omr_ops, NULL, 636 "exynos4210.chipid", sizeof(chipid_and_omr)); 637 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 638 &s->chipid_mem); 639 640 /* Internal ROM */ 641 memory_region_init_rom(&s->irom_mem, OBJECT(socdev), "exynos4210.irom", 642 EXYNOS4210_IROM_SIZE, &error_fatal); 643 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 644 &s->irom_mem); 645 /* mirror of iROM */ 646 memory_region_init_alias(&s->irom_alias_mem, OBJECT(socdev), 647 "exynos4210.irom_alias", &s->irom_mem, 0, 648 EXYNOS4210_IROM_SIZE); 649 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 650 &s->irom_alias_mem); 651 652 /* Internal RAM */ 653 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 654 EXYNOS4210_IRAM_SIZE, &error_fatal); 655 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 656 &s->iram_mem); 657 658 /* PMU. 659 * The only reason of existence at the moment is that secondary CPU boot 660 * loader uses PMU INFORM5 register as a holding pen. 661 */ 662 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 663 664 sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL); 665 sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL); 666 667 /* PWM */ 668 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 669 s->irq_table[exynos4210_get_irq(22, 0)], 670 s->irq_table[exynos4210_get_irq(22, 1)], 671 s->irq_table[exynos4210_get_irq(22, 2)], 672 s->irq_table[exynos4210_get_irq(22, 3)], 673 s->irq_table[exynos4210_get_irq(22, 4)], 674 NULL); 675 /* RTC */ 676 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 677 s->irq_table[exynos4210_get_irq(23, 0)], 678 s->irq_table[exynos4210_get_irq(23, 1)], 679 NULL); 680 681 /* Multi Core Timer */ 682 dev = qdev_new("exynos4210.mct"); 683 busdev = SYS_BUS_DEVICE(dev); 684 sysbus_realize_and_unref(busdev, &error_fatal); 685 for (n = 0; n < 4; n++) { 686 /* Connect global timer interrupts to Combiner gpio_in */ 687 sysbus_connect_irq(busdev, n, 688 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 689 } 690 /* Connect local timer interrupts to Combiner gpio_in */ 691 sysbus_connect_irq(busdev, 4, 692 s->irq_table[exynos4210_get_irq(51, 0)]); 693 sysbus_connect_irq(busdev, 5, 694 s->irq_table[exynos4210_get_irq(35, 3)]); 695 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 696 697 /*** I2C ***/ 698 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 699 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 700 qemu_irq i2c_irq; 701 702 if (n < 8) { 703 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 704 } else { 705 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 706 } 707 708 dev = qdev_new("exynos4210.i2c"); 709 busdev = SYS_BUS_DEVICE(dev); 710 sysbus_realize_and_unref(busdev, &error_fatal); 711 sysbus_connect_irq(busdev, 0, i2c_irq); 712 sysbus_mmio_map(busdev, 0, addr); 713 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 714 } 715 716 717 /*** UARTs ***/ 718 uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 719 EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0), 720 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 721 722 uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 723 EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1), 724 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 725 726 uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 727 EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2), 728 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 729 730 uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 731 EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3), 732 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 733 734 /*** SD/MMC host controllers ***/ 735 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { 736 DeviceState *carddev; 737 BlockBackend *blk; 738 DriveInfo *di; 739 740 /* Compatible with: 741 * - SD Host Controller Specification Version 2.0 742 * - SDIO Specification Version 2.0 743 * - MMC Specification Version 4.3 744 * - SDMA 745 * - ADMA2 746 * 747 * As this part of the Exynos4210 is not publically available, 748 * we used the "HS-MMC Controller S3C2416X RISC Microprocessor" 749 * public datasheet which is very similar (implementing 750 * MMC Specification Version 4.0 being the only difference noted) 751 */ 752 dev = qdev_new(TYPE_S3C_SDHCI); 753 qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); 754 755 busdev = SYS_BUS_DEVICE(dev); 756 sysbus_realize_and_unref(busdev, &error_fatal); 757 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); 758 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); 759 760 di = drive_get(IF_SD, 0, n); 761 blk = di ? blk_by_legacy_dinfo(di) : NULL; 762 carddev = qdev_new(TYPE_SD_CARD); 763 qdev_prop_set_drive(carddev, "drive", blk); 764 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), 765 &error_fatal); 766 } 767 768 /*** Display controller (FIMD) ***/ 769 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 770 s->irq_table[exynos4210_get_irq(11, 0)], 771 s->irq_table[exynos4210_get_irq(11, 1)], 772 s->irq_table[exynos4210_get_irq(11, 2)], 773 NULL); 774 775 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 776 s->irq_table[exynos4210_get_irq(28, 3)]); 777 778 /*** DMA controllers ***/ 779 pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR, 780 &s->pl330_irq_orgate[0], 781 s->irq_table[exynos4210_get_irq(21, 0)], 782 32, 32, 32); 783 pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR, 784 &s->pl330_irq_orgate[1], 785 s->irq_table[exynos4210_get_irq(21, 1)], 786 32, 32, 32); 787 pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR, 788 &s->pl330_irq_orgate[2], 789 s->irq_table[exynos4210_get_irq(20, 1)], 790 1, 31, 64); 791 792 sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1, 793 qdev_get_gpio_in(pl330[0], 15)); 794 sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1, 795 qdev_get_gpio_in(pl330[1], 15)); 796 sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1, 797 qdev_get_gpio_in(pl330[0], 17)); 798 sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1, 799 qdev_get_gpio_in(pl330[1], 17)); 800 } 801 802 static void exynos4210_init(Object *obj) 803 { 804 Exynos4210State *s = EXYNOS4210_SOC(obj); 805 int i; 806 807 for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { 808 char *name = g_strdup_printf("pl330-irq-orgate%d", i); 809 qemu_or_irq *orgate = &s->pl330_irq_orgate[i]; 810 811 object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); 812 g_free(name); 813 } 814 815 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { 816 g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); 817 object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); 818 } 819 820 for (i = 0; i < ARRAY_SIZE(s->splitter); i++) { 821 g_autofree char *name = g_strdup_printf("irq-splitter%d", i); 822 object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ); 823 } 824 825 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 826 object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); 827 object_initialize_child(obj, "int-combiner", &s->int_combiner, 828 TYPE_EXYNOS4210_COMBINER); 829 object_initialize_child(obj, "ext-combiner", &s->ext_combiner, 830 TYPE_EXYNOS4210_COMBINER); 831 } 832 833 static void exynos4210_class_init(ObjectClass *klass, void *data) 834 { 835 DeviceClass *dc = DEVICE_CLASS(klass); 836 837 dc->realize = exynos4210_realize; 838 } 839 840 static const TypeInfo exynos4210_info = { 841 .name = TYPE_EXYNOS4210_SOC, 842 .parent = TYPE_SYS_BUS_DEVICE, 843 .instance_size = sizeof(Exynos4210State), 844 .instance_init = exynos4210_init, 845 .class_init = exynos4210_class_init, 846 }; 847 848 static void exynos4210_register_types(void) 849 { 850 type_register_static(&exynos4210_info); 851 } 852 853 type_init(exynos4210_register_types) 854