xref: /openbmc/qemu/hw/arm/exynos4210.c (revision d0f0cd5b)
1 /*
2  *  Samsung exynos4210 SoC emulation
3  *
4  *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
5  *    Maksim Kozlov <m.kozlov@samsung.com>
6  *    Evgeny Voevodin <e.voevodin@samsung.com>
7  *    Igor Mitsyanko  <i.mitsyanko@samsung.com>
8  *
9  *  This program is free software; you can redistribute it and/or modify it
10  *  under the terms of the GNU General Public License as published by the
11  *  Free Software Foundation; either version 2 of the License, or
12  *  (at your option) any later version.
13  *
14  *  This program is distributed in the hope that it will be useful, but WITHOUT
15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17  *  for more details.
18  *
19  *  You should have received a copy of the GNU General Public License along
20  *  with this program; if not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23 
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "exec/tswap.h"
27 #include "cpu.h"
28 #include "hw/cpu/a9mpcore.h"
29 #include "hw/irq.h"
30 #include "sysemu/blockdev.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/sysbus.h"
33 #include "hw/arm/boot.h"
34 #include "hw/loader.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/arm/exynos4210.h"
37 #include "hw/sd/sdhci.h"
38 #include "hw/usb/hcd-ehci.h"
39 #include "target/arm/cpu-qom.h"
40 
41 #define EXYNOS4210_CHIPID_ADDR         0x10000000
42 
43 /* PWM */
44 #define EXYNOS4210_PWM_BASE_ADDR       0x139D0000
45 
46 /* RTC */
47 #define EXYNOS4210_RTC_BASE_ADDR       0x10070000
48 
49 /* MCT */
50 #define EXYNOS4210_MCT_BASE_ADDR       0x10050000
51 
52 /* I2C */
53 #define EXYNOS4210_I2C_SHIFT           0x00010000
54 #define EXYNOS4210_I2C_BASE_ADDR       0x13860000
55 /* Interrupt Group of External Interrupt Combiner for I2C */
56 #define EXYNOS4210_I2C_INTG            27
57 #define EXYNOS4210_HDMI_INTG           16
58 
59 /* UART's definitions */
60 #define EXYNOS4210_UART0_BASE_ADDR     0x13800000
61 #define EXYNOS4210_UART1_BASE_ADDR     0x13810000
62 #define EXYNOS4210_UART2_BASE_ADDR     0x13820000
63 #define EXYNOS4210_UART3_BASE_ADDR     0x13830000
64 #define EXYNOS4210_UART0_FIFO_SIZE     256
65 #define EXYNOS4210_UART1_FIFO_SIZE     64
66 #define EXYNOS4210_UART2_FIFO_SIZE     16
67 #define EXYNOS4210_UART3_FIFO_SIZE     16
68 /* Interrupt Group of External Interrupt Combiner for UART */
69 #define EXYNOS4210_UART_INT_GRP        26
70 
71 /* External GIC */
72 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR    0x10480000
73 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR   0x10490000
74 
75 /* Combiner */
76 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
77 #define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000
78 
79 /* SD/MMC host controllers */
80 #define EXYNOS4210_SDHCI_CAPABILITIES       0x05E80080
81 #define EXYNOS4210_SDHCI_BASE_ADDR          0x12510000
82 #define EXYNOS4210_SDHCI_ADDR(n)            (EXYNOS4210_SDHCI_BASE_ADDR + \
83                                                 0x00010000 * (n))
84 #define EXYNOS4210_SDHCI_NUMBER             4
85 
86 /* PMU SFR base address */
87 #define EXYNOS4210_PMU_BASE_ADDR            0x10020000
88 
89 /* Clock controller SFR base address */
90 #define EXYNOS4210_CLK_BASE_ADDR            0x10030000
91 
92 /* PRNG/HASH SFR base address */
93 #define EXYNOS4210_RNG_BASE_ADDR            0x10830400
94 
95 /* Display controllers (FIMD) */
96 #define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
97 
98 /* EHCI */
99 #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
100 
101 /* DMA */
102 #define EXYNOS4210_PL330_BASE0_ADDR         0x12680000
103 #define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
104 #define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
105 
106 enum ExtGicId {
107     EXT_GIC_ID_MDMA_LCD0 = 66,
108     EXT_GIC_ID_PDMA0,
109     EXT_GIC_ID_PDMA1,
110     EXT_GIC_ID_TIMER0,
111     EXT_GIC_ID_TIMER1,
112     EXT_GIC_ID_TIMER2,
113     EXT_GIC_ID_TIMER3,
114     EXT_GIC_ID_TIMER4,
115     EXT_GIC_ID_MCT_L0,
116     EXT_GIC_ID_WDT,
117     EXT_GIC_ID_RTC_ALARM,
118     EXT_GIC_ID_RTC_TIC,
119     EXT_GIC_ID_GPIO_XB,
120     EXT_GIC_ID_GPIO_XA,
121     EXT_GIC_ID_MCT_L1,
122     EXT_GIC_ID_IEM_APC,
123     EXT_GIC_ID_IEM_IEC,
124     EXT_GIC_ID_NFC,
125     EXT_GIC_ID_UART0,
126     EXT_GIC_ID_UART1,
127     EXT_GIC_ID_UART2,
128     EXT_GIC_ID_UART3,
129     EXT_GIC_ID_UART4,
130     EXT_GIC_ID_MCT_G0,
131     EXT_GIC_ID_I2C0,
132     EXT_GIC_ID_I2C1,
133     EXT_GIC_ID_I2C2,
134     EXT_GIC_ID_I2C3,
135     EXT_GIC_ID_I2C4,
136     EXT_GIC_ID_I2C5,
137     EXT_GIC_ID_I2C6,
138     EXT_GIC_ID_I2C7,
139     EXT_GIC_ID_SPI0,
140     EXT_GIC_ID_SPI1,
141     EXT_GIC_ID_SPI2,
142     EXT_GIC_ID_MCT_G1,
143     EXT_GIC_ID_USB_HOST,
144     EXT_GIC_ID_USB_DEVICE,
145     EXT_GIC_ID_MODEMIF,
146     EXT_GIC_ID_HSMMC0,
147     EXT_GIC_ID_HSMMC1,
148     EXT_GIC_ID_HSMMC2,
149     EXT_GIC_ID_HSMMC3,
150     EXT_GIC_ID_SDMMC,
151     EXT_GIC_ID_MIPI_CSI_4LANE,
152     EXT_GIC_ID_MIPI_DSI_4LANE,
153     EXT_GIC_ID_MIPI_CSI_2LANE,
154     EXT_GIC_ID_MIPI_DSI_2LANE,
155     EXT_GIC_ID_ONENAND_AUDI,
156     EXT_GIC_ID_ROTATOR,
157     EXT_GIC_ID_FIMC0,
158     EXT_GIC_ID_FIMC1,
159     EXT_GIC_ID_FIMC2,
160     EXT_GIC_ID_FIMC3,
161     EXT_GIC_ID_JPEG,
162     EXT_GIC_ID_2D,
163     EXT_GIC_ID_PCIe,
164     EXT_GIC_ID_MIXER,
165     EXT_GIC_ID_HDMI,
166     EXT_GIC_ID_HDMI_I2C,
167     EXT_GIC_ID_MFC,
168     EXT_GIC_ID_TVENC,
169 };
170 
171 enum ExtInt {
172     EXT_GIC_ID_EXTINT0 = 48,
173     EXT_GIC_ID_EXTINT1,
174     EXT_GIC_ID_EXTINT2,
175     EXT_GIC_ID_EXTINT3,
176     EXT_GIC_ID_EXTINT4,
177     EXT_GIC_ID_EXTINT5,
178     EXT_GIC_ID_EXTINT6,
179     EXT_GIC_ID_EXTINT7,
180     EXT_GIC_ID_EXTINT8,
181     EXT_GIC_ID_EXTINT9,
182     EXT_GIC_ID_EXTINT10,
183     EXT_GIC_ID_EXTINT11,
184     EXT_GIC_ID_EXTINT12,
185     EXT_GIC_ID_EXTINT13,
186     EXT_GIC_ID_EXTINT14,
187     EXT_GIC_ID_EXTINT15
188 };
189 
190 /*
191  * External GIC sources which are not from External Interrupt Combiner or
192  * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
193  * which is INTG16 in Internal Interrupt Combiner.
194  */
195 
196 static const uint32_t
197 combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
198     /* int combiner groups 16-19 */
199     { }, { }, { }, { },
200     /* int combiner group 20 */
201     { 0, EXT_GIC_ID_MDMA_LCD0 },
202     /* int combiner group 21 */
203     { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
204     /* int combiner group 22 */
205     { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
206             EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
207     /* int combiner group 23 */
208     { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
209     /* int combiner group 24 */
210     { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
211     /* int combiner group 25 */
212     { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
213     /* int combiner group 26 */
214     { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
215             EXT_GIC_ID_UART4 },
216     /* int combiner group 27 */
217     { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
218             EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
219             EXT_GIC_ID_I2C7 },
220     /* int combiner group 28 */
221     { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
222     /* int combiner group 29 */
223     { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
224      EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
225     /* int combiner group 30 */
226     { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
227     /* int combiner group 31 */
228     { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
229     /* int combiner group 32 */
230     { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
231     /* int combiner group 33 */
232     { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
233     /* int combiner group 34 */
234     { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
235     /* int combiner group 35 */
236     { 0, 0, 0, EXT_GIC_ID_MCT_L1 },
237     /* int combiner group 36 */
238     { EXT_GIC_ID_MIXER },
239     /* int combiner group 37 */
240     { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
241      EXT_GIC_ID_EXTINT7 },
242     /* groups 38-50 */
243     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
244     /* int combiner group 51 */
245     { EXT_GIC_ID_MCT_L0 },
246     /* group 52 */
247     { },
248     /* int combiner group 53 */
249     { EXT_GIC_ID_WDT },
250     /* groups 54-63 */
251     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
252 };
253 
254 #define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit)  ((grp) * 8 + (bit))
255 #define EXYNOS4210_COMBINER_GET_GRP_NUM(irq)       ((irq) / 8)
256 #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
257     ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
258 
259 /*
260  * Some interrupt lines go to multiple combiner inputs.
261  * This data structure defines those: each array element is
262  * a list of combiner inputs which are connected together;
263  * the one with the smallest interrupt ID value must be first.
264  * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being
265  * wired to anything so we can use 0 as a terminator.
266  */
267 #define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B)
268 #define IRQNONE 0
269 
270 #define COMBINERMAP_SIZE 16
271 
272 static const int combinermap[COMBINERMAP_SIZE][6] = {
273     /* MDNIE_LCD1 */
274     { IRQNO(0, 4), IRQNO(1, 0), IRQNONE },
275     { IRQNO(0, 5), IRQNO(1, 1), IRQNONE },
276     { IRQNO(0, 6), IRQNO(1, 2), IRQNONE },
277     { IRQNO(0, 7), IRQNO(1, 3), IRQNONE },
278     /* TMU */
279     { IRQNO(2, 4), IRQNO(3, 4), IRQNONE },
280     { IRQNO(2, 5), IRQNO(3, 5), IRQNONE },
281     { IRQNO(2, 6), IRQNO(3, 6), IRQNONE },
282     { IRQNO(2, 7), IRQNO(3, 7), IRQNONE },
283     /* LCD1 */
284     { IRQNO(11, 4), IRQNO(12, 0), IRQNONE },
285     { IRQNO(11, 5), IRQNO(12, 1), IRQNONE },
286     { IRQNO(11, 6), IRQNO(12, 2), IRQNONE },
287     { IRQNO(11, 7), IRQNO(12, 3), IRQNONE },
288     /* Multi-core timer */
289     { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE },
290     { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE },
291     { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE },
292     { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE },
293 };
294 
295 #undef IRQNO
296 
297 static const int *combinermap_entry(int irq)
298 {
299     /*
300      * If the interrupt number passed in is the first entry in some
301      * line of the combinermap, return a pointer to that line;
302      * otherwise return NULL.
303      */
304     int i;
305     for (i = 0; i < COMBINERMAP_SIZE; i++) {
306         if (combinermap[i][0] == irq) {
307             return combinermap[i];
308         }
309     }
310     return NULL;
311 }
312 
313 static int mapline_size(const int *mapline)
314 {
315     /* Return number of entries in this mapline in total */
316     int i = 0;
317 
318     if (!mapline) {
319         /* Not in the map? IRQ goes to exactly one combiner input */
320         return 1;
321     }
322     while (*mapline != IRQNONE) {
323         mapline++;
324         i++;
325     }
326     return i;
327 }
328 
329 /*
330  * Initialize board IRQs.
331  * These IRQs contain split Int/External Combiner and External Gic IRQs.
332  */
333 static void exynos4210_init_board_irqs(Exynos4210State *s)
334 {
335     uint32_t grp, bit, irq_id, n;
336     DeviceState *extgicdev = DEVICE(&s->ext_gic);
337     DeviceState *intcdev = DEVICE(&s->int_combiner);
338     DeviceState *extcdev = DEVICE(&s->ext_combiner);
339     int splitcount = 0;
340     DeviceState *splitter;
341     const int *mapline;
342     int numlines, splitin, in;
343 
344     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
345         irq_id = 0;
346         if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) {
347             /* MCT_G0 is passed to External GIC */
348             irq_id = EXT_GIC_ID_MCT_G0;
349         }
350         if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) {
351             /* MCT_G1 is passed to External and GIC */
352             irq_id = EXT_GIC_ID_MCT_G1;
353         }
354 
355         if (s->irq_table[n]) {
356             /*
357              * This must be some non-first entry in a combinermap line,
358              * and we've already filled it in.
359              */
360             continue;
361         }
362         mapline = combinermap_entry(n);
363         /*
364          * We need to connect the IRQ to multiple inputs on both combiners
365          * and possibly also to the external GIC.
366          */
367         numlines = 2 * mapline_size(mapline);
368         if (irq_id) {
369             numlines++;
370         }
371         assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
372         splitter = DEVICE(&s->splitter[splitcount]);
373         qdev_prop_set_uint16(splitter, "num-lines", numlines);
374         qdev_realize(splitter, NULL, &error_abort);
375         splitcount++;
376 
377         in = n;
378         splitin = 0;
379         for (;;) {
380             s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
381             qdev_connect_gpio_out(splitter, splitin,
382                                   qdev_get_gpio_in(intcdev, in));
383             qdev_connect_gpio_out(splitter, splitin + 1,
384                                   qdev_get_gpio_in(extcdev, in));
385             splitin += 2;
386             if (!mapline) {
387                 break;
388             }
389             mapline++;
390             in = *mapline;
391             if (in == IRQNONE) {
392                 break;
393             }
394         }
395         if (irq_id) {
396             qdev_connect_gpio_out(splitter, splitin,
397                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
398         }
399     }
400     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
401         /* these IDs are passed to Internal Combiner and External GIC */
402         grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
403         bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
404         irq_id = combiner_grp_to_gic_id[grp -
405                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
406 
407         if (s->irq_table[n]) {
408             /*
409              * This must be some non-first entry in a combinermap line,
410              * and we've already filled it in.
411              */
412             continue;
413         }
414 
415         if (irq_id) {
416             assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
417             splitter = DEVICE(&s->splitter[splitcount]);
418             qdev_prop_set_uint16(splitter, "num-lines", 2);
419             qdev_realize(splitter, NULL, &error_abort);
420             splitcount++;
421             s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
422             qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n));
423             qdev_connect_gpio_out(splitter, 1,
424                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
425         } else {
426             s->irq_table[n] = qdev_get_gpio_in(intcdev, n);
427         }
428     }
429     /*
430      * We check this here to avoid a more obscure assert later when
431      * qdev_assert_realized_properly() checks that we realized every
432      * child object we initialized.
433      */
434     assert(splitcount == EXYNOS4210_NUM_SPLITTERS);
435 }
436 
437 /*
438  * Get IRQ number from exynos4210 IRQ subsystem stub.
439  * To identify IRQ source use internal combiner group and bit number
440  *  grp - group number
441  *  bit - bit number inside group
442  */
443 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
444 {
445     return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
446 }
447 
448 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
449                                     0x09, 0x00, 0x00, 0x00 };
450 
451 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
452                                                unsigned size)
453 {
454     assert(offset < sizeof(chipid_and_omr));
455     return chipid_and_omr[offset];
456 }
457 
458 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
459                                             uint64_t value, unsigned size)
460 {
461     return;
462 }
463 
464 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
465     .read = exynos4210_chipid_and_omr_read,
466     .write = exynos4210_chipid_and_omr_write,
467     .endianness = DEVICE_NATIVE_ENDIAN,
468     .impl = {
469         .max_access_size = 1,
470     }
471 };
472 
473 void exynos4210_write_secondary(ARMCPU *cpu,
474         const struct arm_boot_info *info)
475 {
476     int n;
477     uint32_t smpboot[] = {
478         0xe59f3034, /* ldr r3, External gic_cpu_if */
479         0xe59f2034, /* ldr r2, Internal gic_cpu_if */
480         0xe59f0034, /* ldr r0, startaddr */
481         0xe3a01001, /* mov r1, #1 */
482         0xe5821000, /* str r1, [r2] */
483         0xe5831000, /* str r1, [r3] */
484         0xe3a010ff, /* mov r1, #0xff */
485         0xe5821004, /* str r1, [r2, #4] */
486         0xe5831004, /* str r1, [r3, #4] */
487         0xf57ff04f, /* dsb */
488         0xe320f003, /* wfi */
489         0xe5901000, /* ldr     r1, [r0] */
490         0xe1110001, /* tst     r1, r1 */
491         0x0afffffb, /* beq     <wfi> */
492         0xe12fff11, /* bx      r1 */
493         EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
494         0,          /* gic_cpu_if: base address of Internal GIC CPU interface */
495         0           /* bootreg: Boot register address is held here */
496     };
497     smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
498     smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
499     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
500         smpboot[n] = tswap32(smpboot[n]);
501     }
502     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
503                        info->smp_loader_start);
504 }
505 
506 static uint64_t exynos4210_calc_affinity(int cpu)
507 {
508     /* Exynos4210 has 0x9 as cluster ID */
509     return (0x9 << ARM_AFF1_SHIFT) | cpu;
510 }
511 
512 static DeviceState *pl330_create(uint32_t base, OrIRQState *orgate,
513                                  qemu_irq irq, int nreq, int nevents, int width)
514 {
515     SysBusDevice *busdev;
516     DeviceState *dev;
517     int i;
518 
519     dev = qdev_new("pl330");
520     object_property_set_link(OBJECT(dev), "memory",
521                              OBJECT(get_system_memory()),
522                              &error_fatal);
523     qdev_prop_set_uint8(dev, "num_events", nevents);
524     qdev_prop_set_uint8(dev, "num_chnls",  8);
525     qdev_prop_set_uint8(dev, "num_periph_req",  nreq);
526 
527     qdev_prop_set_uint8(dev, "wr_cap", 4);
528     qdev_prop_set_uint8(dev, "wr_q_dep", 8);
529     qdev_prop_set_uint8(dev, "rd_cap", 4);
530     qdev_prop_set_uint8(dev, "rd_q_dep", 8);
531     qdev_prop_set_uint8(dev, "data_width", width);
532     qdev_prop_set_uint16(dev, "data_buffer_dep", width);
533     busdev = SYS_BUS_DEVICE(dev);
534     sysbus_realize_and_unref(busdev, &error_fatal);
535     sysbus_mmio_map(busdev, 0, base);
536 
537     object_property_set_int(OBJECT(orgate), "num-lines", nevents + 1,
538                             &error_abort);
539     qdev_realize(DEVICE(orgate), NULL, &error_abort);
540 
541     for (i = 0; i < nevents + 1; i++) {
542         sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i));
543     }
544     qdev_connect_gpio_out(DEVICE(orgate), 0, irq);
545     return dev;
546 }
547 
548 static void exynos4210_realize(DeviceState *socdev, Error **errp)
549 {
550     Exynos4210State *s = EXYNOS4210_SOC(socdev);
551     MemoryRegion *system_mem = get_system_memory();
552     SysBusDevice *busdev;
553     DeviceState *dev, *uart[4], *pl330[3];
554     int i, n;
555 
556     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
557         Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9"));
558 
559         object_property_add_child(OBJECT(s), "cpu[*]", cpuobj);
560         /* By default A9 CPUs have EL3 enabled.  This board does not currently
561          * support EL3 so the CPU EL3 property is disabled before realization.
562          */
563         if (object_property_find(cpuobj, "has_el3")) {
564             object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
565         }
566 
567         s->cpu[n] = ARM_CPU(cpuobj);
568         object_property_set_int(cpuobj, "mp-affinity",
569                                 exynos4210_calc_affinity(n), &error_abort);
570         object_property_set_int(cpuobj, "reset-cbar",
571                                 EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
572                                 &error_abort);
573         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
574     }
575 
576     /* IRQ Gate */
577     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
578         DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
579         object_property_set_int(OBJECT(orgate), "num-lines",
580                                 EXYNOS4210_IRQ_GATE_NINPUTS,
581                                 &error_abort);
582         qdev_realize(orgate, NULL, &error_abort);
583         qdev_connect_gpio_out(orgate, 0,
584                               qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
585     }
586 
587     /* Private memory region and Internal GIC */
588     qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
589     busdev = SYS_BUS_DEVICE(&s->a9mpcore);
590     sysbus_realize(busdev, &error_fatal);
591     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
592     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
593         sysbus_connect_irq(busdev, n,
594                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
595     }
596 
597     /* Cache controller */
598     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
599 
600     /* External GIC */
601     qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS);
602     busdev = SYS_BUS_DEVICE(&s->ext_gic);
603     sysbus_realize(busdev, &error_fatal);
604     /* Map CPU interface */
605     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
606     /* Map Distributer interface */
607     sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
608     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
609         sysbus_connect_irq(busdev, n,
610                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
611     }
612 
613     /* Internal Interrupt Combiner */
614     busdev = SYS_BUS_DEVICE(&s->int_combiner);
615     sysbus_realize(busdev, &error_fatal);
616     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
617         sysbus_connect_irq(busdev, n,
618                            qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
619     }
620     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
621 
622     /* External Interrupt Combiner */
623     qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1);
624     busdev = SYS_BUS_DEVICE(&s->ext_combiner);
625     sysbus_realize(busdev, &error_fatal);
626     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
627         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
628     }
629     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
630 
631     /* Initialize board IRQs. */
632     exynos4210_init_board_irqs(s);
633 
634     /*** Memory ***/
635 
636     /* Chip-ID and OMR */
637     memory_region_init_io(&s->chipid_mem, OBJECT(socdev),
638                           &exynos4210_chipid_and_omr_ops, NULL,
639                           "exynos4210.chipid", sizeof(chipid_and_omr));
640     memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
641                                 &s->chipid_mem);
642 
643     /* Internal ROM */
644     memory_region_init_rom(&s->irom_mem, OBJECT(socdev), "exynos4210.irom",
645                            EXYNOS4210_IROM_SIZE, &error_fatal);
646     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
647                                 &s->irom_mem);
648     /* mirror of iROM */
649     memory_region_init_alias(&s->irom_alias_mem, OBJECT(socdev),
650                              "exynos4210.irom_alias", &s->irom_mem, 0,
651                              EXYNOS4210_IROM_SIZE);
652     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
653                                 &s->irom_alias_mem);
654 
655     /* Internal RAM */
656     memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
657                            EXYNOS4210_IRAM_SIZE, &error_fatal);
658     memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
659                                 &s->iram_mem);
660 
661    /* PMU.
662     * The only reason of existence at the moment is that secondary CPU boot
663     * loader uses PMU INFORM5 register as a holding pen.
664     */
665     sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
666 
667     sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
668     sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL);
669 
670     /* PWM */
671     sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
672                           s->irq_table[exynos4210_get_irq(22, 0)],
673                           s->irq_table[exynos4210_get_irq(22, 1)],
674                           s->irq_table[exynos4210_get_irq(22, 2)],
675                           s->irq_table[exynos4210_get_irq(22, 3)],
676                           s->irq_table[exynos4210_get_irq(22, 4)],
677                           NULL);
678     /* RTC */
679     sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
680                           s->irq_table[exynos4210_get_irq(23, 0)],
681                           s->irq_table[exynos4210_get_irq(23, 1)],
682                           NULL);
683 
684     /* Multi Core Timer */
685     dev = qdev_new("exynos4210.mct");
686     busdev = SYS_BUS_DEVICE(dev);
687     sysbus_realize_and_unref(busdev, &error_fatal);
688     for (n = 0; n < 4; n++) {
689         /* Connect global timer interrupts to Combiner gpio_in */
690         sysbus_connect_irq(busdev, n,
691                 s->irq_table[exynos4210_get_irq(1, 4 + n)]);
692     }
693     /* Connect local timer interrupts to Combiner gpio_in */
694     sysbus_connect_irq(busdev, 4,
695             s->irq_table[exynos4210_get_irq(51, 0)]);
696     sysbus_connect_irq(busdev, 5,
697             s->irq_table[exynos4210_get_irq(35, 3)]);
698     sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
699 
700     /*** I2C ***/
701     for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
702         uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
703         qemu_irq i2c_irq;
704 
705         if (n < 8) {
706             i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
707         } else {
708             i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
709         }
710 
711         dev = qdev_new("exynos4210.i2c");
712         busdev = SYS_BUS_DEVICE(dev);
713         sysbus_realize_and_unref(busdev, &error_fatal);
714         sysbus_connect_irq(busdev, 0, i2c_irq);
715         sysbus_mmio_map(busdev, 0, addr);
716         s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
717     }
718 
719 
720     /*** UARTs ***/
721     uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
722                            EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0),
723                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
724 
725     uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
726                            EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1),
727                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
728 
729     uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
730                            EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2),
731                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
732 
733     uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
734                            EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3),
735                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
736 
737     /*** SD/MMC host controllers ***/
738     for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) {
739         DeviceState *carddev;
740         BlockBackend *blk;
741         DriveInfo *di;
742 
743         /* Compatible with:
744          * - SD Host Controller Specification Version 2.0
745          * - SDIO Specification Version 2.0
746          * - MMC Specification Version 4.3
747          * - SDMA
748          * - ADMA2
749          *
750          * As this part of the Exynos4210 is not publicly available,
751          * we used the "HS-MMC Controller S3C2416X RISC Microprocessor"
752          * public datasheet which is very similar (implementing
753          * MMC Specification Version 4.0 being the only difference noted)
754          */
755         dev = qdev_new(TYPE_S3C_SDHCI);
756         qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
757 
758         busdev = SYS_BUS_DEVICE(dev);
759         sysbus_realize_and_unref(busdev, &error_fatal);
760         sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n));
761         sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]);
762 
763         di = drive_get(IF_SD, 0, n);
764         blk = di ? blk_by_legacy_dinfo(di) : NULL;
765         carddev = qdev_new(TYPE_SD_CARD);
766         qdev_prop_set_drive(carddev, "drive", blk);
767         qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
768                                &error_fatal);
769     }
770 
771     /*** Display controller (FIMD) ***/
772     dev = qdev_new("exynos4210.fimd");
773     object_property_set_link(OBJECT(dev), "framebuffer-memory",
774                              OBJECT(system_mem), &error_fatal);
775     busdev = SYS_BUS_DEVICE(dev);
776     sysbus_realize_and_unref(busdev, &error_fatal);
777     sysbus_mmio_map(busdev, 0, EXYNOS4210_FIMD0_BASE_ADDR);
778     for (n = 0; n < 3; n++) {
779         sysbus_connect_irq(busdev, n, s->irq_table[exynos4210_get_irq(11, n)]);
780     }
781 
782     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
783             s->irq_table[exynos4210_get_irq(28, 3)]);
784 
785     /*** DMA controllers ***/
786     pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
787                             &s->pl330_irq_orgate[0],
788                             s->irq_table[exynos4210_get_irq(21, 0)],
789                             32, 32, 32);
790     pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
791                             &s->pl330_irq_orgate[1],
792                             s->irq_table[exynos4210_get_irq(21, 1)],
793                             32, 32, 32);
794     pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
795                             &s->pl330_irq_orgate[2],
796                             s->irq_table[exynos4210_get_irq(20, 1)],
797                             1, 31, 64);
798 
799     sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1,
800                        qdev_get_gpio_in(pl330[0], 15));
801     sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1,
802                        qdev_get_gpio_in(pl330[1], 15));
803     sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1,
804                        qdev_get_gpio_in(pl330[0], 17));
805     sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1,
806                        qdev_get_gpio_in(pl330[1], 17));
807 }
808 
809 static void exynos4210_init(Object *obj)
810 {
811     Exynos4210State *s = EXYNOS4210_SOC(obj);
812     int i;
813 
814     for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) {
815         char *name = g_strdup_printf("pl330-irq-orgate%d", i);
816         OrIRQState *orgate = &s->pl330_irq_orgate[i];
817 
818         object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
819         g_free(name);
820     }
821 
822     for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) {
823         g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
824         object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
825     }
826 
827     for (i = 0; i < ARRAY_SIZE(s->splitter); i++) {
828         g_autofree char *name = g_strdup_printf("irq-splitter%d", i);
829         object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ);
830     }
831 
832     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
833     object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
834     object_initialize_child(obj, "int-combiner", &s->int_combiner,
835                             TYPE_EXYNOS4210_COMBINER);
836     object_initialize_child(obj, "ext-combiner", &s->ext_combiner,
837                             TYPE_EXYNOS4210_COMBINER);
838 }
839 
840 static void exynos4210_class_init(ObjectClass *klass, void *data)
841 {
842     DeviceClass *dc = DEVICE_CLASS(klass);
843 
844     dc->realize = exynos4210_realize;
845 }
846 
847 static const TypeInfo exynos4210_info = {
848     .name = TYPE_EXYNOS4210_SOC,
849     .parent = TYPE_SYS_BUS_DEVICE,
850     .instance_size = sizeof(Exynos4210State),
851     .instance_init = exynos4210_init,
852     .class_init = exynos4210_class_init,
853 };
854 
855 static void exynos4210_register_types(void)
856 {
857     type_register_static(&exynos4210_info);
858 }
859 
860 type_init(exynos4210_register_types)
861