1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "exec/tswap.h" 27 #include "cpu.h" 28 #include "hw/cpu/a9mpcore.h" 29 #include "hw/irq.h" 30 #include "sysemu/blockdev.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/sysbus.h" 33 #include "hw/arm/boot.h" 34 #include "hw/loader.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/arm/exynos4210.h" 37 #include "hw/sd/sdhci.h" 38 #include "hw/usb/hcd-ehci.h" 39 40 #define EXYNOS4210_CHIPID_ADDR 0x10000000 41 42 /* PWM */ 43 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 44 45 /* RTC */ 46 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 47 48 /* MCT */ 49 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 50 51 /* I2C */ 52 #define EXYNOS4210_I2C_SHIFT 0x00010000 53 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 54 /* Interrupt Group of External Interrupt Combiner for I2C */ 55 #define EXYNOS4210_I2C_INTG 27 56 #define EXYNOS4210_HDMI_INTG 16 57 58 /* UART's definitions */ 59 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 60 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 61 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 62 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 63 #define EXYNOS4210_UART0_FIFO_SIZE 256 64 #define EXYNOS4210_UART1_FIFO_SIZE 64 65 #define EXYNOS4210_UART2_FIFO_SIZE 16 66 #define EXYNOS4210_UART3_FIFO_SIZE 16 67 /* Interrupt Group of External Interrupt Combiner for UART */ 68 #define EXYNOS4210_UART_INT_GRP 26 69 70 /* External GIC */ 71 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 72 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 73 74 /* Combiner */ 75 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 76 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 77 78 /* SD/MMC host controllers */ 79 #define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 80 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 81 #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ 82 0x00010000 * (n)) 83 #define EXYNOS4210_SDHCI_NUMBER 4 84 85 /* PMU SFR base address */ 86 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 87 88 /* Clock controller SFR base address */ 89 #define EXYNOS4210_CLK_BASE_ADDR 0x10030000 90 91 /* PRNG/HASH SFR base address */ 92 #define EXYNOS4210_RNG_BASE_ADDR 0x10830400 93 94 /* Display controllers (FIMD) */ 95 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 96 97 /* EHCI */ 98 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 99 100 /* DMA */ 101 #define EXYNOS4210_PL330_BASE0_ADDR 0x12680000 102 #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 103 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 104 105 enum ExtGicId { 106 EXT_GIC_ID_MDMA_LCD0 = 66, 107 EXT_GIC_ID_PDMA0, 108 EXT_GIC_ID_PDMA1, 109 EXT_GIC_ID_TIMER0, 110 EXT_GIC_ID_TIMER1, 111 EXT_GIC_ID_TIMER2, 112 EXT_GIC_ID_TIMER3, 113 EXT_GIC_ID_TIMER4, 114 EXT_GIC_ID_MCT_L0, 115 EXT_GIC_ID_WDT, 116 EXT_GIC_ID_RTC_ALARM, 117 EXT_GIC_ID_RTC_TIC, 118 EXT_GIC_ID_GPIO_XB, 119 EXT_GIC_ID_GPIO_XA, 120 EXT_GIC_ID_MCT_L1, 121 EXT_GIC_ID_IEM_APC, 122 EXT_GIC_ID_IEM_IEC, 123 EXT_GIC_ID_NFC, 124 EXT_GIC_ID_UART0, 125 EXT_GIC_ID_UART1, 126 EXT_GIC_ID_UART2, 127 EXT_GIC_ID_UART3, 128 EXT_GIC_ID_UART4, 129 EXT_GIC_ID_MCT_G0, 130 EXT_GIC_ID_I2C0, 131 EXT_GIC_ID_I2C1, 132 EXT_GIC_ID_I2C2, 133 EXT_GIC_ID_I2C3, 134 EXT_GIC_ID_I2C4, 135 EXT_GIC_ID_I2C5, 136 EXT_GIC_ID_I2C6, 137 EXT_GIC_ID_I2C7, 138 EXT_GIC_ID_SPI0, 139 EXT_GIC_ID_SPI1, 140 EXT_GIC_ID_SPI2, 141 EXT_GIC_ID_MCT_G1, 142 EXT_GIC_ID_USB_HOST, 143 EXT_GIC_ID_USB_DEVICE, 144 EXT_GIC_ID_MODEMIF, 145 EXT_GIC_ID_HSMMC0, 146 EXT_GIC_ID_HSMMC1, 147 EXT_GIC_ID_HSMMC2, 148 EXT_GIC_ID_HSMMC3, 149 EXT_GIC_ID_SDMMC, 150 EXT_GIC_ID_MIPI_CSI_4LANE, 151 EXT_GIC_ID_MIPI_DSI_4LANE, 152 EXT_GIC_ID_MIPI_CSI_2LANE, 153 EXT_GIC_ID_MIPI_DSI_2LANE, 154 EXT_GIC_ID_ONENAND_AUDI, 155 EXT_GIC_ID_ROTATOR, 156 EXT_GIC_ID_FIMC0, 157 EXT_GIC_ID_FIMC1, 158 EXT_GIC_ID_FIMC2, 159 EXT_GIC_ID_FIMC3, 160 EXT_GIC_ID_JPEG, 161 EXT_GIC_ID_2D, 162 EXT_GIC_ID_PCIe, 163 EXT_GIC_ID_MIXER, 164 EXT_GIC_ID_HDMI, 165 EXT_GIC_ID_HDMI_I2C, 166 EXT_GIC_ID_MFC, 167 EXT_GIC_ID_TVENC, 168 }; 169 170 enum ExtInt { 171 EXT_GIC_ID_EXTINT0 = 48, 172 EXT_GIC_ID_EXTINT1, 173 EXT_GIC_ID_EXTINT2, 174 EXT_GIC_ID_EXTINT3, 175 EXT_GIC_ID_EXTINT4, 176 EXT_GIC_ID_EXTINT5, 177 EXT_GIC_ID_EXTINT6, 178 EXT_GIC_ID_EXTINT7, 179 EXT_GIC_ID_EXTINT8, 180 EXT_GIC_ID_EXTINT9, 181 EXT_GIC_ID_EXTINT10, 182 EXT_GIC_ID_EXTINT11, 183 EXT_GIC_ID_EXTINT12, 184 EXT_GIC_ID_EXTINT13, 185 EXT_GIC_ID_EXTINT14, 186 EXT_GIC_ID_EXTINT15 187 }; 188 189 /* 190 * External GIC sources which are not from External Interrupt Combiner or 191 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, 192 * which is INTG16 in Internal Interrupt Combiner. 193 */ 194 195 static const uint32_t 196 combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { 197 /* int combiner groups 16-19 */ 198 { }, { }, { }, { }, 199 /* int combiner group 20 */ 200 { 0, EXT_GIC_ID_MDMA_LCD0 }, 201 /* int combiner group 21 */ 202 { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, 203 /* int combiner group 22 */ 204 { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, 205 EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, 206 /* int combiner group 23 */ 207 { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, 208 /* int combiner group 24 */ 209 { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, 210 /* int combiner group 25 */ 211 { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, 212 /* int combiner group 26 */ 213 { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, 214 EXT_GIC_ID_UART4 }, 215 /* int combiner group 27 */ 216 { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, 217 EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, 218 EXT_GIC_ID_I2C7 }, 219 /* int combiner group 28 */ 220 { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, 221 /* int combiner group 29 */ 222 { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, 223 EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, 224 /* int combiner group 30 */ 225 { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, 226 /* int combiner group 31 */ 227 { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, 228 /* int combiner group 32 */ 229 { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, 230 /* int combiner group 33 */ 231 { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, 232 /* int combiner group 34 */ 233 { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, 234 /* int combiner group 35 */ 235 { 0, 0, 0, EXT_GIC_ID_MCT_L1 }, 236 /* int combiner group 36 */ 237 { EXT_GIC_ID_MIXER }, 238 /* int combiner group 37 */ 239 { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, 240 EXT_GIC_ID_EXTINT7 }, 241 /* groups 38-50 */ 242 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, 243 /* int combiner group 51 */ 244 { EXT_GIC_ID_MCT_L0 }, 245 /* group 52 */ 246 { }, 247 /* int combiner group 53 */ 248 { EXT_GIC_ID_WDT }, 249 /* groups 54-63 */ 250 { }, { }, { }, { }, { }, { }, { }, { }, { }, { } 251 }; 252 253 #define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit)) 254 #define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) 255 #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ 256 ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) 257 258 /* 259 * Some interrupt lines go to multiple combiner inputs. 260 * This data structure defines those: each array element is 261 * a list of combiner inputs which are connected together; 262 * the one with the smallest interrupt ID value must be first. 263 * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being 264 * wired to anything so we can use 0 as a terminator. 265 */ 266 #define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B) 267 #define IRQNONE 0 268 269 #define COMBINERMAP_SIZE 16 270 271 static const int combinermap[COMBINERMAP_SIZE][6] = { 272 /* MDNIE_LCD1 */ 273 { IRQNO(0, 4), IRQNO(1, 0), IRQNONE }, 274 { IRQNO(0, 5), IRQNO(1, 1), IRQNONE }, 275 { IRQNO(0, 6), IRQNO(1, 2), IRQNONE }, 276 { IRQNO(0, 7), IRQNO(1, 3), IRQNONE }, 277 /* TMU */ 278 { IRQNO(2, 4), IRQNO(3, 4), IRQNONE }, 279 { IRQNO(2, 5), IRQNO(3, 5), IRQNONE }, 280 { IRQNO(2, 6), IRQNO(3, 6), IRQNONE }, 281 { IRQNO(2, 7), IRQNO(3, 7), IRQNONE }, 282 /* LCD1 */ 283 { IRQNO(11, 4), IRQNO(12, 0), IRQNONE }, 284 { IRQNO(11, 5), IRQNO(12, 1), IRQNONE }, 285 { IRQNO(11, 6), IRQNO(12, 2), IRQNONE }, 286 { IRQNO(11, 7), IRQNO(12, 3), IRQNONE }, 287 /* Multi-core timer */ 288 { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE }, 289 { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE }, 290 { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE }, 291 { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE }, 292 }; 293 294 #undef IRQNO 295 296 static const int *combinermap_entry(int irq) 297 { 298 /* 299 * If the interrupt number passed in is the first entry in some 300 * line of the combinermap, return a pointer to that line; 301 * otherwise return NULL. 302 */ 303 int i; 304 for (i = 0; i < COMBINERMAP_SIZE; i++) { 305 if (combinermap[i][0] == irq) { 306 return combinermap[i]; 307 } 308 } 309 return NULL; 310 } 311 312 static int mapline_size(const int *mapline) 313 { 314 /* Return number of entries in this mapline in total */ 315 int i = 0; 316 317 if (!mapline) { 318 /* Not in the map? IRQ goes to exactly one combiner input */ 319 return 1; 320 } 321 while (*mapline != IRQNONE) { 322 mapline++; 323 i++; 324 } 325 return i; 326 } 327 328 /* 329 * Initialize board IRQs. 330 * These IRQs contain split Int/External Combiner and External Gic IRQs. 331 */ 332 static void exynos4210_init_board_irqs(Exynos4210State *s) 333 { 334 uint32_t grp, bit, irq_id, n; 335 DeviceState *extgicdev = DEVICE(&s->ext_gic); 336 DeviceState *intcdev = DEVICE(&s->int_combiner); 337 DeviceState *extcdev = DEVICE(&s->ext_combiner); 338 int splitcount = 0; 339 DeviceState *splitter; 340 const int *mapline; 341 int numlines, splitin, in; 342 343 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { 344 irq_id = 0; 345 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) { 346 /* MCT_G0 is passed to External GIC */ 347 irq_id = EXT_GIC_ID_MCT_G0; 348 } 349 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) { 350 /* MCT_G1 is passed to External and GIC */ 351 irq_id = EXT_GIC_ID_MCT_G1; 352 } 353 354 if (s->irq_table[n]) { 355 /* 356 * This must be some non-first entry in a combinermap line, 357 * and we've already filled it in. 358 */ 359 continue; 360 } 361 mapline = combinermap_entry(n); 362 /* 363 * We need to connect the IRQ to multiple inputs on both combiners 364 * and possibly also to the external GIC. 365 */ 366 numlines = 2 * mapline_size(mapline); 367 if (irq_id) { 368 numlines++; 369 } 370 assert(splitcount < EXYNOS4210_NUM_SPLITTERS); 371 splitter = DEVICE(&s->splitter[splitcount]); 372 qdev_prop_set_uint16(splitter, "num-lines", numlines); 373 qdev_realize(splitter, NULL, &error_abort); 374 splitcount++; 375 376 in = n; 377 splitin = 0; 378 for (;;) { 379 s->irq_table[in] = qdev_get_gpio_in(splitter, 0); 380 qdev_connect_gpio_out(splitter, splitin, 381 qdev_get_gpio_in(intcdev, in)); 382 qdev_connect_gpio_out(splitter, splitin + 1, 383 qdev_get_gpio_in(extcdev, in)); 384 splitin += 2; 385 if (!mapline) { 386 break; 387 } 388 mapline++; 389 in = *mapline; 390 if (in == IRQNONE) { 391 break; 392 } 393 } 394 if (irq_id) { 395 qdev_connect_gpio_out(splitter, splitin, 396 qdev_get_gpio_in(extgicdev, irq_id - 32)); 397 } 398 } 399 for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { 400 /* these IDs are passed to Internal Combiner and External GIC */ 401 grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); 402 bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); 403 irq_id = combiner_grp_to_gic_id[grp - 404 EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; 405 406 if (s->irq_table[n]) { 407 /* 408 * This must be some non-first entry in a combinermap line, 409 * and we've already filled it in. 410 */ 411 continue; 412 } 413 414 if (irq_id) { 415 assert(splitcount < EXYNOS4210_NUM_SPLITTERS); 416 splitter = DEVICE(&s->splitter[splitcount]); 417 qdev_prop_set_uint16(splitter, "num-lines", 2); 418 qdev_realize(splitter, NULL, &error_abort); 419 splitcount++; 420 s->irq_table[n] = qdev_get_gpio_in(splitter, 0); 421 qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n)); 422 qdev_connect_gpio_out(splitter, 1, 423 qdev_get_gpio_in(extgicdev, irq_id - 32)); 424 } else { 425 s->irq_table[n] = qdev_get_gpio_in(intcdev, n); 426 } 427 } 428 /* 429 * We check this here to avoid a more obscure assert later when 430 * qdev_assert_realized_properly() checks that we realized every 431 * child object we initialized. 432 */ 433 assert(splitcount == EXYNOS4210_NUM_SPLITTERS); 434 } 435 436 /* 437 * Get IRQ number from exynos4210 IRQ subsystem stub. 438 * To identify IRQ source use internal combiner group and bit number 439 * grp - group number 440 * bit - bit number inside group 441 */ 442 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) 443 { 444 return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); 445 } 446 447 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 448 0x09, 0x00, 0x00, 0x00 }; 449 450 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 451 unsigned size) 452 { 453 assert(offset < sizeof(chipid_and_omr)); 454 return chipid_and_omr[offset]; 455 } 456 457 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 458 uint64_t value, unsigned size) 459 { 460 return; 461 } 462 463 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 464 .read = exynos4210_chipid_and_omr_read, 465 .write = exynos4210_chipid_and_omr_write, 466 .endianness = DEVICE_NATIVE_ENDIAN, 467 .impl = { 468 .max_access_size = 1, 469 } 470 }; 471 472 void exynos4210_write_secondary(ARMCPU *cpu, 473 const struct arm_boot_info *info) 474 { 475 int n; 476 uint32_t smpboot[] = { 477 0xe59f3034, /* ldr r3, External gic_cpu_if */ 478 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 479 0xe59f0034, /* ldr r0, startaddr */ 480 0xe3a01001, /* mov r1, #1 */ 481 0xe5821000, /* str r1, [r2] */ 482 0xe5831000, /* str r1, [r3] */ 483 0xe3a010ff, /* mov r1, #0xff */ 484 0xe5821004, /* str r1, [r2, #4] */ 485 0xe5831004, /* str r1, [r3, #4] */ 486 0xf57ff04f, /* dsb */ 487 0xe320f003, /* wfi */ 488 0xe5901000, /* ldr r1, [r0] */ 489 0xe1110001, /* tst r1, r1 */ 490 0x0afffffb, /* beq <wfi> */ 491 0xe12fff11, /* bx r1 */ 492 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 493 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 494 0 /* bootreg: Boot register address is held here */ 495 }; 496 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 497 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 498 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 499 smpboot[n] = tswap32(smpboot[n]); 500 } 501 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 502 info->smp_loader_start); 503 } 504 505 static uint64_t exynos4210_calc_affinity(int cpu) 506 { 507 /* Exynos4210 has 0x9 as cluster ID */ 508 return (0x9 << ARM_AFF1_SHIFT) | cpu; 509 } 510 511 static DeviceState *pl330_create(uint32_t base, OrIRQState *orgate, 512 qemu_irq irq, int nreq, int nevents, int width) 513 { 514 SysBusDevice *busdev; 515 DeviceState *dev; 516 int i; 517 518 dev = qdev_new("pl330"); 519 object_property_set_link(OBJECT(dev), "memory", 520 OBJECT(get_system_memory()), 521 &error_fatal); 522 qdev_prop_set_uint8(dev, "num_events", nevents); 523 qdev_prop_set_uint8(dev, "num_chnls", 8); 524 qdev_prop_set_uint8(dev, "num_periph_req", nreq); 525 526 qdev_prop_set_uint8(dev, "wr_cap", 4); 527 qdev_prop_set_uint8(dev, "wr_q_dep", 8); 528 qdev_prop_set_uint8(dev, "rd_cap", 4); 529 qdev_prop_set_uint8(dev, "rd_q_dep", 8); 530 qdev_prop_set_uint8(dev, "data_width", width); 531 qdev_prop_set_uint16(dev, "data_buffer_dep", width); 532 busdev = SYS_BUS_DEVICE(dev); 533 sysbus_realize_and_unref(busdev, &error_fatal); 534 sysbus_mmio_map(busdev, 0, base); 535 536 object_property_set_int(OBJECT(orgate), "num-lines", nevents + 1, 537 &error_abort); 538 qdev_realize(DEVICE(orgate), NULL, &error_abort); 539 540 for (i = 0; i < nevents + 1; i++) { 541 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i)); 542 } 543 qdev_connect_gpio_out(DEVICE(orgate), 0, irq); 544 return dev; 545 } 546 547 static void exynos4210_realize(DeviceState *socdev, Error **errp) 548 { 549 Exynos4210State *s = EXYNOS4210_SOC(socdev); 550 MemoryRegion *system_mem = get_system_memory(); 551 SysBusDevice *busdev; 552 DeviceState *dev, *uart[4], *pl330[3]; 553 int i, n; 554 555 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 556 Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); 557 558 /* By default A9 CPUs have EL3 enabled. This board does not currently 559 * support EL3 so the CPU EL3 property is disabled before realization. 560 */ 561 if (object_property_find(cpuobj, "has_el3")) { 562 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 563 } 564 565 s->cpu[n] = ARM_CPU(cpuobj); 566 object_property_set_int(cpuobj, "mp-affinity", 567 exynos4210_calc_affinity(n), &error_abort); 568 object_property_set_int(cpuobj, "reset-cbar", 569 EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 570 &error_abort); 571 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 572 } 573 574 /* IRQ Gate */ 575 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 576 DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); 577 object_property_set_int(OBJECT(orgate), "num-lines", 578 EXYNOS4210_IRQ_GATE_NINPUTS, 579 &error_abort); 580 qdev_realize(orgate, NULL, &error_abort); 581 qdev_connect_gpio_out(orgate, 0, 582 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 583 } 584 585 /* Private memory region and Internal GIC */ 586 qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); 587 busdev = SYS_BUS_DEVICE(&s->a9mpcore); 588 sysbus_realize(busdev, &error_fatal); 589 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 590 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 591 sysbus_connect_irq(busdev, n, 592 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); 593 } 594 595 /* Cache controller */ 596 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 597 598 /* External GIC */ 599 qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS); 600 busdev = SYS_BUS_DEVICE(&s->ext_gic); 601 sysbus_realize(busdev, &error_fatal); 602 /* Map CPU interface */ 603 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 604 /* Map Distributer interface */ 605 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 606 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 607 sysbus_connect_irq(busdev, n, 608 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); 609 } 610 611 /* Internal Interrupt Combiner */ 612 busdev = SYS_BUS_DEVICE(&s->int_combiner); 613 sysbus_realize(busdev, &error_fatal); 614 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 615 sysbus_connect_irq(busdev, n, 616 qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); 617 } 618 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 619 620 /* External Interrupt Combiner */ 621 qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1); 622 busdev = SYS_BUS_DEVICE(&s->ext_combiner); 623 sysbus_realize(busdev, &error_fatal); 624 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 625 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); 626 } 627 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 628 629 /* Initialize board IRQs. */ 630 exynos4210_init_board_irqs(s); 631 632 /*** Memory ***/ 633 634 /* Chip-ID and OMR */ 635 memory_region_init_io(&s->chipid_mem, OBJECT(socdev), 636 &exynos4210_chipid_and_omr_ops, NULL, 637 "exynos4210.chipid", sizeof(chipid_and_omr)); 638 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 639 &s->chipid_mem); 640 641 /* Internal ROM */ 642 memory_region_init_rom(&s->irom_mem, OBJECT(socdev), "exynos4210.irom", 643 EXYNOS4210_IROM_SIZE, &error_fatal); 644 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 645 &s->irom_mem); 646 /* mirror of iROM */ 647 memory_region_init_alias(&s->irom_alias_mem, OBJECT(socdev), 648 "exynos4210.irom_alias", &s->irom_mem, 0, 649 EXYNOS4210_IROM_SIZE); 650 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 651 &s->irom_alias_mem); 652 653 /* Internal RAM */ 654 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 655 EXYNOS4210_IRAM_SIZE, &error_fatal); 656 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 657 &s->iram_mem); 658 659 /* PMU. 660 * The only reason of existence at the moment is that secondary CPU boot 661 * loader uses PMU INFORM5 register as a holding pen. 662 */ 663 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 664 665 sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL); 666 sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL); 667 668 /* PWM */ 669 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 670 s->irq_table[exynos4210_get_irq(22, 0)], 671 s->irq_table[exynos4210_get_irq(22, 1)], 672 s->irq_table[exynos4210_get_irq(22, 2)], 673 s->irq_table[exynos4210_get_irq(22, 3)], 674 s->irq_table[exynos4210_get_irq(22, 4)], 675 NULL); 676 /* RTC */ 677 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 678 s->irq_table[exynos4210_get_irq(23, 0)], 679 s->irq_table[exynos4210_get_irq(23, 1)], 680 NULL); 681 682 /* Multi Core Timer */ 683 dev = qdev_new("exynos4210.mct"); 684 busdev = SYS_BUS_DEVICE(dev); 685 sysbus_realize_and_unref(busdev, &error_fatal); 686 for (n = 0; n < 4; n++) { 687 /* Connect global timer interrupts to Combiner gpio_in */ 688 sysbus_connect_irq(busdev, n, 689 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 690 } 691 /* Connect local timer interrupts to Combiner gpio_in */ 692 sysbus_connect_irq(busdev, 4, 693 s->irq_table[exynos4210_get_irq(51, 0)]); 694 sysbus_connect_irq(busdev, 5, 695 s->irq_table[exynos4210_get_irq(35, 3)]); 696 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 697 698 /*** I2C ***/ 699 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 700 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 701 qemu_irq i2c_irq; 702 703 if (n < 8) { 704 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 705 } else { 706 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 707 } 708 709 dev = qdev_new("exynos4210.i2c"); 710 busdev = SYS_BUS_DEVICE(dev); 711 sysbus_realize_and_unref(busdev, &error_fatal); 712 sysbus_connect_irq(busdev, 0, i2c_irq); 713 sysbus_mmio_map(busdev, 0, addr); 714 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 715 } 716 717 718 /*** UARTs ***/ 719 uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 720 EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0), 721 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 722 723 uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 724 EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1), 725 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 726 727 uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 728 EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2), 729 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 730 731 uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 732 EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3), 733 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 734 735 /*** SD/MMC host controllers ***/ 736 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { 737 DeviceState *carddev; 738 BlockBackend *blk; 739 DriveInfo *di; 740 741 /* Compatible with: 742 * - SD Host Controller Specification Version 2.0 743 * - SDIO Specification Version 2.0 744 * - MMC Specification Version 4.3 745 * - SDMA 746 * - ADMA2 747 * 748 * As this part of the Exynos4210 is not publicly available, 749 * we used the "HS-MMC Controller S3C2416X RISC Microprocessor" 750 * public datasheet which is very similar (implementing 751 * MMC Specification Version 4.0 being the only difference noted) 752 */ 753 dev = qdev_new(TYPE_S3C_SDHCI); 754 qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); 755 756 busdev = SYS_BUS_DEVICE(dev); 757 sysbus_realize_and_unref(busdev, &error_fatal); 758 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); 759 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); 760 761 di = drive_get(IF_SD, 0, n); 762 blk = di ? blk_by_legacy_dinfo(di) : NULL; 763 carddev = qdev_new(TYPE_SD_CARD); 764 qdev_prop_set_drive(carddev, "drive", blk); 765 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), 766 &error_fatal); 767 } 768 769 /*** Display controller (FIMD) ***/ 770 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 771 s->irq_table[exynos4210_get_irq(11, 0)], 772 s->irq_table[exynos4210_get_irq(11, 1)], 773 s->irq_table[exynos4210_get_irq(11, 2)], 774 NULL); 775 776 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 777 s->irq_table[exynos4210_get_irq(28, 3)]); 778 779 /*** DMA controllers ***/ 780 pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR, 781 &s->pl330_irq_orgate[0], 782 s->irq_table[exynos4210_get_irq(21, 0)], 783 32, 32, 32); 784 pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR, 785 &s->pl330_irq_orgate[1], 786 s->irq_table[exynos4210_get_irq(21, 1)], 787 32, 32, 32); 788 pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR, 789 &s->pl330_irq_orgate[2], 790 s->irq_table[exynos4210_get_irq(20, 1)], 791 1, 31, 64); 792 793 sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1, 794 qdev_get_gpio_in(pl330[0], 15)); 795 sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1, 796 qdev_get_gpio_in(pl330[1], 15)); 797 sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1, 798 qdev_get_gpio_in(pl330[0], 17)); 799 sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1, 800 qdev_get_gpio_in(pl330[1], 17)); 801 } 802 803 static void exynos4210_init(Object *obj) 804 { 805 Exynos4210State *s = EXYNOS4210_SOC(obj); 806 int i; 807 808 for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { 809 char *name = g_strdup_printf("pl330-irq-orgate%d", i); 810 OrIRQState *orgate = &s->pl330_irq_orgate[i]; 811 812 object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); 813 g_free(name); 814 } 815 816 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { 817 g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); 818 object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); 819 } 820 821 for (i = 0; i < ARRAY_SIZE(s->splitter); i++) { 822 g_autofree char *name = g_strdup_printf("irq-splitter%d", i); 823 object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ); 824 } 825 826 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 827 object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); 828 object_initialize_child(obj, "int-combiner", &s->int_combiner, 829 TYPE_EXYNOS4210_COMBINER); 830 object_initialize_child(obj, "ext-combiner", &s->ext_combiner, 831 TYPE_EXYNOS4210_COMBINER); 832 } 833 834 static void exynos4210_class_init(ObjectClass *klass, void *data) 835 { 836 DeviceClass *dc = DEVICE_CLASS(klass); 837 838 dc->realize = exynos4210_realize; 839 } 840 841 static const TypeInfo exynos4210_info = { 842 .name = TYPE_EXYNOS4210_SOC, 843 .parent = TYPE_SYS_BUS_DEVICE, 844 .instance_size = sizeof(Exynos4210State), 845 .instance_init = exynos4210_init, 846 .class_init = exynos4210_class_init, 847 }; 848 849 static void exynos4210_register_types(void) 850 { 851 type_register_static(&exynos4210_info); 852 } 853 854 type_init(exynos4210_register_types) 855