1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "qemu/log.h" 28 #include "cpu.h" 29 #include "hw/cpu/a9mpcore.h" 30 #include "hw/boards.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/sysbus.h" 33 #include "hw/arm/arm.h" 34 #include "hw/loader.h" 35 #include "hw/arm/exynos4210.h" 36 #include "hw/sd/sd.h" 37 #include "hw/usb/hcd-ehci.h" 38 39 #define EXYNOS4210_CHIPID_ADDR 0x10000000 40 41 /* PWM */ 42 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 43 44 /* RTC */ 45 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 46 47 /* MCT */ 48 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 49 50 /* I2C */ 51 #define EXYNOS4210_I2C_SHIFT 0x00010000 52 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 53 /* Interrupt Group of External Interrupt Combiner for I2C */ 54 #define EXYNOS4210_I2C_INTG 27 55 #define EXYNOS4210_HDMI_INTG 16 56 57 /* UART's definitions */ 58 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 59 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 60 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 61 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 62 #define EXYNOS4210_UART0_FIFO_SIZE 256 63 #define EXYNOS4210_UART1_FIFO_SIZE 64 64 #define EXYNOS4210_UART2_FIFO_SIZE 16 65 #define EXYNOS4210_UART3_FIFO_SIZE 16 66 /* Interrupt Group of External Interrupt Combiner for UART */ 67 #define EXYNOS4210_UART_INT_GRP 26 68 69 /* External GIC */ 70 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 71 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 72 73 /* Combiner */ 74 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 75 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 76 77 /* SD/MMC host controllers */ 78 #define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 79 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 80 #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ 81 0x00010000 * (n)) 82 #define EXYNOS4210_SDHCI_NUMBER 4 83 84 /* PMU SFR base address */ 85 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 86 87 /* Clock controller SFR base address */ 88 #define EXYNOS4210_CLK_BASE_ADDR 0x10030000 89 90 /* Display controllers (FIMD) */ 91 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 92 93 /* EHCI */ 94 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 95 96 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 97 0x09, 0x00, 0x00, 0x00 }; 98 99 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 100 unsigned size) 101 { 102 assert(offset < sizeof(chipid_and_omr)); 103 return chipid_and_omr[offset]; 104 } 105 106 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 107 uint64_t value, unsigned size) 108 { 109 return; 110 } 111 112 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 113 .read = exynos4210_chipid_and_omr_read, 114 .write = exynos4210_chipid_and_omr_write, 115 .endianness = DEVICE_NATIVE_ENDIAN, 116 .impl = { 117 .max_access_size = 1, 118 } 119 }; 120 121 void exynos4210_write_secondary(ARMCPU *cpu, 122 const struct arm_boot_info *info) 123 { 124 int n; 125 uint32_t smpboot[] = { 126 0xe59f3034, /* ldr r3, External gic_cpu_if */ 127 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 128 0xe59f0034, /* ldr r0, startaddr */ 129 0xe3a01001, /* mov r1, #1 */ 130 0xe5821000, /* str r1, [r2] */ 131 0xe5831000, /* str r1, [r3] */ 132 0xe3a010ff, /* mov r1, #0xff */ 133 0xe5821004, /* str r1, [r2, #4] */ 134 0xe5831004, /* str r1, [r3, #4] */ 135 0xf57ff04f, /* dsb */ 136 0xe320f003, /* wfi */ 137 0xe5901000, /* ldr r1, [r0] */ 138 0xe1110001, /* tst r1, r1 */ 139 0x0afffffb, /* beq <wfi> */ 140 0xe12fff11, /* bx r1 */ 141 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 142 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 143 0 /* bootreg: Boot register address is held here */ 144 }; 145 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 146 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 147 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 148 smpboot[n] = tswap32(smpboot[n]); 149 } 150 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 151 info->smp_loader_start); 152 } 153 154 static uint64_t exynos4210_calc_affinity(int cpu) 155 { 156 uint64_t mp_affinity; 157 158 /* Exynos4210 has 0x9 as cluster ID */ 159 mp_affinity = (0x9 << ARM_AFF1_SHIFT) | cpu; 160 161 return mp_affinity; 162 } 163 164 Exynos4210State *exynos4210_init(MemoryRegion *system_mem) 165 { 166 Exynos4210State *s = g_new(Exynos4210State, 1); 167 qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; 168 SysBusDevice *busdev; 169 ObjectClass *cpu_oc; 170 DeviceState *dev; 171 int i, n; 172 173 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); 174 assert(cpu_oc); 175 176 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 177 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 178 179 /* By default A9 CPUs have EL3 enabled. This board does not currently 180 * support EL3 so the CPU EL3 property is disabled before realization. 181 */ 182 if (object_property_find(cpuobj, "has_el3", NULL)) { 183 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 184 } 185 186 s->cpu[n] = ARM_CPU(cpuobj); 187 object_property_set_int(cpuobj, exynos4210_calc_affinity(n), 188 "mp-affinity", &error_abort); 189 object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 190 "reset-cbar", &error_abort); 191 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 192 } 193 194 /*** IRQs ***/ 195 196 s->irq_table = exynos4210_init_irq(&s->irqs); 197 198 /* IRQ Gate */ 199 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 200 dev = qdev_create(NULL, "exynos4210.irq_gate"); 201 qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); 202 qdev_init_nofail(dev); 203 /* Get IRQ Gate input in gate_irq */ 204 for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { 205 gate_irq[i][n] = qdev_get_gpio_in(dev, n); 206 } 207 busdev = SYS_BUS_DEVICE(dev); 208 209 /* Connect IRQ Gate output to CPU's IRQ line */ 210 sysbus_connect_irq(busdev, 0, 211 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 212 } 213 214 /* Private memory region and Internal GIC */ 215 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); 216 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 217 qdev_init_nofail(dev); 218 busdev = SYS_BUS_DEVICE(dev); 219 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 220 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 221 sysbus_connect_irq(busdev, n, gate_irq[n][0]); 222 } 223 for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { 224 s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); 225 } 226 227 /* Cache controller */ 228 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 229 230 /* External GIC */ 231 dev = qdev_create(NULL, "exynos4210.gic"); 232 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 233 qdev_init_nofail(dev); 234 busdev = SYS_BUS_DEVICE(dev); 235 /* Map CPU interface */ 236 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 237 /* Map Distributer interface */ 238 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 239 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 240 sysbus_connect_irq(busdev, n, gate_irq[n][1]); 241 } 242 for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { 243 s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); 244 } 245 246 /* Internal Interrupt Combiner */ 247 dev = qdev_create(NULL, "exynos4210.combiner"); 248 qdev_init_nofail(dev); 249 busdev = SYS_BUS_DEVICE(dev); 250 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 251 sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); 252 } 253 exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); 254 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 255 256 /* External Interrupt Combiner */ 257 dev = qdev_create(NULL, "exynos4210.combiner"); 258 qdev_prop_set_uint32(dev, "external", 1); 259 qdev_init_nofail(dev); 260 busdev = SYS_BUS_DEVICE(dev); 261 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 262 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); 263 } 264 exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); 265 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 266 267 /* Initialize board IRQs. */ 268 exynos4210_init_board_irqs(&s->irqs); 269 270 /*** Memory ***/ 271 272 /* Chip-ID and OMR */ 273 memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops, 274 NULL, "exynos4210.chipid", sizeof(chipid_and_omr)); 275 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 276 &s->chipid_mem); 277 278 /* Internal ROM */ 279 memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom", 280 EXYNOS4210_IROM_SIZE, &error_fatal); 281 vmstate_register_ram_global(&s->irom_mem); 282 memory_region_set_readonly(&s->irom_mem, true); 283 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 284 &s->irom_mem); 285 /* mirror of iROM */ 286 memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias", 287 &s->irom_mem, 288 0, 289 EXYNOS4210_IROM_SIZE); 290 memory_region_set_readonly(&s->irom_alias_mem, true); 291 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 292 &s->irom_alias_mem); 293 294 /* Internal RAM */ 295 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 296 EXYNOS4210_IRAM_SIZE, &error_fatal); 297 vmstate_register_ram_global(&s->iram_mem); 298 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 299 &s->iram_mem); 300 301 /* PMU. 302 * The only reason of existence at the moment is that secondary CPU boot 303 * loader uses PMU INFORM5 register as a holding pen. 304 */ 305 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 306 307 sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL); 308 309 /* PWM */ 310 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 311 s->irq_table[exynos4210_get_irq(22, 0)], 312 s->irq_table[exynos4210_get_irq(22, 1)], 313 s->irq_table[exynos4210_get_irq(22, 2)], 314 s->irq_table[exynos4210_get_irq(22, 3)], 315 s->irq_table[exynos4210_get_irq(22, 4)], 316 NULL); 317 /* RTC */ 318 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 319 s->irq_table[exynos4210_get_irq(23, 0)], 320 s->irq_table[exynos4210_get_irq(23, 1)], 321 NULL); 322 323 /* Multi Core Timer */ 324 dev = qdev_create(NULL, "exynos4210.mct"); 325 qdev_init_nofail(dev); 326 busdev = SYS_BUS_DEVICE(dev); 327 for (n = 0; n < 4; n++) { 328 /* Connect global timer interrupts to Combiner gpio_in */ 329 sysbus_connect_irq(busdev, n, 330 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 331 } 332 /* Connect local timer interrupts to Combiner gpio_in */ 333 sysbus_connect_irq(busdev, 4, 334 s->irq_table[exynos4210_get_irq(51, 0)]); 335 sysbus_connect_irq(busdev, 5, 336 s->irq_table[exynos4210_get_irq(35, 3)]); 337 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 338 339 /*** I2C ***/ 340 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 341 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 342 qemu_irq i2c_irq; 343 344 if (n < 8) { 345 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 346 } else { 347 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 348 } 349 350 dev = qdev_create(NULL, "exynos4210.i2c"); 351 qdev_init_nofail(dev); 352 busdev = SYS_BUS_DEVICE(dev); 353 sysbus_connect_irq(busdev, 0, i2c_irq); 354 sysbus_mmio_map(busdev, 0, addr); 355 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 356 } 357 358 359 /*** UARTs ***/ 360 exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 361 EXYNOS4210_UART0_FIFO_SIZE, 0, NULL, 362 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 363 364 exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 365 EXYNOS4210_UART1_FIFO_SIZE, 1, NULL, 366 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 367 368 exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 369 EXYNOS4210_UART2_FIFO_SIZE, 2, NULL, 370 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 371 372 exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 373 EXYNOS4210_UART3_FIFO_SIZE, 3, NULL, 374 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 375 376 /*** SD/MMC host controllers ***/ 377 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { 378 DeviceState *carddev; 379 BlockBackend *blk; 380 DriveInfo *di; 381 382 dev = qdev_create(NULL, "generic-sdhci"); 383 qdev_prop_set_uint32(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); 384 qdev_init_nofail(dev); 385 386 busdev = SYS_BUS_DEVICE(dev); 387 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); 388 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); 389 390 di = drive_get(IF_SD, 0, n); 391 blk = di ? blk_by_legacy_dinfo(di) : NULL; 392 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 393 qdev_prop_set_drive(carddev, "drive", blk, &error_abort); 394 qdev_init_nofail(carddev); 395 } 396 397 /*** Display controller (FIMD) ***/ 398 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 399 s->irq_table[exynos4210_get_irq(11, 0)], 400 s->irq_table[exynos4210_get_irq(11, 1)], 401 s->irq_table[exynos4210_get_irq(11, 2)], 402 NULL); 403 404 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 405 s->irq_table[exynos4210_get_irq(28, 3)]); 406 407 return s; 408 } 409