1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/boards.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/sysbus.h" 28 #include "hw/arm/arm.h" 29 #include "hw/loader.h" 30 #include "hw/arm/exynos4210.h" 31 #include "hw/usb/hcd-ehci.h" 32 33 #define EXYNOS4210_CHIPID_ADDR 0x10000000 34 35 /* PWM */ 36 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 37 38 /* RTC */ 39 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 40 41 /* MCT */ 42 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 43 44 /* I2C */ 45 #define EXYNOS4210_I2C_SHIFT 0x00010000 46 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 47 /* Interrupt Group of External Interrupt Combiner for I2C */ 48 #define EXYNOS4210_I2C_INTG 27 49 #define EXYNOS4210_HDMI_INTG 16 50 51 /* UART's definitions */ 52 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 53 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 54 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 55 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 56 #define EXYNOS4210_UART0_FIFO_SIZE 256 57 #define EXYNOS4210_UART1_FIFO_SIZE 64 58 #define EXYNOS4210_UART2_FIFO_SIZE 16 59 #define EXYNOS4210_UART3_FIFO_SIZE 16 60 /* Interrupt Group of External Interrupt Combiner for UART */ 61 #define EXYNOS4210_UART_INT_GRP 26 62 63 /* External GIC */ 64 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 65 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 66 67 /* Combiner */ 68 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 69 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 70 71 /* PMU SFR base address */ 72 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 73 74 /* Display controllers (FIMD) */ 75 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 76 77 /* EHCI */ 78 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 79 80 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 81 0x09, 0x00, 0x00, 0x00 }; 82 83 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 84 unsigned size) 85 { 86 assert(offset < sizeof(chipid_and_omr)); 87 return chipid_and_omr[offset]; 88 } 89 90 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 91 uint64_t value, unsigned size) 92 { 93 return; 94 } 95 96 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 97 .read = exynos4210_chipid_and_omr_read, 98 .write = exynos4210_chipid_and_omr_write, 99 .endianness = DEVICE_NATIVE_ENDIAN, 100 .impl = { 101 .max_access_size = 1, 102 } 103 }; 104 105 void exynos4210_write_secondary(ARMCPU *cpu, 106 const struct arm_boot_info *info) 107 { 108 int n; 109 uint32_t smpboot[] = { 110 0xe59f3034, /* ldr r3, External gic_cpu_if */ 111 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 112 0xe59f0034, /* ldr r0, startaddr */ 113 0xe3a01001, /* mov r1, #1 */ 114 0xe5821000, /* str r1, [r2] */ 115 0xe5831000, /* str r1, [r3] */ 116 0xe3a010ff, /* mov r1, #0xff */ 117 0xe5821004, /* str r1, [r2, #4] */ 118 0xe5831004, /* str r1, [r3, #4] */ 119 0xf57ff04f, /* dsb */ 120 0xe320f003, /* wfi */ 121 0xe5901000, /* ldr r1, [r0] */ 122 0xe1110001, /* tst r1, r1 */ 123 0x0afffffb, /* beq <wfi> */ 124 0xe12fff11, /* bx r1 */ 125 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 126 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 127 0 /* bootreg: Boot register address is held here */ 128 }; 129 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 130 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 131 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 132 smpboot[n] = tswap32(smpboot[n]); 133 } 134 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 135 info->smp_loader_start); 136 } 137 138 Exynos4210State *exynos4210_init(MemoryRegion *system_mem, 139 unsigned long ram_size) 140 { 141 int i, n; 142 Exynos4210State *s = g_new(Exynos4210State, 1); 143 qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; 144 unsigned long mem_size; 145 DeviceState *dev; 146 SysBusDevice *busdev; 147 ObjectClass *cpu_oc; 148 149 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); 150 assert(cpu_oc); 151 152 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 153 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 154 155 /* By default A9 CPUs have EL3 enabled. This board does not currently 156 * support EL3 so the CPU EL3 property is disabled before realization. 157 */ 158 if (object_property_find(cpuobj, "has_el3", NULL)) { 159 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 160 } 161 162 s->cpu[n] = ARM_CPU(cpuobj); 163 object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 164 "reset-cbar", &error_abort); 165 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 166 } 167 168 /*** IRQs ***/ 169 170 s->irq_table = exynos4210_init_irq(&s->irqs); 171 172 /* IRQ Gate */ 173 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 174 dev = qdev_create(NULL, "exynos4210.irq_gate"); 175 qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); 176 qdev_init_nofail(dev); 177 /* Get IRQ Gate input in gate_irq */ 178 for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { 179 gate_irq[i][n] = qdev_get_gpio_in(dev, n); 180 } 181 busdev = SYS_BUS_DEVICE(dev); 182 183 /* Connect IRQ Gate output to CPU's IRQ line */ 184 sysbus_connect_irq(busdev, 0, 185 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 186 } 187 188 /* Private memory region and Internal GIC */ 189 dev = qdev_create(NULL, "a9mpcore_priv"); 190 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 191 qdev_init_nofail(dev); 192 busdev = SYS_BUS_DEVICE(dev); 193 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 194 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 195 sysbus_connect_irq(busdev, n, gate_irq[n][0]); 196 } 197 for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { 198 s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); 199 } 200 201 /* Cache controller */ 202 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 203 204 /* External GIC */ 205 dev = qdev_create(NULL, "exynos4210.gic"); 206 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 207 qdev_init_nofail(dev); 208 busdev = SYS_BUS_DEVICE(dev); 209 /* Map CPU interface */ 210 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 211 /* Map Distributer interface */ 212 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 213 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 214 sysbus_connect_irq(busdev, n, gate_irq[n][1]); 215 } 216 for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { 217 s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); 218 } 219 220 /* Internal Interrupt Combiner */ 221 dev = qdev_create(NULL, "exynos4210.combiner"); 222 qdev_init_nofail(dev); 223 busdev = SYS_BUS_DEVICE(dev); 224 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 225 sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); 226 } 227 exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); 228 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 229 230 /* External Interrupt Combiner */ 231 dev = qdev_create(NULL, "exynos4210.combiner"); 232 qdev_prop_set_uint32(dev, "external", 1); 233 qdev_init_nofail(dev); 234 busdev = SYS_BUS_DEVICE(dev); 235 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 236 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); 237 } 238 exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); 239 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 240 241 /* Initialize board IRQs. */ 242 exynos4210_init_board_irqs(&s->irqs); 243 244 /*** Memory ***/ 245 246 /* Chip-ID and OMR */ 247 memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops, 248 NULL, "exynos4210.chipid", sizeof(chipid_and_omr)); 249 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 250 &s->chipid_mem); 251 252 /* Internal ROM */ 253 memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom", 254 EXYNOS4210_IROM_SIZE, &error_fatal); 255 vmstate_register_ram_global(&s->irom_mem); 256 memory_region_set_readonly(&s->irom_mem, true); 257 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 258 &s->irom_mem); 259 /* mirror of iROM */ 260 memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias", 261 &s->irom_mem, 262 0, 263 EXYNOS4210_IROM_SIZE); 264 memory_region_set_readonly(&s->irom_alias_mem, true); 265 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 266 &s->irom_alias_mem); 267 268 /* Internal RAM */ 269 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 270 EXYNOS4210_IRAM_SIZE, &error_fatal); 271 vmstate_register_ram_global(&s->iram_mem); 272 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 273 &s->iram_mem); 274 275 /* DRAM */ 276 mem_size = ram_size; 277 if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { 278 memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", 279 mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal); 280 vmstate_register_ram_global(&s->dram1_mem); 281 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, 282 &s->dram1_mem); 283 mem_size = EXYNOS4210_DRAM_MAX_SIZE; 284 } 285 memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, 286 &error_fatal); 287 vmstate_register_ram_global(&s->dram0_mem); 288 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, 289 &s->dram0_mem); 290 291 /* PMU. 292 * The only reason of existence at the moment is that secondary CPU boot 293 * loader uses PMU INFORM5 register as a holding pen. 294 */ 295 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 296 297 /* PWM */ 298 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 299 s->irq_table[exynos4210_get_irq(22, 0)], 300 s->irq_table[exynos4210_get_irq(22, 1)], 301 s->irq_table[exynos4210_get_irq(22, 2)], 302 s->irq_table[exynos4210_get_irq(22, 3)], 303 s->irq_table[exynos4210_get_irq(22, 4)], 304 NULL); 305 /* RTC */ 306 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 307 s->irq_table[exynos4210_get_irq(23, 0)], 308 s->irq_table[exynos4210_get_irq(23, 1)], 309 NULL); 310 311 /* Multi Core Timer */ 312 dev = qdev_create(NULL, "exynos4210.mct"); 313 qdev_init_nofail(dev); 314 busdev = SYS_BUS_DEVICE(dev); 315 for (n = 0; n < 4; n++) { 316 /* Connect global timer interrupts to Combiner gpio_in */ 317 sysbus_connect_irq(busdev, n, 318 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 319 } 320 /* Connect local timer interrupts to Combiner gpio_in */ 321 sysbus_connect_irq(busdev, 4, 322 s->irq_table[exynos4210_get_irq(51, 0)]); 323 sysbus_connect_irq(busdev, 5, 324 s->irq_table[exynos4210_get_irq(35, 3)]); 325 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 326 327 /*** I2C ***/ 328 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 329 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 330 qemu_irq i2c_irq; 331 332 if (n < 8) { 333 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 334 } else { 335 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 336 } 337 338 dev = qdev_create(NULL, "exynos4210.i2c"); 339 qdev_init_nofail(dev); 340 busdev = SYS_BUS_DEVICE(dev); 341 sysbus_connect_irq(busdev, 0, i2c_irq); 342 sysbus_mmio_map(busdev, 0, addr); 343 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 344 } 345 346 347 /*** UARTs ***/ 348 exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 349 EXYNOS4210_UART0_FIFO_SIZE, 0, NULL, 350 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 351 352 exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 353 EXYNOS4210_UART1_FIFO_SIZE, 1, NULL, 354 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 355 356 exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 357 EXYNOS4210_UART2_FIFO_SIZE, 2, NULL, 358 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 359 360 exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 361 EXYNOS4210_UART3_FIFO_SIZE, 3, NULL, 362 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 363 364 /*** Display controller (FIMD) ***/ 365 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 366 s->irq_table[exynos4210_get_irq(11, 0)], 367 s->irq_table[exynos4210_get_irq(11, 1)], 368 s->irq_table[exynos4210_get_irq(11, 2)], 369 NULL); 370 371 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 372 s->irq_table[exynos4210_get_irq(28, 3)]); 373 374 return s; 375 } 376