1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "hw/cpu/a9mpcore.h" 28 #include "hw/irq.h" 29 #include "sysemu/blockdev.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/sysbus.h" 32 #include "hw/arm/boot.h" 33 #include "hw/loader.h" 34 #include "hw/qdev-properties.h" 35 #include "hw/arm/exynos4210.h" 36 #include "hw/sd/sdhci.h" 37 #include "hw/usb/hcd-ehci.h" 38 39 #define EXYNOS4210_CHIPID_ADDR 0x10000000 40 41 /* PWM */ 42 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 43 44 /* RTC */ 45 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 46 47 /* MCT */ 48 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 49 50 /* I2C */ 51 #define EXYNOS4210_I2C_SHIFT 0x00010000 52 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 53 /* Interrupt Group of External Interrupt Combiner for I2C */ 54 #define EXYNOS4210_I2C_INTG 27 55 #define EXYNOS4210_HDMI_INTG 16 56 57 /* UART's definitions */ 58 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 59 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 60 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 61 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 62 #define EXYNOS4210_UART0_FIFO_SIZE 256 63 #define EXYNOS4210_UART1_FIFO_SIZE 64 64 #define EXYNOS4210_UART2_FIFO_SIZE 16 65 #define EXYNOS4210_UART3_FIFO_SIZE 16 66 /* Interrupt Group of External Interrupt Combiner for UART */ 67 #define EXYNOS4210_UART_INT_GRP 26 68 69 /* External GIC */ 70 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 71 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 72 73 /* Combiner */ 74 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 75 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 76 77 /* SD/MMC host controllers */ 78 #define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 79 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 80 #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ 81 0x00010000 * (n)) 82 #define EXYNOS4210_SDHCI_NUMBER 4 83 84 /* PMU SFR base address */ 85 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 86 87 /* Clock controller SFR base address */ 88 #define EXYNOS4210_CLK_BASE_ADDR 0x10030000 89 90 /* PRNG/HASH SFR base address */ 91 #define EXYNOS4210_RNG_BASE_ADDR 0x10830400 92 93 /* Display controllers (FIMD) */ 94 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 95 96 /* EHCI */ 97 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 98 99 /* DMA */ 100 #define EXYNOS4210_PL330_BASE0_ADDR 0x12680000 101 #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 102 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 103 104 enum ExtGicId { 105 EXT_GIC_ID_MDMA_LCD0 = 66, 106 EXT_GIC_ID_PDMA0, 107 EXT_GIC_ID_PDMA1, 108 EXT_GIC_ID_TIMER0, 109 EXT_GIC_ID_TIMER1, 110 EXT_GIC_ID_TIMER2, 111 EXT_GIC_ID_TIMER3, 112 EXT_GIC_ID_TIMER4, 113 EXT_GIC_ID_MCT_L0, 114 EXT_GIC_ID_WDT, 115 EXT_GIC_ID_RTC_ALARM, 116 EXT_GIC_ID_RTC_TIC, 117 EXT_GIC_ID_GPIO_XB, 118 EXT_GIC_ID_GPIO_XA, 119 EXT_GIC_ID_MCT_L1, 120 EXT_GIC_ID_IEM_APC, 121 EXT_GIC_ID_IEM_IEC, 122 EXT_GIC_ID_NFC, 123 EXT_GIC_ID_UART0, 124 EXT_GIC_ID_UART1, 125 EXT_GIC_ID_UART2, 126 EXT_GIC_ID_UART3, 127 EXT_GIC_ID_UART4, 128 EXT_GIC_ID_MCT_G0, 129 EXT_GIC_ID_I2C0, 130 EXT_GIC_ID_I2C1, 131 EXT_GIC_ID_I2C2, 132 EXT_GIC_ID_I2C3, 133 EXT_GIC_ID_I2C4, 134 EXT_GIC_ID_I2C5, 135 EXT_GIC_ID_I2C6, 136 EXT_GIC_ID_I2C7, 137 EXT_GIC_ID_SPI0, 138 EXT_GIC_ID_SPI1, 139 EXT_GIC_ID_SPI2, 140 EXT_GIC_ID_MCT_G1, 141 EXT_GIC_ID_USB_HOST, 142 EXT_GIC_ID_USB_DEVICE, 143 EXT_GIC_ID_MODEMIF, 144 EXT_GIC_ID_HSMMC0, 145 EXT_GIC_ID_HSMMC1, 146 EXT_GIC_ID_HSMMC2, 147 EXT_GIC_ID_HSMMC3, 148 EXT_GIC_ID_SDMMC, 149 EXT_GIC_ID_MIPI_CSI_4LANE, 150 EXT_GIC_ID_MIPI_DSI_4LANE, 151 EXT_GIC_ID_MIPI_CSI_2LANE, 152 EXT_GIC_ID_MIPI_DSI_2LANE, 153 EXT_GIC_ID_ONENAND_AUDI, 154 EXT_GIC_ID_ROTATOR, 155 EXT_GIC_ID_FIMC0, 156 EXT_GIC_ID_FIMC1, 157 EXT_GIC_ID_FIMC2, 158 EXT_GIC_ID_FIMC3, 159 EXT_GIC_ID_JPEG, 160 EXT_GIC_ID_2D, 161 EXT_GIC_ID_PCIe, 162 EXT_GIC_ID_MIXER, 163 EXT_GIC_ID_HDMI, 164 EXT_GIC_ID_HDMI_I2C, 165 EXT_GIC_ID_MFC, 166 EXT_GIC_ID_TVENC, 167 }; 168 169 enum ExtInt { 170 EXT_GIC_ID_EXTINT0 = 48, 171 EXT_GIC_ID_EXTINT1, 172 EXT_GIC_ID_EXTINT2, 173 EXT_GIC_ID_EXTINT3, 174 EXT_GIC_ID_EXTINT4, 175 EXT_GIC_ID_EXTINT5, 176 EXT_GIC_ID_EXTINT6, 177 EXT_GIC_ID_EXTINT7, 178 EXT_GIC_ID_EXTINT8, 179 EXT_GIC_ID_EXTINT9, 180 EXT_GIC_ID_EXTINT10, 181 EXT_GIC_ID_EXTINT11, 182 EXT_GIC_ID_EXTINT12, 183 EXT_GIC_ID_EXTINT13, 184 EXT_GIC_ID_EXTINT14, 185 EXT_GIC_ID_EXTINT15 186 }; 187 188 /* 189 * External GIC sources which are not from External Interrupt Combiner or 190 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, 191 * which is INTG16 in Internal Interrupt Combiner. 192 */ 193 194 static const uint32_t 195 combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { 196 /* int combiner groups 16-19 */ 197 { }, { }, { }, { }, 198 /* int combiner group 20 */ 199 { 0, EXT_GIC_ID_MDMA_LCD0 }, 200 /* int combiner group 21 */ 201 { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, 202 /* int combiner group 22 */ 203 { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, 204 EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, 205 /* int combiner group 23 */ 206 { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, 207 /* int combiner group 24 */ 208 { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, 209 /* int combiner group 25 */ 210 { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, 211 /* int combiner group 26 */ 212 { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, 213 EXT_GIC_ID_UART4 }, 214 /* int combiner group 27 */ 215 { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, 216 EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, 217 EXT_GIC_ID_I2C7 }, 218 /* int combiner group 28 */ 219 { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, 220 /* int combiner group 29 */ 221 { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, 222 EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, 223 /* int combiner group 30 */ 224 { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, 225 /* int combiner group 31 */ 226 { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, 227 /* int combiner group 32 */ 228 { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, 229 /* int combiner group 33 */ 230 { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, 231 /* int combiner group 34 */ 232 { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, 233 /* int combiner group 35 */ 234 { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 235 /* int combiner group 36 */ 236 { EXT_GIC_ID_MIXER }, 237 /* int combiner group 37 */ 238 { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, 239 EXT_GIC_ID_EXTINT7 }, 240 /* groups 38-50 */ 241 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, 242 /* int combiner group 51 */ 243 { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 244 /* group 52 */ 245 { }, 246 /* int combiner group 53 */ 247 { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 248 /* groups 54-63 */ 249 { }, { }, { }, { }, { }, { }, { }, { }, { }, { } 250 }; 251 252 /* 253 * Initialize board IRQs. 254 * These IRQs contain splitted Int/External Combiner and External Gic IRQs. 255 */ 256 static void exynos4210_init_board_irqs(Exynos4210State *s) 257 { 258 uint32_t grp, bit, irq_id, n; 259 Exynos4210Irq *is = &s->irqs; 260 261 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { 262 irq_id = 0; 263 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || 264 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { 265 /* MCT_G0 is passed to External GIC */ 266 irq_id = EXT_GIC_ID_MCT_G0; 267 } 268 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || 269 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { 270 /* MCT_G1 is passed to External and GIC */ 271 irq_id = EXT_GIC_ID_MCT_G1; 272 } 273 if (irq_id) { 274 s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], 275 is->ext_gic_irq[irq_id - 32]); 276 } else { 277 s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], 278 is->ext_combiner_irq[n]); 279 } 280 } 281 for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { 282 /* these IDs are passed to Internal Combiner and External GIC */ 283 grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); 284 bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); 285 irq_id = combiner_grp_to_gic_id[grp - 286 EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; 287 288 if (irq_id) { 289 s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], 290 is->ext_gic_irq[irq_id - 32]); 291 } 292 } 293 } 294 295 /* 296 * Get IRQ number from exynos4210 IRQ subsystem stub. 297 * To identify IRQ source use internal combiner group and bit number 298 * grp - group number 299 * bit - bit number inside group 300 */ 301 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) 302 { 303 return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); 304 } 305 306 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 307 0x09, 0x00, 0x00, 0x00 }; 308 309 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 310 unsigned size) 311 { 312 assert(offset < sizeof(chipid_and_omr)); 313 return chipid_and_omr[offset]; 314 } 315 316 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 317 uint64_t value, unsigned size) 318 { 319 return; 320 } 321 322 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 323 .read = exynos4210_chipid_and_omr_read, 324 .write = exynos4210_chipid_and_omr_write, 325 .endianness = DEVICE_NATIVE_ENDIAN, 326 .impl = { 327 .max_access_size = 1, 328 } 329 }; 330 331 void exynos4210_write_secondary(ARMCPU *cpu, 332 const struct arm_boot_info *info) 333 { 334 int n; 335 uint32_t smpboot[] = { 336 0xe59f3034, /* ldr r3, External gic_cpu_if */ 337 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 338 0xe59f0034, /* ldr r0, startaddr */ 339 0xe3a01001, /* mov r1, #1 */ 340 0xe5821000, /* str r1, [r2] */ 341 0xe5831000, /* str r1, [r3] */ 342 0xe3a010ff, /* mov r1, #0xff */ 343 0xe5821004, /* str r1, [r2, #4] */ 344 0xe5831004, /* str r1, [r3, #4] */ 345 0xf57ff04f, /* dsb */ 346 0xe320f003, /* wfi */ 347 0xe5901000, /* ldr r1, [r0] */ 348 0xe1110001, /* tst r1, r1 */ 349 0x0afffffb, /* beq <wfi> */ 350 0xe12fff11, /* bx r1 */ 351 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 352 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 353 0 /* bootreg: Boot register address is held here */ 354 }; 355 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 356 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 357 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 358 smpboot[n] = tswap32(smpboot[n]); 359 } 360 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 361 info->smp_loader_start); 362 } 363 364 static uint64_t exynos4210_calc_affinity(int cpu) 365 { 366 /* Exynos4210 has 0x9 as cluster ID */ 367 return (0x9 << ARM_AFF1_SHIFT) | cpu; 368 } 369 370 static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate, 371 qemu_irq irq, int nreq, int nevents, int width) 372 { 373 SysBusDevice *busdev; 374 DeviceState *dev; 375 int i; 376 377 dev = qdev_new("pl330"); 378 object_property_set_link(OBJECT(dev), "memory", 379 OBJECT(get_system_memory()), 380 &error_fatal); 381 qdev_prop_set_uint8(dev, "num_events", nevents); 382 qdev_prop_set_uint8(dev, "num_chnls", 8); 383 qdev_prop_set_uint8(dev, "num_periph_req", nreq); 384 385 qdev_prop_set_uint8(dev, "wr_cap", 4); 386 qdev_prop_set_uint8(dev, "wr_q_dep", 8); 387 qdev_prop_set_uint8(dev, "rd_cap", 4); 388 qdev_prop_set_uint8(dev, "rd_q_dep", 8); 389 qdev_prop_set_uint8(dev, "data_width", width); 390 qdev_prop_set_uint16(dev, "data_buffer_dep", width); 391 busdev = SYS_BUS_DEVICE(dev); 392 sysbus_realize_and_unref(busdev, &error_fatal); 393 sysbus_mmio_map(busdev, 0, base); 394 395 object_property_set_int(OBJECT(orgate), "num-lines", nevents + 1, 396 &error_abort); 397 qdev_realize(DEVICE(orgate), NULL, &error_abort); 398 399 for (i = 0; i < nevents + 1; i++) { 400 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i)); 401 } 402 qdev_connect_gpio_out(DEVICE(orgate), 0, irq); 403 return dev; 404 } 405 406 static void exynos4210_realize(DeviceState *socdev, Error **errp) 407 { 408 Exynos4210State *s = EXYNOS4210_SOC(socdev); 409 MemoryRegion *system_mem = get_system_memory(); 410 SysBusDevice *busdev; 411 DeviceState *dev, *uart[4], *pl330[3]; 412 int i, n; 413 414 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 415 Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); 416 417 /* By default A9 CPUs have EL3 enabled. This board does not currently 418 * support EL3 so the CPU EL3 property is disabled before realization. 419 */ 420 if (object_property_find(cpuobj, "has_el3")) { 421 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 422 } 423 424 s->cpu[n] = ARM_CPU(cpuobj); 425 object_property_set_int(cpuobj, "mp-affinity", 426 exynos4210_calc_affinity(n), &error_abort); 427 object_property_set_int(cpuobj, "reset-cbar", 428 EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 429 &error_abort); 430 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 431 } 432 433 /* IRQ Gate */ 434 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 435 DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); 436 object_property_set_int(OBJECT(orgate), "num-lines", 437 EXYNOS4210_IRQ_GATE_NINPUTS, 438 &error_abort); 439 qdev_realize(orgate, NULL, &error_abort); 440 qdev_connect_gpio_out(orgate, 0, 441 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 442 } 443 444 /* Private memory region and Internal GIC */ 445 qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); 446 busdev = SYS_BUS_DEVICE(&s->a9mpcore); 447 sysbus_realize(busdev, &error_fatal); 448 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 449 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 450 sysbus_connect_irq(busdev, n, 451 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); 452 } 453 454 /* Cache controller */ 455 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 456 457 /* External GIC */ 458 dev = qdev_new("exynos4210.gic"); 459 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 460 busdev = SYS_BUS_DEVICE(dev); 461 sysbus_realize_and_unref(busdev, &error_fatal); 462 /* Map CPU interface */ 463 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 464 /* Map Distributer interface */ 465 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 466 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 467 sysbus_connect_irq(busdev, n, 468 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); 469 } 470 for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { 471 s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); 472 } 473 474 /* Internal Interrupt Combiner */ 475 dev = qdev_new("exynos4210.combiner"); 476 busdev = SYS_BUS_DEVICE(dev); 477 sysbus_realize_and_unref(busdev, &error_fatal); 478 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 479 sysbus_connect_irq(busdev, n, 480 qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); 481 } 482 exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); 483 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 484 485 /* External Interrupt Combiner */ 486 dev = qdev_new("exynos4210.combiner"); 487 qdev_prop_set_uint32(dev, "external", 1); 488 busdev = SYS_BUS_DEVICE(dev); 489 sysbus_realize_and_unref(busdev, &error_fatal); 490 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 491 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); 492 } 493 exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); 494 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 495 496 /* Initialize board IRQs. */ 497 exynos4210_init_board_irqs(s); 498 499 /*** Memory ***/ 500 501 /* Chip-ID and OMR */ 502 memory_region_init_io(&s->chipid_mem, OBJECT(socdev), 503 &exynos4210_chipid_and_omr_ops, NULL, 504 "exynos4210.chipid", sizeof(chipid_and_omr)); 505 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 506 &s->chipid_mem); 507 508 /* Internal ROM */ 509 memory_region_init_rom(&s->irom_mem, OBJECT(socdev), "exynos4210.irom", 510 EXYNOS4210_IROM_SIZE, &error_fatal); 511 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 512 &s->irom_mem); 513 /* mirror of iROM */ 514 memory_region_init_alias(&s->irom_alias_mem, OBJECT(socdev), 515 "exynos4210.irom_alias", &s->irom_mem, 0, 516 EXYNOS4210_IROM_SIZE); 517 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 518 &s->irom_alias_mem); 519 520 /* Internal RAM */ 521 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 522 EXYNOS4210_IRAM_SIZE, &error_fatal); 523 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 524 &s->iram_mem); 525 526 /* PMU. 527 * The only reason of existence at the moment is that secondary CPU boot 528 * loader uses PMU INFORM5 register as a holding pen. 529 */ 530 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 531 532 sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL); 533 sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL); 534 535 /* PWM */ 536 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 537 s->irq_table[exynos4210_get_irq(22, 0)], 538 s->irq_table[exynos4210_get_irq(22, 1)], 539 s->irq_table[exynos4210_get_irq(22, 2)], 540 s->irq_table[exynos4210_get_irq(22, 3)], 541 s->irq_table[exynos4210_get_irq(22, 4)], 542 NULL); 543 /* RTC */ 544 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 545 s->irq_table[exynos4210_get_irq(23, 0)], 546 s->irq_table[exynos4210_get_irq(23, 1)], 547 NULL); 548 549 /* Multi Core Timer */ 550 dev = qdev_new("exynos4210.mct"); 551 busdev = SYS_BUS_DEVICE(dev); 552 sysbus_realize_and_unref(busdev, &error_fatal); 553 for (n = 0; n < 4; n++) { 554 /* Connect global timer interrupts to Combiner gpio_in */ 555 sysbus_connect_irq(busdev, n, 556 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 557 } 558 /* Connect local timer interrupts to Combiner gpio_in */ 559 sysbus_connect_irq(busdev, 4, 560 s->irq_table[exynos4210_get_irq(51, 0)]); 561 sysbus_connect_irq(busdev, 5, 562 s->irq_table[exynos4210_get_irq(35, 3)]); 563 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 564 565 /*** I2C ***/ 566 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 567 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 568 qemu_irq i2c_irq; 569 570 if (n < 8) { 571 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 572 } else { 573 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 574 } 575 576 dev = qdev_new("exynos4210.i2c"); 577 busdev = SYS_BUS_DEVICE(dev); 578 sysbus_realize_and_unref(busdev, &error_fatal); 579 sysbus_connect_irq(busdev, 0, i2c_irq); 580 sysbus_mmio_map(busdev, 0, addr); 581 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 582 } 583 584 585 /*** UARTs ***/ 586 uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 587 EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0), 588 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 589 590 uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 591 EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1), 592 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 593 594 uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 595 EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2), 596 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 597 598 uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 599 EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3), 600 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 601 602 /*** SD/MMC host controllers ***/ 603 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { 604 DeviceState *carddev; 605 BlockBackend *blk; 606 DriveInfo *di; 607 608 /* Compatible with: 609 * - SD Host Controller Specification Version 2.0 610 * - SDIO Specification Version 2.0 611 * - MMC Specification Version 4.3 612 * - SDMA 613 * - ADMA2 614 * 615 * As this part of the Exynos4210 is not publically available, 616 * we used the "HS-MMC Controller S3C2416X RISC Microprocessor" 617 * public datasheet which is very similar (implementing 618 * MMC Specification Version 4.0 being the only difference noted) 619 */ 620 dev = qdev_new(TYPE_S3C_SDHCI); 621 qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); 622 623 busdev = SYS_BUS_DEVICE(dev); 624 sysbus_realize_and_unref(busdev, &error_fatal); 625 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); 626 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); 627 628 di = drive_get(IF_SD, 0, n); 629 blk = di ? blk_by_legacy_dinfo(di) : NULL; 630 carddev = qdev_new(TYPE_SD_CARD); 631 qdev_prop_set_drive(carddev, "drive", blk); 632 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), 633 &error_fatal); 634 } 635 636 /*** Display controller (FIMD) ***/ 637 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 638 s->irq_table[exynos4210_get_irq(11, 0)], 639 s->irq_table[exynos4210_get_irq(11, 1)], 640 s->irq_table[exynos4210_get_irq(11, 2)], 641 NULL); 642 643 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 644 s->irq_table[exynos4210_get_irq(28, 3)]); 645 646 /*** DMA controllers ***/ 647 pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR, 648 &s->pl330_irq_orgate[0], 649 s->irq_table[exynos4210_get_irq(21, 0)], 650 32, 32, 32); 651 pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR, 652 &s->pl330_irq_orgate[1], 653 s->irq_table[exynos4210_get_irq(21, 1)], 654 32, 32, 32); 655 pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR, 656 &s->pl330_irq_orgate[2], 657 s->irq_table[exynos4210_get_irq(20, 1)], 658 1, 31, 64); 659 660 sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1, 661 qdev_get_gpio_in(pl330[0], 15)); 662 sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1, 663 qdev_get_gpio_in(pl330[1], 15)); 664 sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1, 665 qdev_get_gpio_in(pl330[0], 17)); 666 sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1, 667 qdev_get_gpio_in(pl330[1], 17)); 668 } 669 670 static void exynos4210_init(Object *obj) 671 { 672 Exynos4210State *s = EXYNOS4210_SOC(obj); 673 int i; 674 675 for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { 676 char *name = g_strdup_printf("pl330-irq-orgate%d", i); 677 qemu_or_irq *orgate = &s->pl330_irq_orgate[i]; 678 679 object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); 680 g_free(name); 681 } 682 683 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { 684 g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); 685 object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); 686 } 687 688 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 689 } 690 691 static void exynos4210_class_init(ObjectClass *klass, void *data) 692 { 693 DeviceClass *dc = DEVICE_CLASS(klass); 694 695 dc->realize = exynos4210_realize; 696 } 697 698 static const TypeInfo exynos4210_info = { 699 .name = TYPE_EXYNOS4210_SOC, 700 .parent = TYPE_SYS_BUS_DEVICE, 701 .instance_size = sizeof(Exynos4210State), 702 .instance_init = exynos4210_init, 703 .class_init = exynos4210_class_init, 704 }; 705 706 static void exynos4210_register_types(void) 707 { 708 type_register_static(&exynos4210_info); 709 } 710 711 type_init(exynos4210_register_types) 712