1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "hw/boards.h" 25 #include "sysemu/sysemu.h" 26 #include "hw/sysbus.h" 27 #include "hw/arm/arm.h" 28 #include "hw/loader.h" 29 #include "hw/arm/exynos4210.h" 30 #include "hw/usb/hcd-ehci.h" 31 32 #define EXYNOS4210_CHIPID_ADDR 0x10000000 33 34 /* PWM */ 35 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 36 37 /* RTC */ 38 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 39 40 /* MCT */ 41 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 42 43 /* I2C */ 44 #define EXYNOS4210_I2C_SHIFT 0x00010000 45 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 46 /* Interrupt Group of External Interrupt Combiner for I2C */ 47 #define EXYNOS4210_I2C_INTG 27 48 #define EXYNOS4210_HDMI_INTG 16 49 50 /* UART's definitions */ 51 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 52 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 53 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 54 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 55 #define EXYNOS4210_UART0_FIFO_SIZE 256 56 #define EXYNOS4210_UART1_FIFO_SIZE 64 57 #define EXYNOS4210_UART2_FIFO_SIZE 16 58 #define EXYNOS4210_UART3_FIFO_SIZE 16 59 /* Interrupt Group of External Interrupt Combiner for UART */ 60 #define EXYNOS4210_UART_INT_GRP 26 61 62 /* External GIC */ 63 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 64 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 65 66 /* Combiner */ 67 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 68 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 69 70 /* PMU SFR base address */ 71 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 72 73 /* Display controllers (FIMD) */ 74 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 75 76 /* EHCI */ 77 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 78 79 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 80 0x09, 0x00, 0x00, 0x00 }; 81 82 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 83 unsigned size) 84 { 85 assert(offset < sizeof(chipid_and_omr)); 86 return chipid_and_omr[offset]; 87 } 88 89 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 90 uint64_t value, unsigned size) 91 { 92 return; 93 } 94 95 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 96 .read = exynos4210_chipid_and_omr_read, 97 .write = exynos4210_chipid_and_omr_write, 98 .endianness = DEVICE_NATIVE_ENDIAN, 99 .impl = { 100 .max_access_size = 1, 101 } 102 }; 103 104 void exynos4210_write_secondary(ARMCPU *cpu, 105 const struct arm_boot_info *info) 106 { 107 int n; 108 uint32_t smpboot[] = { 109 0xe59f3034, /* ldr r3, External gic_cpu_if */ 110 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 111 0xe59f0034, /* ldr r0, startaddr */ 112 0xe3a01001, /* mov r1, #1 */ 113 0xe5821000, /* str r1, [r2] */ 114 0xe5831000, /* str r1, [r3] */ 115 0xe3a010ff, /* mov r1, #0xff */ 116 0xe5821004, /* str r1, [r2, #4] */ 117 0xe5831004, /* str r1, [r3, #4] */ 118 0xf57ff04f, /* dsb */ 119 0xe320f003, /* wfi */ 120 0xe5901000, /* ldr r1, [r0] */ 121 0xe1110001, /* tst r1, r1 */ 122 0x0afffffb, /* beq <wfi> */ 123 0xe12fff11, /* bx r1 */ 124 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 125 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 126 0 /* bootreg: Boot register address is held here */ 127 }; 128 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 129 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 130 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 131 smpboot[n] = tswap32(smpboot[n]); 132 } 133 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 134 info->smp_loader_start); 135 } 136 137 Exynos4210State *exynos4210_init(MemoryRegion *system_mem, 138 unsigned long ram_size) 139 { 140 int i, n; 141 Exynos4210State *s = g_new(Exynos4210State, 1); 142 qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; 143 unsigned long mem_size; 144 DeviceState *dev; 145 SysBusDevice *busdev; 146 ObjectClass *cpu_oc; 147 148 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); 149 assert(cpu_oc); 150 151 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 152 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 153 154 /* By default A9 CPUs have EL3 enabled. This board does not currently 155 * support EL3 so the CPU EL3 property is disabled before realization. 156 */ 157 if (object_property_find(cpuobj, "has_el3", NULL)) { 158 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 159 } 160 161 s->cpu[n] = ARM_CPU(cpuobj); 162 object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 163 "reset-cbar", &error_abort); 164 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 165 } 166 167 /*** IRQs ***/ 168 169 s->irq_table = exynos4210_init_irq(&s->irqs); 170 171 /* IRQ Gate */ 172 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 173 dev = qdev_create(NULL, "exynos4210.irq_gate"); 174 qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); 175 qdev_init_nofail(dev); 176 /* Get IRQ Gate input in gate_irq */ 177 for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { 178 gate_irq[i][n] = qdev_get_gpio_in(dev, n); 179 } 180 busdev = SYS_BUS_DEVICE(dev); 181 182 /* Connect IRQ Gate output to CPU's IRQ line */ 183 sysbus_connect_irq(busdev, 0, 184 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 185 } 186 187 /* Private memory region and Internal GIC */ 188 dev = qdev_create(NULL, "a9mpcore_priv"); 189 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 190 qdev_init_nofail(dev); 191 busdev = SYS_BUS_DEVICE(dev); 192 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 193 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 194 sysbus_connect_irq(busdev, n, gate_irq[n][0]); 195 } 196 for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { 197 s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); 198 } 199 200 /* Cache controller */ 201 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 202 203 /* External GIC */ 204 dev = qdev_create(NULL, "exynos4210.gic"); 205 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 206 qdev_init_nofail(dev); 207 busdev = SYS_BUS_DEVICE(dev); 208 /* Map CPU interface */ 209 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 210 /* Map Distributer interface */ 211 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 212 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 213 sysbus_connect_irq(busdev, n, gate_irq[n][1]); 214 } 215 for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { 216 s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); 217 } 218 219 /* Internal Interrupt Combiner */ 220 dev = qdev_create(NULL, "exynos4210.combiner"); 221 qdev_init_nofail(dev); 222 busdev = SYS_BUS_DEVICE(dev); 223 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 224 sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); 225 } 226 exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); 227 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 228 229 /* External Interrupt Combiner */ 230 dev = qdev_create(NULL, "exynos4210.combiner"); 231 qdev_prop_set_uint32(dev, "external", 1); 232 qdev_init_nofail(dev); 233 busdev = SYS_BUS_DEVICE(dev); 234 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 235 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); 236 } 237 exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); 238 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 239 240 /* Initialize board IRQs. */ 241 exynos4210_init_board_irqs(&s->irqs); 242 243 /*** Memory ***/ 244 245 /* Chip-ID and OMR */ 246 memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops, 247 NULL, "exynos4210.chipid", sizeof(chipid_and_omr)); 248 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 249 &s->chipid_mem); 250 251 /* Internal ROM */ 252 memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom", 253 EXYNOS4210_IROM_SIZE, &error_fatal); 254 vmstate_register_ram_global(&s->irom_mem); 255 memory_region_set_readonly(&s->irom_mem, true); 256 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 257 &s->irom_mem); 258 /* mirror of iROM */ 259 memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias", 260 &s->irom_mem, 261 0, 262 EXYNOS4210_IROM_SIZE); 263 memory_region_set_readonly(&s->irom_alias_mem, true); 264 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 265 &s->irom_alias_mem); 266 267 /* Internal RAM */ 268 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 269 EXYNOS4210_IRAM_SIZE, &error_fatal); 270 vmstate_register_ram_global(&s->iram_mem); 271 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 272 &s->iram_mem); 273 274 /* DRAM */ 275 mem_size = ram_size; 276 if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { 277 memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", 278 mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal); 279 vmstate_register_ram_global(&s->dram1_mem); 280 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, 281 &s->dram1_mem); 282 mem_size = EXYNOS4210_DRAM_MAX_SIZE; 283 } 284 memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, 285 &error_fatal); 286 vmstate_register_ram_global(&s->dram0_mem); 287 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, 288 &s->dram0_mem); 289 290 /* PMU. 291 * The only reason of existence at the moment is that secondary CPU boot 292 * loader uses PMU INFORM5 register as a holding pen. 293 */ 294 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 295 296 /* PWM */ 297 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 298 s->irq_table[exynos4210_get_irq(22, 0)], 299 s->irq_table[exynos4210_get_irq(22, 1)], 300 s->irq_table[exynos4210_get_irq(22, 2)], 301 s->irq_table[exynos4210_get_irq(22, 3)], 302 s->irq_table[exynos4210_get_irq(22, 4)], 303 NULL); 304 /* RTC */ 305 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 306 s->irq_table[exynos4210_get_irq(23, 0)], 307 s->irq_table[exynos4210_get_irq(23, 1)], 308 NULL); 309 310 /* Multi Core Timer */ 311 dev = qdev_create(NULL, "exynos4210.mct"); 312 qdev_init_nofail(dev); 313 busdev = SYS_BUS_DEVICE(dev); 314 for (n = 0; n < 4; n++) { 315 /* Connect global timer interrupts to Combiner gpio_in */ 316 sysbus_connect_irq(busdev, n, 317 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 318 } 319 /* Connect local timer interrupts to Combiner gpio_in */ 320 sysbus_connect_irq(busdev, 4, 321 s->irq_table[exynos4210_get_irq(51, 0)]); 322 sysbus_connect_irq(busdev, 5, 323 s->irq_table[exynos4210_get_irq(35, 3)]); 324 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 325 326 /*** I2C ***/ 327 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 328 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 329 qemu_irq i2c_irq; 330 331 if (n < 8) { 332 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 333 } else { 334 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 335 } 336 337 dev = qdev_create(NULL, "exynos4210.i2c"); 338 qdev_init_nofail(dev); 339 busdev = SYS_BUS_DEVICE(dev); 340 sysbus_connect_irq(busdev, 0, i2c_irq); 341 sysbus_mmio_map(busdev, 0, addr); 342 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 343 } 344 345 346 /*** UARTs ***/ 347 exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 348 EXYNOS4210_UART0_FIFO_SIZE, 0, NULL, 349 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 350 351 exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 352 EXYNOS4210_UART1_FIFO_SIZE, 1, NULL, 353 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 354 355 exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 356 EXYNOS4210_UART2_FIFO_SIZE, 2, NULL, 357 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 358 359 exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 360 EXYNOS4210_UART3_FIFO_SIZE, 3, NULL, 361 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 362 363 /*** Display controller (FIMD) ***/ 364 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 365 s->irq_table[exynos4210_get_irq(11, 0)], 366 s->irq_table[exynos4210_get_irq(11, 1)], 367 s->irq_table[exynos4210_get_irq(11, 2)], 368 NULL); 369 370 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 371 s->irq_table[exynos4210_get_irq(28, 3)]); 372 373 return s; 374 } 375