1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "qemu/log.h" 28 #include "cpu.h" 29 #include "hw/boards.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/sysbus.h" 32 #include "hw/arm/arm.h" 33 #include "hw/loader.h" 34 #include "hw/arm/exynos4210.h" 35 #include "hw/sd/sd.h" 36 #include "hw/usb/hcd-ehci.h" 37 38 #define EXYNOS4210_CHIPID_ADDR 0x10000000 39 40 /* PWM */ 41 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 42 43 /* RTC */ 44 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 45 46 /* MCT */ 47 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 48 49 /* I2C */ 50 #define EXYNOS4210_I2C_SHIFT 0x00010000 51 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 52 /* Interrupt Group of External Interrupt Combiner for I2C */ 53 #define EXYNOS4210_I2C_INTG 27 54 #define EXYNOS4210_HDMI_INTG 16 55 56 /* UART's definitions */ 57 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 58 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 59 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 60 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 61 #define EXYNOS4210_UART0_FIFO_SIZE 256 62 #define EXYNOS4210_UART1_FIFO_SIZE 64 63 #define EXYNOS4210_UART2_FIFO_SIZE 16 64 #define EXYNOS4210_UART3_FIFO_SIZE 16 65 /* Interrupt Group of External Interrupt Combiner for UART */ 66 #define EXYNOS4210_UART_INT_GRP 26 67 68 /* External GIC */ 69 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 70 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 71 72 /* Combiner */ 73 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 74 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 75 76 /* SD/MMC host controllers */ 77 #define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 78 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 79 #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ 80 0x00010000 * (n)) 81 #define EXYNOS4210_SDHCI_NUMBER 4 82 83 /* PMU SFR base address */ 84 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 85 86 /* Clock controller SFR base address */ 87 #define EXYNOS4210_CLK_BASE_ADDR 0x10030000 88 89 /* Display controllers (FIMD) */ 90 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 91 92 /* EHCI */ 93 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 94 95 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 96 0x09, 0x00, 0x00, 0x00 }; 97 98 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 99 unsigned size) 100 { 101 assert(offset < sizeof(chipid_and_omr)); 102 return chipid_and_omr[offset]; 103 } 104 105 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 106 uint64_t value, unsigned size) 107 { 108 return; 109 } 110 111 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 112 .read = exynos4210_chipid_and_omr_read, 113 .write = exynos4210_chipid_and_omr_write, 114 .endianness = DEVICE_NATIVE_ENDIAN, 115 .impl = { 116 .max_access_size = 1, 117 } 118 }; 119 120 void exynos4210_write_secondary(ARMCPU *cpu, 121 const struct arm_boot_info *info) 122 { 123 int n; 124 uint32_t smpboot[] = { 125 0xe59f3034, /* ldr r3, External gic_cpu_if */ 126 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 127 0xe59f0034, /* ldr r0, startaddr */ 128 0xe3a01001, /* mov r1, #1 */ 129 0xe5821000, /* str r1, [r2] */ 130 0xe5831000, /* str r1, [r3] */ 131 0xe3a010ff, /* mov r1, #0xff */ 132 0xe5821004, /* str r1, [r2, #4] */ 133 0xe5831004, /* str r1, [r3, #4] */ 134 0xf57ff04f, /* dsb */ 135 0xe320f003, /* wfi */ 136 0xe5901000, /* ldr r1, [r0] */ 137 0xe1110001, /* tst r1, r1 */ 138 0x0afffffb, /* beq <wfi> */ 139 0xe12fff11, /* bx r1 */ 140 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 141 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 142 0 /* bootreg: Boot register address is held here */ 143 }; 144 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 145 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 146 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 147 smpboot[n] = tswap32(smpboot[n]); 148 } 149 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 150 info->smp_loader_start); 151 } 152 153 static uint64_t exynos4210_calc_affinity(int cpu) 154 { 155 uint64_t mp_affinity; 156 157 /* Exynos4210 has 0x9 as cluster ID */ 158 mp_affinity = (0x9 << ARM_AFF1_SHIFT) | cpu; 159 160 return mp_affinity; 161 } 162 163 Exynos4210State *exynos4210_init(MemoryRegion *system_mem, 164 unsigned long ram_size) 165 { 166 int i, n; 167 Exynos4210State *s = g_new(Exynos4210State, 1); 168 qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; 169 unsigned long mem_size; 170 DeviceState *dev; 171 SysBusDevice *busdev; 172 ObjectClass *cpu_oc; 173 174 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); 175 assert(cpu_oc); 176 177 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 178 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 179 180 /* By default A9 CPUs have EL3 enabled. This board does not currently 181 * support EL3 so the CPU EL3 property is disabled before realization. 182 */ 183 if (object_property_find(cpuobj, "has_el3", NULL)) { 184 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 185 } 186 187 s->cpu[n] = ARM_CPU(cpuobj); 188 object_property_set_int(cpuobj, exynos4210_calc_affinity(n), 189 "mp-affinity", &error_abort); 190 object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 191 "reset-cbar", &error_abort); 192 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 193 } 194 195 /*** IRQs ***/ 196 197 s->irq_table = exynos4210_init_irq(&s->irqs); 198 199 /* IRQ Gate */ 200 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 201 dev = qdev_create(NULL, "exynos4210.irq_gate"); 202 qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); 203 qdev_init_nofail(dev); 204 /* Get IRQ Gate input in gate_irq */ 205 for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { 206 gate_irq[i][n] = qdev_get_gpio_in(dev, n); 207 } 208 busdev = SYS_BUS_DEVICE(dev); 209 210 /* Connect IRQ Gate output to CPU's IRQ line */ 211 sysbus_connect_irq(busdev, 0, 212 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 213 } 214 215 /* Private memory region and Internal GIC */ 216 dev = qdev_create(NULL, "a9mpcore_priv"); 217 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 218 qdev_init_nofail(dev); 219 busdev = SYS_BUS_DEVICE(dev); 220 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 221 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 222 sysbus_connect_irq(busdev, n, gate_irq[n][0]); 223 } 224 for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { 225 s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); 226 } 227 228 /* Cache controller */ 229 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 230 231 /* External GIC */ 232 dev = qdev_create(NULL, "exynos4210.gic"); 233 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 234 qdev_init_nofail(dev); 235 busdev = SYS_BUS_DEVICE(dev); 236 /* Map CPU interface */ 237 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 238 /* Map Distributer interface */ 239 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 240 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 241 sysbus_connect_irq(busdev, n, gate_irq[n][1]); 242 } 243 for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { 244 s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); 245 } 246 247 /* Internal Interrupt Combiner */ 248 dev = qdev_create(NULL, "exynos4210.combiner"); 249 qdev_init_nofail(dev); 250 busdev = SYS_BUS_DEVICE(dev); 251 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 252 sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); 253 } 254 exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); 255 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 256 257 /* External Interrupt Combiner */ 258 dev = qdev_create(NULL, "exynos4210.combiner"); 259 qdev_prop_set_uint32(dev, "external", 1); 260 qdev_init_nofail(dev); 261 busdev = SYS_BUS_DEVICE(dev); 262 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 263 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); 264 } 265 exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); 266 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 267 268 /* Initialize board IRQs. */ 269 exynos4210_init_board_irqs(&s->irqs); 270 271 /*** Memory ***/ 272 273 /* Chip-ID and OMR */ 274 memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops, 275 NULL, "exynos4210.chipid", sizeof(chipid_and_omr)); 276 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 277 &s->chipid_mem); 278 279 /* Internal ROM */ 280 memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom", 281 EXYNOS4210_IROM_SIZE, &error_fatal); 282 vmstate_register_ram_global(&s->irom_mem); 283 memory_region_set_readonly(&s->irom_mem, true); 284 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 285 &s->irom_mem); 286 /* mirror of iROM */ 287 memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias", 288 &s->irom_mem, 289 0, 290 EXYNOS4210_IROM_SIZE); 291 memory_region_set_readonly(&s->irom_alias_mem, true); 292 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 293 &s->irom_alias_mem); 294 295 /* Internal RAM */ 296 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 297 EXYNOS4210_IRAM_SIZE, &error_fatal); 298 vmstate_register_ram_global(&s->iram_mem); 299 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 300 &s->iram_mem); 301 302 /* DRAM */ 303 mem_size = ram_size; 304 if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { 305 memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", 306 mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal); 307 vmstate_register_ram_global(&s->dram1_mem); 308 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, 309 &s->dram1_mem); 310 mem_size = EXYNOS4210_DRAM_MAX_SIZE; 311 } 312 memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, 313 &error_fatal); 314 vmstate_register_ram_global(&s->dram0_mem); 315 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, 316 &s->dram0_mem); 317 318 /* PMU. 319 * The only reason of existence at the moment is that secondary CPU boot 320 * loader uses PMU INFORM5 register as a holding pen. 321 */ 322 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 323 324 sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL); 325 326 /* PWM */ 327 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 328 s->irq_table[exynos4210_get_irq(22, 0)], 329 s->irq_table[exynos4210_get_irq(22, 1)], 330 s->irq_table[exynos4210_get_irq(22, 2)], 331 s->irq_table[exynos4210_get_irq(22, 3)], 332 s->irq_table[exynos4210_get_irq(22, 4)], 333 NULL); 334 /* RTC */ 335 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 336 s->irq_table[exynos4210_get_irq(23, 0)], 337 s->irq_table[exynos4210_get_irq(23, 1)], 338 NULL); 339 340 /* Multi Core Timer */ 341 dev = qdev_create(NULL, "exynos4210.mct"); 342 qdev_init_nofail(dev); 343 busdev = SYS_BUS_DEVICE(dev); 344 for (n = 0; n < 4; n++) { 345 /* Connect global timer interrupts to Combiner gpio_in */ 346 sysbus_connect_irq(busdev, n, 347 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 348 } 349 /* Connect local timer interrupts to Combiner gpio_in */ 350 sysbus_connect_irq(busdev, 4, 351 s->irq_table[exynos4210_get_irq(51, 0)]); 352 sysbus_connect_irq(busdev, 5, 353 s->irq_table[exynos4210_get_irq(35, 3)]); 354 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 355 356 /*** I2C ***/ 357 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 358 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 359 qemu_irq i2c_irq; 360 361 if (n < 8) { 362 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 363 } else { 364 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 365 } 366 367 dev = qdev_create(NULL, "exynos4210.i2c"); 368 qdev_init_nofail(dev); 369 busdev = SYS_BUS_DEVICE(dev); 370 sysbus_connect_irq(busdev, 0, i2c_irq); 371 sysbus_mmio_map(busdev, 0, addr); 372 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 373 } 374 375 376 /*** UARTs ***/ 377 exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 378 EXYNOS4210_UART0_FIFO_SIZE, 0, NULL, 379 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 380 381 exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 382 EXYNOS4210_UART1_FIFO_SIZE, 1, NULL, 383 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 384 385 exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 386 EXYNOS4210_UART2_FIFO_SIZE, 2, NULL, 387 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 388 389 exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 390 EXYNOS4210_UART3_FIFO_SIZE, 3, NULL, 391 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 392 393 /*** SD/MMC host controllers ***/ 394 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { 395 DeviceState *carddev; 396 BlockBackend *blk; 397 DriveInfo *di; 398 399 dev = qdev_create(NULL, "generic-sdhci"); 400 qdev_prop_set_uint32(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); 401 qdev_init_nofail(dev); 402 403 busdev = SYS_BUS_DEVICE(dev); 404 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); 405 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); 406 407 di = drive_get(IF_SD, 0, n); 408 blk = di ? blk_by_legacy_dinfo(di) : NULL; 409 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 410 qdev_prop_set_drive(carddev, "drive", blk, &error_abort); 411 qdev_init_nofail(carddev); 412 } 413 414 /*** Display controller (FIMD) ***/ 415 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 416 s->irq_table[exynos4210_get_irq(11, 0)], 417 s->irq_table[exynos4210_get_irq(11, 1)], 418 s->irq_table[exynos4210_get_irq(11, 2)], 419 NULL); 420 421 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 422 s->irq_table[exynos4210_get_irq(28, 3)]); 423 424 return s; 425 } 426