1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "hw/cpu/a9mpcore.h" 28 #include "hw/irq.h" 29 #include "sysemu/blockdev.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/sysbus.h" 32 #include "hw/arm/boot.h" 33 #include "hw/loader.h" 34 #include "hw/qdev-properties.h" 35 #include "hw/arm/exynos4210.h" 36 #include "hw/sd/sdhci.h" 37 #include "hw/usb/hcd-ehci.h" 38 39 #define EXYNOS4210_CHIPID_ADDR 0x10000000 40 41 /* PWM */ 42 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 43 44 /* RTC */ 45 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 46 47 /* MCT */ 48 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 49 50 /* I2C */ 51 #define EXYNOS4210_I2C_SHIFT 0x00010000 52 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 53 /* Interrupt Group of External Interrupt Combiner for I2C */ 54 #define EXYNOS4210_I2C_INTG 27 55 #define EXYNOS4210_HDMI_INTG 16 56 57 /* UART's definitions */ 58 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 59 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 60 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 61 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 62 #define EXYNOS4210_UART0_FIFO_SIZE 256 63 #define EXYNOS4210_UART1_FIFO_SIZE 64 64 #define EXYNOS4210_UART2_FIFO_SIZE 16 65 #define EXYNOS4210_UART3_FIFO_SIZE 16 66 /* Interrupt Group of External Interrupt Combiner for UART */ 67 #define EXYNOS4210_UART_INT_GRP 26 68 69 /* External GIC */ 70 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 71 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 72 73 /* Combiner */ 74 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 75 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 76 77 /* SD/MMC host controllers */ 78 #define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 79 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 80 #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ 81 0x00010000 * (n)) 82 #define EXYNOS4210_SDHCI_NUMBER 4 83 84 /* PMU SFR base address */ 85 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 86 87 /* Clock controller SFR base address */ 88 #define EXYNOS4210_CLK_BASE_ADDR 0x10030000 89 90 /* PRNG/HASH SFR base address */ 91 #define EXYNOS4210_RNG_BASE_ADDR 0x10830400 92 93 /* Display controllers (FIMD) */ 94 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 95 96 /* EHCI */ 97 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 98 99 /* DMA */ 100 #define EXYNOS4210_PL330_BASE0_ADDR 0x12680000 101 #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 102 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 103 104 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 105 0x09, 0x00, 0x00, 0x00 }; 106 107 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 108 unsigned size) 109 { 110 assert(offset < sizeof(chipid_and_omr)); 111 return chipid_and_omr[offset]; 112 } 113 114 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 115 uint64_t value, unsigned size) 116 { 117 return; 118 } 119 120 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 121 .read = exynos4210_chipid_and_omr_read, 122 .write = exynos4210_chipid_and_omr_write, 123 .endianness = DEVICE_NATIVE_ENDIAN, 124 .impl = { 125 .max_access_size = 1, 126 } 127 }; 128 129 void exynos4210_write_secondary(ARMCPU *cpu, 130 const struct arm_boot_info *info) 131 { 132 int n; 133 uint32_t smpboot[] = { 134 0xe59f3034, /* ldr r3, External gic_cpu_if */ 135 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 136 0xe59f0034, /* ldr r0, startaddr */ 137 0xe3a01001, /* mov r1, #1 */ 138 0xe5821000, /* str r1, [r2] */ 139 0xe5831000, /* str r1, [r3] */ 140 0xe3a010ff, /* mov r1, #0xff */ 141 0xe5821004, /* str r1, [r2, #4] */ 142 0xe5831004, /* str r1, [r3, #4] */ 143 0xf57ff04f, /* dsb */ 144 0xe320f003, /* wfi */ 145 0xe5901000, /* ldr r1, [r0] */ 146 0xe1110001, /* tst r1, r1 */ 147 0x0afffffb, /* beq <wfi> */ 148 0xe12fff11, /* bx r1 */ 149 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 150 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 151 0 /* bootreg: Boot register address is held here */ 152 }; 153 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 154 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 155 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 156 smpboot[n] = tswap32(smpboot[n]); 157 } 158 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 159 info->smp_loader_start); 160 } 161 162 static uint64_t exynos4210_calc_affinity(int cpu) 163 { 164 /* Exynos4210 has 0x9 as cluster ID */ 165 return (0x9 << ARM_AFF1_SHIFT) | cpu; 166 } 167 168 static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate, 169 qemu_irq irq, int nreq, int nevents, int width) 170 { 171 SysBusDevice *busdev; 172 DeviceState *dev; 173 int i; 174 175 dev = qdev_new("pl330"); 176 object_property_set_link(OBJECT(dev), "memory", 177 OBJECT(get_system_memory()), 178 &error_fatal); 179 qdev_prop_set_uint8(dev, "num_events", nevents); 180 qdev_prop_set_uint8(dev, "num_chnls", 8); 181 qdev_prop_set_uint8(dev, "num_periph_req", nreq); 182 183 qdev_prop_set_uint8(dev, "wr_cap", 4); 184 qdev_prop_set_uint8(dev, "wr_q_dep", 8); 185 qdev_prop_set_uint8(dev, "rd_cap", 4); 186 qdev_prop_set_uint8(dev, "rd_q_dep", 8); 187 qdev_prop_set_uint8(dev, "data_width", width); 188 qdev_prop_set_uint16(dev, "data_buffer_dep", width); 189 busdev = SYS_BUS_DEVICE(dev); 190 sysbus_realize_and_unref(busdev, &error_fatal); 191 sysbus_mmio_map(busdev, 0, base); 192 193 object_property_set_int(OBJECT(orgate), "num-lines", nevents + 1, 194 &error_abort); 195 qdev_realize(DEVICE(orgate), NULL, &error_abort); 196 197 for (i = 0; i < nevents + 1; i++) { 198 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i)); 199 } 200 qdev_connect_gpio_out(DEVICE(orgate), 0, irq); 201 return dev; 202 } 203 204 static void exynos4210_realize(DeviceState *socdev, Error **errp) 205 { 206 Exynos4210State *s = EXYNOS4210_SOC(socdev); 207 MemoryRegion *system_mem = get_system_memory(); 208 SysBusDevice *busdev; 209 DeviceState *dev, *uart[4], *pl330[3]; 210 int i, n; 211 212 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 213 Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); 214 215 /* By default A9 CPUs have EL3 enabled. This board does not currently 216 * support EL3 so the CPU EL3 property is disabled before realization. 217 */ 218 if (object_property_find(cpuobj, "has_el3")) { 219 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 220 } 221 222 s->cpu[n] = ARM_CPU(cpuobj); 223 object_property_set_int(cpuobj, "mp-affinity", 224 exynos4210_calc_affinity(n), &error_abort); 225 object_property_set_int(cpuobj, "reset-cbar", 226 EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 227 &error_abort); 228 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 229 } 230 231 /* IRQ Gate */ 232 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 233 DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); 234 object_property_set_int(OBJECT(orgate), "num-lines", 235 EXYNOS4210_IRQ_GATE_NINPUTS, 236 &error_abort); 237 qdev_realize(orgate, NULL, &error_abort); 238 qdev_connect_gpio_out(orgate, 0, 239 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 240 } 241 242 /* Private memory region and Internal GIC */ 243 qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); 244 busdev = SYS_BUS_DEVICE(&s->a9mpcore); 245 sysbus_realize(busdev, &error_fatal); 246 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 247 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 248 sysbus_connect_irq(busdev, n, 249 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); 250 } 251 252 /* Cache controller */ 253 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 254 255 /* External GIC */ 256 dev = qdev_new("exynos4210.gic"); 257 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 258 busdev = SYS_BUS_DEVICE(dev); 259 sysbus_realize_and_unref(busdev, &error_fatal); 260 /* Map CPU interface */ 261 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 262 /* Map Distributer interface */ 263 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 264 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 265 sysbus_connect_irq(busdev, n, 266 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); 267 } 268 for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { 269 s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); 270 } 271 272 /* Internal Interrupt Combiner */ 273 dev = qdev_new("exynos4210.combiner"); 274 busdev = SYS_BUS_DEVICE(dev); 275 sysbus_realize_and_unref(busdev, &error_fatal); 276 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 277 sysbus_connect_irq(busdev, n, 278 qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); 279 } 280 exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); 281 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 282 283 /* External Interrupt Combiner */ 284 dev = qdev_new("exynos4210.combiner"); 285 qdev_prop_set_uint32(dev, "external", 1); 286 busdev = SYS_BUS_DEVICE(dev); 287 sysbus_realize_and_unref(busdev, &error_fatal); 288 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 289 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); 290 } 291 exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); 292 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 293 294 /* Initialize board IRQs. */ 295 exynos4210_init_board_irqs(s); 296 297 /*** Memory ***/ 298 299 /* Chip-ID and OMR */ 300 memory_region_init_io(&s->chipid_mem, OBJECT(socdev), 301 &exynos4210_chipid_and_omr_ops, NULL, 302 "exynos4210.chipid", sizeof(chipid_and_omr)); 303 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 304 &s->chipid_mem); 305 306 /* Internal ROM */ 307 memory_region_init_rom(&s->irom_mem, OBJECT(socdev), "exynos4210.irom", 308 EXYNOS4210_IROM_SIZE, &error_fatal); 309 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 310 &s->irom_mem); 311 /* mirror of iROM */ 312 memory_region_init_alias(&s->irom_alias_mem, OBJECT(socdev), 313 "exynos4210.irom_alias", &s->irom_mem, 0, 314 EXYNOS4210_IROM_SIZE); 315 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 316 &s->irom_alias_mem); 317 318 /* Internal RAM */ 319 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 320 EXYNOS4210_IRAM_SIZE, &error_fatal); 321 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 322 &s->iram_mem); 323 324 /* PMU. 325 * The only reason of existence at the moment is that secondary CPU boot 326 * loader uses PMU INFORM5 register as a holding pen. 327 */ 328 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 329 330 sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL); 331 sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL); 332 333 /* PWM */ 334 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 335 s->irq_table[exynos4210_get_irq(22, 0)], 336 s->irq_table[exynos4210_get_irq(22, 1)], 337 s->irq_table[exynos4210_get_irq(22, 2)], 338 s->irq_table[exynos4210_get_irq(22, 3)], 339 s->irq_table[exynos4210_get_irq(22, 4)], 340 NULL); 341 /* RTC */ 342 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 343 s->irq_table[exynos4210_get_irq(23, 0)], 344 s->irq_table[exynos4210_get_irq(23, 1)], 345 NULL); 346 347 /* Multi Core Timer */ 348 dev = qdev_new("exynos4210.mct"); 349 busdev = SYS_BUS_DEVICE(dev); 350 sysbus_realize_and_unref(busdev, &error_fatal); 351 for (n = 0; n < 4; n++) { 352 /* Connect global timer interrupts to Combiner gpio_in */ 353 sysbus_connect_irq(busdev, n, 354 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 355 } 356 /* Connect local timer interrupts to Combiner gpio_in */ 357 sysbus_connect_irq(busdev, 4, 358 s->irq_table[exynos4210_get_irq(51, 0)]); 359 sysbus_connect_irq(busdev, 5, 360 s->irq_table[exynos4210_get_irq(35, 3)]); 361 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 362 363 /*** I2C ***/ 364 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 365 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 366 qemu_irq i2c_irq; 367 368 if (n < 8) { 369 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 370 } else { 371 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 372 } 373 374 dev = qdev_new("exynos4210.i2c"); 375 busdev = SYS_BUS_DEVICE(dev); 376 sysbus_realize_and_unref(busdev, &error_fatal); 377 sysbus_connect_irq(busdev, 0, i2c_irq); 378 sysbus_mmio_map(busdev, 0, addr); 379 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 380 } 381 382 383 /*** UARTs ***/ 384 uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 385 EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0), 386 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 387 388 uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 389 EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1), 390 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 391 392 uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 393 EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2), 394 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 395 396 uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 397 EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3), 398 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 399 400 /*** SD/MMC host controllers ***/ 401 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { 402 DeviceState *carddev; 403 BlockBackend *blk; 404 DriveInfo *di; 405 406 /* Compatible with: 407 * - SD Host Controller Specification Version 2.0 408 * - SDIO Specification Version 2.0 409 * - MMC Specification Version 4.3 410 * - SDMA 411 * - ADMA2 412 * 413 * As this part of the Exynos4210 is not publically available, 414 * we used the "HS-MMC Controller S3C2416X RISC Microprocessor" 415 * public datasheet which is very similar (implementing 416 * MMC Specification Version 4.0 being the only difference noted) 417 */ 418 dev = qdev_new(TYPE_S3C_SDHCI); 419 qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); 420 421 busdev = SYS_BUS_DEVICE(dev); 422 sysbus_realize_and_unref(busdev, &error_fatal); 423 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); 424 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); 425 426 di = drive_get(IF_SD, 0, n); 427 blk = di ? blk_by_legacy_dinfo(di) : NULL; 428 carddev = qdev_new(TYPE_SD_CARD); 429 qdev_prop_set_drive(carddev, "drive", blk); 430 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), 431 &error_fatal); 432 } 433 434 /*** Display controller (FIMD) ***/ 435 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 436 s->irq_table[exynos4210_get_irq(11, 0)], 437 s->irq_table[exynos4210_get_irq(11, 1)], 438 s->irq_table[exynos4210_get_irq(11, 2)], 439 NULL); 440 441 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 442 s->irq_table[exynos4210_get_irq(28, 3)]); 443 444 /*** DMA controllers ***/ 445 pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR, 446 &s->pl330_irq_orgate[0], 447 s->irq_table[exynos4210_get_irq(21, 0)], 448 32, 32, 32); 449 pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR, 450 &s->pl330_irq_orgate[1], 451 s->irq_table[exynos4210_get_irq(21, 1)], 452 32, 32, 32); 453 pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR, 454 &s->pl330_irq_orgate[2], 455 s->irq_table[exynos4210_get_irq(20, 1)], 456 1, 31, 64); 457 458 sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1, 459 qdev_get_gpio_in(pl330[0], 15)); 460 sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1, 461 qdev_get_gpio_in(pl330[1], 15)); 462 sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1, 463 qdev_get_gpio_in(pl330[0], 17)); 464 sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1, 465 qdev_get_gpio_in(pl330[1], 17)); 466 } 467 468 static void exynos4210_init(Object *obj) 469 { 470 Exynos4210State *s = EXYNOS4210_SOC(obj); 471 int i; 472 473 for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { 474 char *name = g_strdup_printf("pl330-irq-orgate%d", i); 475 qemu_or_irq *orgate = &s->pl330_irq_orgate[i]; 476 477 object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); 478 g_free(name); 479 } 480 481 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { 482 g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); 483 object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); 484 } 485 486 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 487 } 488 489 static void exynos4210_class_init(ObjectClass *klass, void *data) 490 { 491 DeviceClass *dc = DEVICE_CLASS(klass); 492 493 dc->realize = exynos4210_realize; 494 } 495 496 static const TypeInfo exynos4210_info = { 497 .name = TYPE_EXYNOS4210_SOC, 498 .parent = TYPE_SYS_BUS_DEVICE, 499 .instance_size = sizeof(Exynos4210State), 500 .instance_init = exynos4210_init, 501 .class_init = exynos4210_class_init, 502 }; 503 504 static void exynos4210_register_types(void) 505 { 506 type_register_static(&exynos4210_info); 507 } 508 509 type_init(exynos4210_register_types) 510