1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "qemu/log.h" 28 #include "cpu.h" 29 #include "hw/cpu/a9mpcore.h" 30 #include "hw/boards.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/sysbus.h" 33 #include "hw/arm/boot.h" 34 #include "hw/loader.h" 35 #include "hw/arm/exynos4210.h" 36 #include "hw/sd/sdhci.h" 37 #include "hw/usb/hcd-ehci.h" 38 39 #define EXYNOS4210_CHIPID_ADDR 0x10000000 40 41 /* PWM */ 42 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 43 44 /* RTC */ 45 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 46 47 /* MCT */ 48 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 49 50 /* I2C */ 51 #define EXYNOS4210_I2C_SHIFT 0x00010000 52 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 53 /* Interrupt Group of External Interrupt Combiner for I2C */ 54 #define EXYNOS4210_I2C_INTG 27 55 #define EXYNOS4210_HDMI_INTG 16 56 57 /* UART's definitions */ 58 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 59 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 60 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 61 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 62 #define EXYNOS4210_UART0_FIFO_SIZE 256 63 #define EXYNOS4210_UART1_FIFO_SIZE 64 64 #define EXYNOS4210_UART2_FIFO_SIZE 16 65 #define EXYNOS4210_UART3_FIFO_SIZE 16 66 /* Interrupt Group of External Interrupt Combiner for UART */ 67 #define EXYNOS4210_UART_INT_GRP 26 68 69 /* External GIC */ 70 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 71 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 72 73 /* Combiner */ 74 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 75 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 76 77 /* SD/MMC host controllers */ 78 #define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 79 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 80 #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ 81 0x00010000 * (n)) 82 #define EXYNOS4210_SDHCI_NUMBER 4 83 84 /* PMU SFR base address */ 85 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 86 87 /* Clock controller SFR base address */ 88 #define EXYNOS4210_CLK_BASE_ADDR 0x10030000 89 90 /* PRNG/HASH SFR base address */ 91 #define EXYNOS4210_RNG_BASE_ADDR 0x10830400 92 93 /* Display controllers (FIMD) */ 94 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 95 96 /* EHCI */ 97 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 98 99 /* DMA */ 100 #define EXYNOS4210_PL330_BASE0_ADDR 0x12680000 101 #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 102 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 103 104 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 105 0x09, 0x00, 0x00, 0x00 }; 106 107 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 108 unsigned size) 109 { 110 assert(offset < sizeof(chipid_and_omr)); 111 return chipid_and_omr[offset]; 112 } 113 114 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 115 uint64_t value, unsigned size) 116 { 117 return; 118 } 119 120 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 121 .read = exynos4210_chipid_and_omr_read, 122 .write = exynos4210_chipid_and_omr_write, 123 .endianness = DEVICE_NATIVE_ENDIAN, 124 .impl = { 125 .max_access_size = 1, 126 } 127 }; 128 129 void exynos4210_write_secondary(ARMCPU *cpu, 130 const struct arm_boot_info *info) 131 { 132 int n; 133 uint32_t smpboot[] = { 134 0xe59f3034, /* ldr r3, External gic_cpu_if */ 135 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 136 0xe59f0034, /* ldr r0, startaddr */ 137 0xe3a01001, /* mov r1, #1 */ 138 0xe5821000, /* str r1, [r2] */ 139 0xe5831000, /* str r1, [r3] */ 140 0xe3a010ff, /* mov r1, #0xff */ 141 0xe5821004, /* str r1, [r2, #4] */ 142 0xe5831004, /* str r1, [r3, #4] */ 143 0xf57ff04f, /* dsb */ 144 0xe320f003, /* wfi */ 145 0xe5901000, /* ldr r1, [r0] */ 146 0xe1110001, /* tst r1, r1 */ 147 0x0afffffb, /* beq <wfi> */ 148 0xe12fff11, /* bx r1 */ 149 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 150 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 151 0 /* bootreg: Boot register address is held here */ 152 }; 153 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 154 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 155 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 156 smpboot[n] = tswap32(smpboot[n]); 157 } 158 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 159 info->smp_loader_start); 160 } 161 162 static uint64_t exynos4210_calc_affinity(int cpu) 163 { 164 /* Exynos4210 has 0x9 as cluster ID */ 165 return (0x9 << ARM_AFF1_SHIFT) | cpu; 166 } 167 168 static void pl330_create(uint32_t base, qemu_irq irq, int nreq) 169 { 170 SysBusDevice *busdev; 171 DeviceState *dev; 172 173 dev = qdev_create(NULL, "pl330"); 174 qdev_prop_set_uint8(dev, "num_periph_req", nreq); 175 qdev_init_nofail(dev); 176 busdev = SYS_BUS_DEVICE(dev); 177 sysbus_mmio_map(busdev, 0, base); 178 sysbus_connect_irq(busdev, 0, irq); 179 } 180 181 static void exynos4210_realize(DeviceState *socdev, Error **errp) 182 { 183 Exynos4210State *s = EXYNOS4210_SOC(socdev); 184 MemoryRegion *system_mem = get_system_memory(); 185 qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; 186 SysBusDevice *busdev; 187 DeviceState *dev; 188 int i, n; 189 190 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 191 Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); 192 193 /* By default A9 CPUs have EL3 enabled. This board does not currently 194 * support EL3 so the CPU EL3 property is disabled before realization. 195 */ 196 if (object_property_find(cpuobj, "has_el3", NULL)) { 197 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 198 } 199 200 s->cpu[n] = ARM_CPU(cpuobj); 201 object_property_set_int(cpuobj, exynos4210_calc_affinity(n), 202 "mp-affinity", &error_abort); 203 object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 204 "reset-cbar", &error_abort); 205 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 206 } 207 208 /*** IRQs ***/ 209 210 s->irq_table = exynos4210_init_irq(&s->irqs); 211 212 /* IRQ Gate */ 213 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 214 dev = qdev_create(NULL, "exynos4210.irq_gate"); 215 qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); 216 qdev_init_nofail(dev); 217 /* Get IRQ Gate input in gate_irq */ 218 for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { 219 gate_irq[i][n] = qdev_get_gpio_in(dev, n); 220 } 221 busdev = SYS_BUS_DEVICE(dev); 222 223 /* Connect IRQ Gate output to CPU's IRQ line */ 224 sysbus_connect_irq(busdev, 0, 225 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 226 } 227 228 /* Private memory region and Internal GIC */ 229 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); 230 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 231 qdev_init_nofail(dev); 232 busdev = SYS_BUS_DEVICE(dev); 233 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 234 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 235 sysbus_connect_irq(busdev, n, gate_irq[n][0]); 236 } 237 for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { 238 s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); 239 } 240 241 /* Cache controller */ 242 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 243 244 /* External GIC */ 245 dev = qdev_create(NULL, "exynos4210.gic"); 246 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 247 qdev_init_nofail(dev); 248 busdev = SYS_BUS_DEVICE(dev); 249 /* Map CPU interface */ 250 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 251 /* Map Distributer interface */ 252 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 253 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 254 sysbus_connect_irq(busdev, n, gate_irq[n][1]); 255 } 256 for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { 257 s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); 258 } 259 260 /* Internal Interrupt Combiner */ 261 dev = qdev_create(NULL, "exynos4210.combiner"); 262 qdev_init_nofail(dev); 263 busdev = SYS_BUS_DEVICE(dev); 264 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 265 sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); 266 } 267 exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); 268 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 269 270 /* External Interrupt Combiner */ 271 dev = qdev_create(NULL, "exynos4210.combiner"); 272 qdev_prop_set_uint32(dev, "external", 1); 273 qdev_init_nofail(dev); 274 busdev = SYS_BUS_DEVICE(dev); 275 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 276 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); 277 } 278 exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); 279 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 280 281 /* Initialize board IRQs. */ 282 exynos4210_init_board_irqs(&s->irqs); 283 284 /*** Memory ***/ 285 286 /* Chip-ID and OMR */ 287 memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops, 288 NULL, "exynos4210.chipid", sizeof(chipid_and_omr)); 289 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 290 &s->chipid_mem); 291 292 /* Internal ROM */ 293 memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom", 294 EXYNOS4210_IROM_SIZE, &error_fatal); 295 memory_region_set_readonly(&s->irom_mem, true); 296 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 297 &s->irom_mem); 298 /* mirror of iROM */ 299 memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias", 300 &s->irom_mem, 301 0, 302 EXYNOS4210_IROM_SIZE); 303 memory_region_set_readonly(&s->irom_alias_mem, true); 304 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 305 &s->irom_alias_mem); 306 307 /* Internal RAM */ 308 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 309 EXYNOS4210_IRAM_SIZE, &error_fatal); 310 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 311 &s->iram_mem); 312 313 /* PMU. 314 * The only reason of existence at the moment is that secondary CPU boot 315 * loader uses PMU INFORM5 register as a holding pen. 316 */ 317 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 318 319 sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL); 320 sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL); 321 322 /* PWM */ 323 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 324 s->irq_table[exynos4210_get_irq(22, 0)], 325 s->irq_table[exynos4210_get_irq(22, 1)], 326 s->irq_table[exynos4210_get_irq(22, 2)], 327 s->irq_table[exynos4210_get_irq(22, 3)], 328 s->irq_table[exynos4210_get_irq(22, 4)], 329 NULL); 330 /* RTC */ 331 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 332 s->irq_table[exynos4210_get_irq(23, 0)], 333 s->irq_table[exynos4210_get_irq(23, 1)], 334 NULL); 335 336 /* Multi Core Timer */ 337 dev = qdev_create(NULL, "exynos4210.mct"); 338 qdev_init_nofail(dev); 339 busdev = SYS_BUS_DEVICE(dev); 340 for (n = 0; n < 4; n++) { 341 /* Connect global timer interrupts to Combiner gpio_in */ 342 sysbus_connect_irq(busdev, n, 343 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 344 } 345 /* Connect local timer interrupts to Combiner gpio_in */ 346 sysbus_connect_irq(busdev, 4, 347 s->irq_table[exynos4210_get_irq(51, 0)]); 348 sysbus_connect_irq(busdev, 5, 349 s->irq_table[exynos4210_get_irq(35, 3)]); 350 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 351 352 /*** I2C ***/ 353 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 354 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 355 qemu_irq i2c_irq; 356 357 if (n < 8) { 358 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 359 } else { 360 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 361 } 362 363 dev = qdev_create(NULL, "exynos4210.i2c"); 364 qdev_init_nofail(dev); 365 busdev = SYS_BUS_DEVICE(dev); 366 sysbus_connect_irq(busdev, 0, i2c_irq); 367 sysbus_mmio_map(busdev, 0, addr); 368 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 369 } 370 371 372 /*** UARTs ***/ 373 exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 374 EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0), 375 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 376 377 exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 378 EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1), 379 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 380 381 exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 382 EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2), 383 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 384 385 exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 386 EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3), 387 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 388 389 /*** SD/MMC host controllers ***/ 390 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { 391 DeviceState *carddev; 392 BlockBackend *blk; 393 DriveInfo *di; 394 395 /* Compatible with: 396 * - SD Host Controller Specification Version 2.0 397 * - SDIO Specification Version 2.0 398 * - MMC Specification Version 4.3 399 * - SDMA 400 * - ADMA2 401 * 402 * As this part of the Exynos4210 is not publically available, 403 * we used the "HS-MMC Controller S3C2416X RISC Microprocessor" 404 * public datasheet which is very similar (implementing 405 * MMC Specification Version 4.0 being the only difference noted) 406 */ 407 dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); 408 qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); 409 qdev_init_nofail(dev); 410 411 busdev = SYS_BUS_DEVICE(dev); 412 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); 413 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); 414 415 di = drive_get(IF_SD, 0, n); 416 blk = di ? blk_by_legacy_dinfo(di) : NULL; 417 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 418 qdev_prop_set_drive(carddev, "drive", blk, &error_abort); 419 qdev_init_nofail(carddev); 420 } 421 422 /*** Display controller (FIMD) ***/ 423 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 424 s->irq_table[exynos4210_get_irq(11, 0)], 425 s->irq_table[exynos4210_get_irq(11, 1)], 426 s->irq_table[exynos4210_get_irq(11, 2)], 427 NULL); 428 429 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 430 s->irq_table[exynos4210_get_irq(28, 3)]); 431 432 /*** DMA controllers ***/ 433 pl330_create(EXYNOS4210_PL330_BASE0_ADDR, 434 qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32); 435 pl330_create(EXYNOS4210_PL330_BASE1_ADDR, 436 qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32); 437 pl330_create(EXYNOS4210_PL330_BASE2_ADDR, 438 qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1); 439 } 440 441 static void exynos4210_class_init(ObjectClass *klass, void *data) 442 { 443 DeviceClass *dc = DEVICE_CLASS(klass); 444 445 dc->realize = exynos4210_realize; 446 } 447 448 static const TypeInfo exynos4210_info = { 449 .name = TYPE_EXYNOS4210_SOC, 450 .parent = TYPE_SYS_BUS_DEVICE, 451 .instance_size = sizeof(Exynos4210State), 452 .class_init = exynos4210_class_init, 453 }; 454 455 static void exynos4210_register_types(void) 456 { 457 type_register_static(&exynos4210_info); 458 } 459 460 type_init(exynos4210_register_types) 461