1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/sysbus.h" 29 #include "hw/arm/arm.h" 30 #include "hw/loader.h" 31 #include "hw/arm/exynos4210.h" 32 #include "hw/usb/hcd-ehci.h" 33 34 #define EXYNOS4210_CHIPID_ADDR 0x10000000 35 36 /* PWM */ 37 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 38 39 /* RTC */ 40 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 41 42 /* MCT */ 43 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 44 45 /* I2C */ 46 #define EXYNOS4210_I2C_SHIFT 0x00010000 47 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 48 /* Interrupt Group of External Interrupt Combiner for I2C */ 49 #define EXYNOS4210_I2C_INTG 27 50 #define EXYNOS4210_HDMI_INTG 16 51 52 /* UART's definitions */ 53 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 54 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 55 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 56 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 57 #define EXYNOS4210_UART0_FIFO_SIZE 256 58 #define EXYNOS4210_UART1_FIFO_SIZE 64 59 #define EXYNOS4210_UART2_FIFO_SIZE 16 60 #define EXYNOS4210_UART3_FIFO_SIZE 16 61 /* Interrupt Group of External Interrupt Combiner for UART */ 62 #define EXYNOS4210_UART_INT_GRP 26 63 64 /* External GIC */ 65 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 66 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 67 68 /* Combiner */ 69 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 70 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 71 72 /* PMU SFR base address */ 73 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 74 75 /* Display controllers (FIMD) */ 76 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 77 78 /* EHCI */ 79 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 80 81 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 82 0x09, 0x00, 0x00, 0x00 }; 83 84 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 85 unsigned size) 86 { 87 assert(offset < sizeof(chipid_and_omr)); 88 return chipid_and_omr[offset]; 89 } 90 91 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 92 uint64_t value, unsigned size) 93 { 94 return; 95 } 96 97 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 98 .read = exynos4210_chipid_and_omr_read, 99 .write = exynos4210_chipid_and_omr_write, 100 .endianness = DEVICE_NATIVE_ENDIAN, 101 .impl = { 102 .max_access_size = 1, 103 } 104 }; 105 106 void exynos4210_write_secondary(ARMCPU *cpu, 107 const struct arm_boot_info *info) 108 { 109 int n; 110 uint32_t smpboot[] = { 111 0xe59f3034, /* ldr r3, External gic_cpu_if */ 112 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 113 0xe59f0034, /* ldr r0, startaddr */ 114 0xe3a01001, /* mov r1, #1 */ 115 0xe5821000, /* str r1, [r2] */ 116 0xe5831000, /* str r1, [r3] */ 117 0xe3a010ff, /* mov r1, #0xff */ 118 0xe5821004, /* str r1, [r2, #4] */ 119 0xe5831004, /* str r1, [r3, #4] */ 120 0xf57ff04f, /* dsb */ 121 0xe320f003, /* wfi */ 122 0xe5901000, /* ldr r1, [r0] */ 123 0xe1110001, /* tst r1, r1 */ 124 0x0afffffb, /* beq <wfi> */ 125 0xe12fff11, /* bx r1 */ 126 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 127 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 128 0 /* bootreg: Boot register address is held here */ 129 }; 130 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 131 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 132 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 133 smpboot[n] = tswap32(smpboot[n]); 134 } 135 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 136 info->smp_loader_start); 137 } 138 139 Exynos4210State *exynos4210_init(MemoryRegion *system_mem, 140 unsigned long ram_size) 141 { 142 int i, n; 143 Exynos4210State *s = g_new(Exynos4210State, 1); 144 qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; 145 unsigned long mem_size; 146 DeviceState *dev; 147 SysBusDevice *busdev; 148 ObjectClass *cpu_oc; 149 150 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); 151 assert(cpu_oc); 152 153 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 154 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 155 156 /* By default A9 CPUs have EL3 enabled. This board does not currently 157 * support EL3 so the CPU EL3 property is disabled before realization. 158 */ 159 if (object_property_find(cpuobj, "has_el3", NULL)) { 160 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 161 } 162 163 s->cpu[n] = ARM_CPU(cpuobj); 164 object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 165 "reset-cbar", &error_abort); 166 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 167 } 168 169 /*** IRQs ***/ 170 171 s->irq_table = exynos4210_init_irq(&s->irqs); 172 173 /* IRQ Gate */ 174 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 175 dev = qdev_create(NULL, "exynos4210.irq_gate"); 176 qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); 177 qdev_init_nofail(dev); 178 /* Get IRQ Gate input in gate_irq */ 179 for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { 180 gate_irq[i][n] = qdev_get_gpio_in(dev, n); 181 } 182 busdev = SYS_BUS_DEVICE(dev); 183 184 /* Connect IRQ Gate output to CPU's IRQ line */ 185 sysbus_connect_irq(busdev, 0, 186 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 187 } 188 189 /* Private memory region and Internal GIC */ 190 dev = qdev_create(NULL, "a9mpcore_priv"); 191 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 192 qdev_init_nofail(dev); 193 busdev = SYS_BUS_DEVICE(dev); 194 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 195 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 196 sysbus_connect_irq(busdev, n, gate_irq[n][0]); 197 } 198 for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { 199 s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); 200 } 201 202 /* Cache controller */ 203 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 204 205 /* External GIC */ 206 dev = qdev_create(NULL, "exynos4210.gic"); 207 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 208 qdev_init_nofail(dev); 209 busdev = SYS_BUS_DEVICE(dev); 210 /* Map CPU interface */ 211 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 212 /* Map Distributer interface */ 213 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 214 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 215 sysbus_connect_irq(busdev, n, gate_irq[n][1]); 216 } 217 for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { 218 s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); 219 } 220 221 /* Internal Interrupt Combiner */ 222 dev = qdev_create(NULL, "exynos4210.combiner"); 223 qdev_init_nofail(dev); 224 busdev = SYS_BUS_DEVICE(dev); 225 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 226 sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); 227 } 228 exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); 229 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 230 231 /* External Interrupt Combiner */ 232 dev = qdev_create(NULL, "exynos4210.combiner"); 233 qdev_prop_set_uint32(dev, "external", 1); 234 qdev_init_nofail(dev); 235 busdev = SYS_BUS_DEVICE(dev); 236 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 237 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); 238 } 239 exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); 240 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 241 242 /* Initialize board IRQs. */ 243 exynos4210_init_board_irqs(&s->irqs); 244 245 /*** Memory ***/ 246 247 /* Chip-ID and OMR */ 248 memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops, 249 NULL, "exynos4210.chipid", sizeof(chipid_and_omr)); 250 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 251 &s->chipid_mem); 252 253 /* Internal ROM */ 254 memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom", 255 EXYNOS4210_IROM_SIZE, &error_fatal); 256 vmstate_register_ram_global(&s->irom_mem); 257 memory_region_set_readonly(&s->irom_mem, true); 258 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 259 &s->irom_mem); 260 /* mirror of iROM */ 261 memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias", 262 &s->irom_mem, 263 0, 264 EXYNOS4210_IROM_SIZE); 265 memory_region_set_readonly(&s->irom_alias_mem, true); 266 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 267 &s->irom_alias_mem); 268 269 /* Internal RAM */ 270 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 271 EXYNOS4210_IRAM_SIZE, &error_fatal); 272 vmstate_register_ram_global(&s->iram_mem); 273 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 274 &s->iram_mem); 275 276 /* DRAM */ 277 mem_size = ram_size; 278 if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { 279 memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", 280 mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal); 281 vmstate_register_ram_global(&s->dram1_mem); 282 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, 283 &s->dram1_mem); 284 mem_size = EXYNOS4210_DRAM_MAX_SIZE; 285 } 286 memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, 287 &error_fatal); 288 vmstate_register_ram_global(&s->dram0_mem); 289 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, 290 &s->dram0_mem); 291 292 /* PMU. 293 * The only reason of existence at the moment is that secondary CPU boot 294 * loader uses PMU INFORM5 register as a holding pen. 295 */ 296 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 297 298 /* PWM */ 299 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 300 s->irq_table[exynos4210_get_irq(22, 0)], 301 s->irq_table[exynos4210_get_irq(22, 1)], 302 s->irq_table[exynos4210_get_irq(22, 2)], 303 s->irq_table[exynos4210_get_irq(22, 3)], 304 s->irq_table[exynos4210_get_irq(22, 4)], 305 NULL); 306 /* RTC */ 307 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 308 s->irq_table[exynos4210_get_irq(23, 0)], 309 s->irq_table[exynos4210_get_irq(23, 1)], 310 NULL); 311 312 /* Multi Core Timer */ 313 dev = qdev_create(NULL, "exynos4210.mct"); 314 qdev_init_nofail(dev); 315 busdev = SYS_BUS_DEVICE(dev); 316 for (n = 0; n < 4; n++) { 317 /* Connect global timer interrupts to Combiner gpio_in */ 318 sysbus_connect_irq(busdev, n, 319 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 320 } 321 /* Connect local timer interrupts to Combiner gpio_in */ 322 sysbus_connect_irq(busdev, 4, 323 s->irq_table[exynos4210_get_irq(51, 0)]); 324 sysbus_connect_irq(busdev, 5, 325 s->irq_table[exynos4210_get_irq(35, 3)]); 326 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 327 328 /*** I2C ***/ 329 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 330 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 331 qemu_irq i2c_irq; 332 333 if (n < 8) { 334 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 335 } else { 336 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 337 } 338 339 dev = qdev_create(NULL, "exynos4210.i2c"); 340 qdev_init_nofail(dev); 341 busdev = SYS_BUS_DEVICE(dev); 342 sysbus_connect_irq(busdev, 0, i2c_irq); 343 sysbus_mmio_map(busdev, 0, addr); 344 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 345 } 346 347 348 /*** UARTs ***/ 349 exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 350 EXYNOS4210_UART0_FIFO_SIZE, 0, NULL, 351 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 352 353 exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 354 EXYNOS4210_UART1_FIFO_SIZE, 1, NULL, 355 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 356 357 exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 358 EXYNOS4210_UART2_FIFO_SIZE, 2, NULL, 359 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 360 361 exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 362 EXYNOS4210_UART3_FIFO_SIZE, 3, NULL, 363 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 364 365 /*** Display controller (FIMD) ***/ 366 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 367 s->irq_table[exynos4210_get_irq(11, 0)], 368 s->irq_table[exynos4210_get_irq(11, 1)], 369 s->irq_table[exynos4210_get_irq(11, 2)], 370 NULL); 371 372 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 373 s->irq_table[exynos4210_get_irq(28, 3)]); 374 375 return s; 376 } 377