1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "hw/boards.h" 25 #include "sysemu/sysemu.h" 26 #include "hw/sysbus.h" 27 #include "hw/arm/arm.h" 28 #include "hw/loader.h" 29 #include "hw/arm/exynos4210.h" 30 #include "hw/usb/hcd-ehci.h" 31 32 #define EXYNOS4210_CHIPID_ADDR 0x10000000 33 34 /* PWM */ 35 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 36 37 /* RTC */ 38 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 39 40 /* MCT */ 41 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 42 43 /* I2C */ 44 #define EXYNOS4210_I2C_SHIFT 0x00010000 45 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 46 /* Interrupt Group of External Interrupt Combiner for I2C */ 47 #define EXYNOS4210_I2C_INTG 27 48 #define EXYNOS4210_HDMI_INTG 16 49 50 /* UART's definitions */ 51 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 52 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 53 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 54 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 55 #define EXYNOS4210_UART0_FIFO_SIZE 256 56 #define EXYNOS4210_UART1_FIFO_SIZE 64 57 #define EXYNOS4210_UART2_FIFO_SIZE 16 58 #define EXYNOS4210_UART3_FIFO_SIZE 16 59 /* Interrupt Group of External Interrupt Combiner for UART */ 60 #define EXYNOS4210_UART_INT_GRP 26 61 62 /* External GIC */ 63 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 64 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 65 66 /* Combiner */ 67 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 68 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 69 70 /* PMU SFR base address */ 71 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 72 73 /* Display controllers (FIMD) */ 74 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 75 76 /* EHCI */ 77 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 78 79 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 80 0x09, 0x00, 0x00, 0x00 }; 81 82 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 83 unsigned size) 84 { 85 assert(offset < sizeof(chipid_and_omr)); 86 return chipid_and_omr[offset]; 87 } 88 89 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 90 uint64_t value, unsigned size) 91 { 92 return; 93 } 94 95 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 96 .read = exynos4210_chipid_and_omr_read, 97 .write = exynos4210_chipid_and_omr_write, 98 .endianness = DEVICE_NATIVE_ENDIAN, 99 .impl = { 100 .max_access_size = 1, 101 } 102 }; 103 104 void exynos4210_write_secondary(ARMCPU *cpu, 105 const struct arm_boot_info *info) 106 { 107 int n; 108 uint32_t smpboot[] = { 109 0xe59f3034, /* ldr r3, External gic_cpu_if */ 110 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 111 0xe59f0034, /* ldr r0, startaddr */ 112 0xe3a01001, /* mov r1, #1 */ 113 0xe5821000, /* str r1, [r2] */ 114 0xe5831000, /* str r1, [r3] */ 115 0xe3a010ff, /* mov r1, #0xff */ 116 0xe5821004, /* str r1, [r2, #4] */ 117 0xe5831004, /* str r1, [r3, #4] */ 118 0xf57ff04f, /* dsb */ 119 0xe320f003, /* wfi */ 120 0xe5901000, /* ldr r1, [r0] */ 121 0xe1110001, /* tst r1, r1 */ 122 0x0afffffb, /* beq <wfi> */ 123 0xe12fff11, /* bx r1 */ 124 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 125 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 126 0 /* bootreg: Boot register address is held here */ 127 }; 128 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 129 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 130 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 131 smpboot[n] = tswap32(smpboot[n]); 132 } 133 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 134 info->smp_loader_start); 135 } 136 137 Exynos4210State *exynos4210_init(MemoryRegion *system_mem, 138 unsigned long ram_size) 139 { 140 int i, n; 141 Exynos4210State *s = g_new(Exynos4210State, 1); 142 qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; 143 unsigned long mem_size; 144 DeviceState *dev; 145 SysBusDevice *busdev; 146 147 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 148 s->cpu[n] = cpu_arm_init("cortex-a9"); 149 if (!s->cpu[n]) { 150 fprintf(stderr, "Unable to find CPU %d definition\n", n); 151 exit(1); 152 } 153 } 154 155 /*** IRQs ***/ 156 157 s->irq_table = exynos4210_init_irq(&s->irqs); 158 159 /* IRQ Gate */ 160 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 161 dev = qdev_create(NULL, "exynos4210.irq_gate"); 162 qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); 163 qdev_init_nofail(dev); 164 /* Get IRQ Gate input in gate_irq */ 165 for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { 166 gate_irq[i][n] = qdev_get_gpio_in(dev, n); 167 } 168 busdev = SYS_BUS_DEVICE(dev); 169 170 /* Connect IRQ Gate output to CPU's IRQ line */ 171 sysbus_connect_irq(busdev, 0, 172 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 173 } 174 175 /* Private memory region and Internal GIC */ 176 dev = qdev_create(NULL, "a9mpcore_priv"); 177 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 178 qdev_init_nofail(dev); 179 busdev = SYS_BUS_DEVICE(dev); 180 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 181 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 182 sysbus_connect_irq(busdev, n, gate_irq[n][0]); 183 } 184 for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { 185 s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); 186 } 187 188 /* Cache controller */ 189 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 190 191 /* External GIC */ 192 dev = qdev_create(NULL, "exynos4210.gic"); 193 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 194 qdev_init_nofail(dev); 195 busdev = SYS_BUS_DEVICE(dev); 196 /* Map CPU interface */ 197 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 198 /* Map Distributer interface */ 199 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 200 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 201 sysbus_connect_irq(busdev, n, gate_irq[n][1]); 202 } 203 for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { 204 s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); 205 } 206 207 /* Internal Interrupt Combiner */ 208 dev = qdev_create(NULL, "exynos4210.combiner"); 209 qdev_init_nofail(dev); 210 busdev = SYS_BUS_DEVICE(dev); 211 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 212 sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); 213 } 214 exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); 215 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 216 217 /* External Interrupt Combiner */ 218 dev = qdev_create(NULL, "exynos4210.combiner"); 219 qdev_prop_set_uint32(dev, "external", 1); 220 qdev_init_nofail(dev); 221 busdev = SYS_BUS_DEVICE(dev); 222 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 223 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); 224 } 225 exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); 226 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 227 228 /* Initialize board IRQs. */ 229 exynos4210_init_board_irqs(&s->irqs); 230 231 /*** Memory ***/ 232 233 /* Chip-ID and OMR */ 234 memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops, 235 NULL, "exynos4210.chipid", sizeof(chipid_and_omr)); 236 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 237 &s->chipid_mem); 238 239 /* Internal ROM */ 240 memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom", 241 EXYNOS4210_IROM_SIZE); 242 vmstate_register_ram_global(&s->irom_mem); 243 memory_region_set_readonly(&s->irom_mem, true); 244 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 245 &s->irom_mem); 246 /* mirror of iROM */ 247 memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias", 248 &s->irom_mem, 249 0, 250 EXYNOS4210_IROM_SIZE); 251 memory_region_set_readonly(&s->irom_alias_mem, true); 252 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 253 &s->irom_alias_mem); 254 255 /* Internal RAM */ 256 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 257 EXYNOS4210_IRAM_SIZE); 258 vmstate_register_ram_global(&s->iram_mem); 259 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 260 &s->iram_mem); 261 262 /* DRAM */ 263 mem_size = ram_size; 264 if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { 265 memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", 266 mem_size - EXYNOS4210_DRAM_MAX_SIZE); 267 vmstate_register_ram_global(&s->dram1_mem); 268 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, 269 &s->dram1_mem); 270 mem_size = EXYNOS4210_DRAM_MAX_SIZE; 271 } 272 memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size); 273 vmstate_register_ram_global(&s->dram0_mem); 274 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, 275 &s->dram0_mem); 276 277 /* PMU. 278 * The only reason of existence at the moment is that secondary CPU boot 279 * loader uses PMU INFORM5 register as a holding pen. 280 */ 281 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 282 283 /* PWM */ 284 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 285 s->irq_table[exynos4210_get_irq(22, 0)], 286 s->irq_table[exynos4210_get_irq(22, 1)], 287 s->irq_table[exynos4210_get_irq(22, 2)], 288 s->irq_table[exynos4210_get_irq(22, 3)], 289 s->irq_table[exynos4210_get_irq(22, 4)], 290 NULL); 291 /* RTC */ 292 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 293 s->irq_table[exynos4210_get_irq(23, 0)], 294 s->irq_table[exynos4210_get_irq(23, 1)], 295 NULL); 296 297 /* Multi Core Timer */ 298 dev = qdev_create(NULL, "exynos4210.mct"); 299 qdev_init_nofail(dev); 300 busdev = SYS_BUS_DEVICE(dev); 301 for (n = 0; n < 4; n++) { 302 /* Connect global timer interrupts to Combiner gpio_in */ 303 sysbus_connect_irq(busdev, n, 304 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 305 } 306 /* Connect local timer interrupts to Combiner gpio_in */ 307 sysbus_connect_irq(busdev, 4, 308 s->irq_table[exynos4210_get_irq(51, 0)]); 309 sysbus_connect_irq(busdev, 5, 310 s->irq_table[exynos4210_get_irq(35, 3)]); 311 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 312 313 /*** I2C ***/ 314 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 315 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 316 qemu_irq i2c_irq; 317 318 if (n < 8) { 319 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 320 } else { 321 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 322 } 323 324 dev = qdev_create(NULL, "exynos4210.i2c"); 325 qdev_init_nofail(dev); 326 busdev = SYS_BUS_DEVICE(dev); 327 sysbus_connect_irq(busdev, 0, i2c_irq); 328 sysbus_mmio_map(busdev, 0, addr); 329 s->i2c_if[n] = (i2c_bus *)qdev_get_child_bus(dev, "i2c"); 330 } 331 332 333 /*** UARTs ***/ 334 exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 335 EXYNOS4210_UART0_FIFO_SIZE, 0, NULL, 336 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 337 338 exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 339 EXYNOS4210_UART1_FIFO_SIZE, 1, NULL, 340 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 341 342 exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 343 EXYNOS4210_UART2_FIFO_SIZE, 2, NULL, 344 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 345 346 exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 347 EXYNOS4210_UART3_FIFO_SIZE, 3, NULL, 348 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 349 350 /*** Display controller (FIMD) ***/ 351 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 352 s->irq_table[exynos4210_get_irq(11, 0)], 353 s->irq_table[exynos4210_get_irq(11, 1)], 354 s->irq_table[exynos4210_get_irq(11, 2)], 355 NULL); 356 357 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 358 s->irq_table[exynos4210_get_irq(28, 3)]); 359 360 return s; 361 } 362