1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu/log.h" 27 #include "cpu.h" 28 #include "hw/cpu/a9mpcore.h" 29 #include "hw/irq.h" 30 #include "sysemu/blockdev.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/sysbus.h" 33 #include "hw/arm/boot.h" 34 #include "hw/loader.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/arm/exynos4210.h" 37 #include "hw/sd/sdhci.h" 38 #include "hw/usb/hcd-ehci.h" 39 40 #define EXYNOS4210_CHIPID_ADDR 0x10000000 41 42 /* PWM */ 43 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 44 45 /* RTC */ 46 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 47 48 /* MCT */ 49 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 50 51 /* I2C */ 52 #define EXYNOS4210_I2C_SHIFT 0x00010000 53 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 54 /* Interrupt Group of External Interrupt Combiner for I2C */ 55 #define EXYNOS4210_I2C_INTG 27 56 #define EXYNOS4210_HDMI_INTG 16 57 58 /* UART's definitions */ 59 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 60 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 61 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 62 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 63 #define EXYNOS4210_UART0_FIFO_SIZE 256 64 #define EXYNOS4210_UART1_FIFO_SIZE 64 65 #define EXYNOS4210_UART2_FIFO_SIZE 16 66 #define EXYNOS4210_UART3_FIFO_SIZE 16 67 /* Interrupt Group of External Interrupt Combiner for UART */ 68 #define EXYNOS4210_UART_INT_GRP 26 69 70 /* External GIC */ 71 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 72 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 73 74 /* Combiner */ 75 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 76 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 77 78 /* SD/MMC host controllers */ 79 #define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 80 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 81 #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ 82 0x00010000 * (n)) 83 #define EXYNOS4210_SDHCI_NUMBER 4 84 85 /* PMU SFR base address */ 86 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 87 88 /* Clock controller SFR base address */ 89 #define EXYNOS4210_CLK_BASE_ADDR 0x10030000 90 91 /* PRNG/HASH SFR base address */ 92 #define EXYNOS4210_RNG_BASE_ADDR 0x10830400 93 94 /* Display controllers (FIMD) */ 95 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 96 97 /* EHCI */ 98 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 99 100 /* DMA */ 101 #define EXYNOS4210_PL330_BASE0_ADDR 0x12680000 102 #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 103 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 104 105 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 106 0x09, 0x00, 0x00, 0x00 }; 107 108 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 109 unsigned size) 110 { 111 assert(offset < sizeof(chipid_and_omr)); 112 return chipid_and_omr[offset]; 113 } 114 115 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 116 uint64_t value, unsigned size) 117 { 118 return; 119 } 120 121 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 122 .read = exynos4210_chipid_and_omr_read, 123 .write = exynos4210_chipid_and_omr_write, 124 .endianness = DEVICE_NATIVE_ENDIAN, 125 .impl = { 126 .max_access_size = 1, 127 } 128 }; 129 130 void exynos4210_write_secondary(ARMCPU *cpu, 131 const struct arm_boot_info *info) 132 { 133 int n; 134 uint32_t smpboot[] = { 135 0xe59f3034, /* ldr r3, External gic_cpu_if */ 136 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 137 0xe59f0034, /* ldr r0, startaddr */ 138 0xe3a01001, /* mov r1, #1 */ 139 0xe5821000, /* str r1, [r2] */ 140 0xe5831000, /* str r1, [r3] */ 141 0xe3a010ff, /* mov r1, #0xff */ 142 0xe5821004, /* str r1, [r2, #4] */ 143 0xe5831004, /* str r1, [r3, #4] */ 144 0xf57ff04f, /* dsb */ 145 0xe320f003, /* wfi */ 146 0xe5901000, /* ldr r1, [r0] */ 147 0xe1110001, /* tst r1, r1 */ 148 0x0afffffb, /* beq <wfi> */ 149 0xe12fff11, /* bx r1 */ 150 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 151 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 152 0 /* bootreg: Boot register address is held here */ 153 }; 154 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 155 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 156 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 157 smpboot[n] = tswap32(smpboot[n]); 158 } 159 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 160 info->smp_loader_start); 161 } 162 163 static uint64_t exynos4210_calc_affinity(int cpu) 164 { 165 /* Exynos4210 has 0x9 as cluster ID */ 166 return (0x9 << ARM_AFF1_SHIFT) | cpu; 167 } 168 169 static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate, 170 qemu_irq irq, int nreq, int nevents, int width) 171 { 172 SysBusDevice *busdev; 173 DeviceState *dev; 174 int i; 175 176 dev = qdev_create(NULL, "pl330"); 177 qdev_prop_set_uint8(dev, "num_events", nevents); 178 qdev_prop_set_uint8(dev, "num_chnls", 8); 179 qdev_prop_set_uint8(dev, "num_periph_req", nreq); 180 181 qdev_prop_set_uint8(dev, "wr_cap", 4); 182 qdev_prop_set_uint8(dev, "wr_q_dep", 8); 183 qdev_prop_set_uint8(dev, "rd_cap", 4); 184 qdev_prop_set_uint8(dev, "rd_q_dep", 8); 185 qdev_prop_set_uint8(dev, "data_width", width); 186 qdev_prop_set_uint16(dev, "data_buffer_dep", width); 187 qdev_init_nofail(dev); 188 busdev = SYS_BUS_DEVICE(dev); 189 sysbus_mmio_map(busdev, 0, base); 190 191 object_property_set_int(OBJECT(orgate), nevents + 1, "num-lines", 192 &error_abort); 193 object_property_set_bool(OBJECT(orgate), true, "realized", &error_abort); 194 195 for (i = 0; i < nevents + 1; i++) { 196 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i)); 197 } 198 qdev_connect_gpio_out(DEVICE(orgate), 0, irq); 199 return dev; 200 } 201 202 static void exynos4210_realize(DeviceState *socdev, Error **errp) 203 { 204 Exynos4210State *s = EXYNOS4210_SOC(socdev); 205 MemoryRegion *system_mem = get_system_memory(); 206 qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; 207 SysBusDevice *busdev; 208 DeviceState *dev, *uart[4], *pl330[3]; 209 int i, n; 210 211 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 212 Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); 213 214 /* By default A9 CPUs have EL3 enabled. This board does not currently 215 * support EL3 so the CPU EL3 property is disabled before realization. 216 */ 217 if (object_property_find(cpuobj, "has_el3", NULL)) { 218 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 219 } 220 221 s->cpu[n] = ARM_CPU(cpuobj); 222 object_property_set_int(cpuobj, exynos4210_calc_affinity(n), 223 "mp-affinity", &error_abort); 224 object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 225 "reset-cbar", &error_abort); 226 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 227 } 228 229 /*** IRQs ***/ 230 231 s->irq_table = exynos4210_init_irq(&s->irqs); 232 233 /* IRQ Gate */ 234 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 235 dev = qdev_create(NULL, "exynos4210.irq_gate"); 236 qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); 237 qdev_init_nofail(dev); 238 /* Get IRQ Gate input in gate_irq */ 239 for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { 240 gate_irq[i][n] = qdev_get_gpio_in(dev, n); 241 } 242 busdev = SYS_BUS_DEVICE(dev); 243 244 /* Connect IRQ Gate output to CPU's IRQ line */ 245 sysbus_connect_irq(busdev, 0, 246 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 247 } 248 249 /* Private memory region and Internal GIC */ 250 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); 251 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 252 qdev_init_nofail(dev); 253 busdev = SYS_BUS_DEVICE(dev); 254 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 255 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 256 sysbus_connect_irq(busdev, n, gate_irq[n][0]); 257 } 258 for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { 259 s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); 260 } 261 262 /* Cache controller */ 263 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 264 265 /* External GIC */ 266 dev = qdev_create(NULL, "exynos4210.gic"); 267 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 268 qdev_init_nofail(dev); 269 busdev = SYS_BUS_DEVICE(dev); 270 /* Map CPU interface */ 271 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 272 /* Map Distributer interface */ 273 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 274 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 275 sysbus_connect_irq(busdev, n, gate_irq[n][1]); 276 } 277 for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { 278 s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); 279 } 280 281 /* Internal Interrupt Combiner */ 282 dev = qdev_create(NULL, "exynos4210.combiner"); 283 qdev_init_nofail(dev); 284 busdev = SYS_BUS_DEVICE(dev); 285 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 286 sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); 287 } 288 exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); 289 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 290 291 /* External Interrupt Combiner */ 292 dev = qdev_create(NULL, "exynos4210.combiner"); 293 qdev_prop_set_uint32(dev, "external", 1); 294 qdev_init_nofail(dev); 295 busdev = SYS_BUS_DEVICE(dev); 296 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 297 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); 298 } 299 exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); 300 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 301 302 /* Initialize board IRQs. */ 303 exynos4210_init_board_irqs(&s->irqs); 304 305 /*** Memory ***/ 306 307 /* Chip-ID and OMR */ 308 memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops, 309 NULL, "exynos4210.chipid", sizeof(chipid_and_omr)); 310 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 311 &s->chipid_mem); 312 313 /* Internal ROM */ 314 memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom", 315 EXYNOS4210_IROM_SIZE, &error_fatal); 316 memory_region_set_readonly(&s->irom_mem, true); 317 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 318 &s->irom_mem); 319 /* mirror of iROM */ 320 memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias", 321 &s->irom_mem, 322 0, 323 EXYNOS4210_IROM_SIZE); 324 memory_region_set_readonly(&s->irom_alias_mem, true); 325 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 326 &s->irom_alias_mem); 327 328 /* Internal RAM */ 329 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 330 EXYNOS4210_IRAM_SIZE, &error_fatal); 331 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 332 &s->iram_mem); 333 334 /* PMU. 335 * The only reason of existence at the moment is that secondary CPU boot 336 * loader uses PMU INFORM5 register as a holding pen. 337 */ 338 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 339 340 sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL); 341 sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL); 342 343 /* PWM */ 344 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 345 s->irq_table[exynos4210_get_irq(22, 0)], 346 s->irq_table[exynos4210_get_irq(22, 1)], 347 s->irq_table[exynos4210_get_irq(22, 2)], 348 s->irq_table[exynos4210_get_irq(22, 3)], 349 s->irq_table[exynos4210_get_irq(22, 4)], 350 NULL); 351 /* RTC */ 352 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 353 s->irq_table[exynos4210_get_irq(23, 0)], 354 s->irq_table[exynos4210_get_irq(23, 1)], 355 NULL); 356 357 /* Multi Core Timer */ 358 dev = qdev_create(NULL, "exynos4210.mct"); 359 qdev_init_nofail(dev); 360 busdev = SYS_BUS_DEVICE(dev); 361 for (n = 0; n < 4; n++) { 362 /* Connect global timer interrupts to Combiner gpio_in */ 363 sysbus_connect_irq(busdev, n, 364 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 365 } 366 /* Connect local timer interrupts to Combiner gpio_in */ 367 sysbus_connect_irq(busdev, 4, 368 s->irq_table[exynos4210_get_irq(51, 0)]); 369 sysbus_connect_irq(busdev, 5, 370 s->irq_table[exynos4210_get_irq(35, 3)]); 371 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 372 373 /*** I2C ***/ 374 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 375 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 376 qemu_irq i2c_irq; 377 378 if (n < 8) { 379 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 380 } else { 381 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 382 } 383 384 dev = qdev_create(NULL, "exynos4210.i2c"); 385 qdev_init_nofail(dev); 386 busdev = SYS_BUS_DEVICE(dev); 387 sysbus_connect_irq(busdev, 0, i2c_irq); 388 sysbus_mmio_map(busdev, 0, addr); 389 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 390 } 391 392 393 /*** UARTs ***/ 394 uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 395 EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0), 396 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 397 398 uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 399 EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1), 400 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 401 402 uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 403 EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2), 404 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 405 406 uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 407 EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3), 408 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 409 410 /*** SD/MMC host controllers ***/ 411 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { 412 DeviceState *carddev; 413 BlockBackend *blk; 414 DriveInfo *di; 415 416 /* Compatible with: 417 * - SD Host Controller Specification Version 2.0 418 * - SDIO Specification Version 2.0 419 * - MMC Specification Version 4.3 420 * - SDMA 421 * - ADMA2 422 * 423 * As this part of the Exynos4210 is not publically available, 424 * we used the "HS-MMC Controller S3C2416X RISC Microprocessor" 425 * public datasheet which is very similar (implementing 426 * MMC Specification Version 4.0 being the only difference noted) 427 */ 428 dev = qdev_create(NULL, TYPE_S3C_SDHCI); 429 qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); 430 qdev_init_nofail(dev); 431 432 busdev = SYS_BUS_DEVICE(dev); 433 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); 434 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); 435 436 di = drive_get(IF_SD, 0, n); 437 blk = di ? blk_by_legacy_dinfo(di) : NULL; 438 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 439 qdev_prop_set_drive(carddev, "drive", blk, &error_abort); 440 qdev_init_nofail(carddev); 441 } 442 443 /*** Display controller (FIMD) ***/ 444 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 445 s->irq_table[exynos4210_get_irq(11, 0)], 446 s->irq_table[exynos4210_get_irq(11, 1)], 447 s->irq_table[exynos4210_get_irq(11, 2)], 448 NULL); 449 450 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 451 s->irq_table[exynos4210_get_irq(28, 3)]); 452 453 /*** DMA controllers ***/ 454 pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR, 455 &s->pl330_irq_orgate[0], 456 s->irq_table[exynos4210_get_irq(21, 0)], 457 32, 32, 32); 458 pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR, 459 &s->pl330_irq_orgate[1], 460 s->irq_table[exynos4210_get_irq(21, 1)], 461 32, 32, 32); 462 pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR, 463 &s->pl330_irq_orgate[2], 464 s->irq_table[exynos4210_get_irq(20, 1)], 465 1, 31, 64); 466 467 sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1, 468 qdev_get_gpio_in(pl330[0], 15)); 469 sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1, 470 qdev_get_gpio_in(pl330[1], 15)); 471 sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1, 472 qdev_get_gpio_in(pl330[0], 17)); 473 sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1, 474 qdev_get_gpio_in(pl330[1], 17)); 475 } 476 477 static void exynos4210_init(Object *obj) 478 { 479 Exynos4210State *s = EXYNOS4210_SOC(obj); 480 int i; 481 482 for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { 483 char *name = g_strdup_printf("pl330-irq-orgate%d", i); 484 qemu_or_irq *orgate = &s->pl330_irq_orgate[i]; 485 486 object_initialize_child(obj, name, orgate, sizeof(*orgate), 487 TYPE_OR_IRQ, &error_abort, NULL); 488 g_free(name); 489 } 490 } 491 492 static void exynos4210_class_init(ObjectClass *klass, void *data) 493 { 494 DeviceClass *dc = DEVICE_CLASS(klass); 495 496 dc->realize = exynos4210_realize; 497 } 498 499 static const TypeInfo exynos4210_info = { 500 .name = TYPE_EXYNOS4210_SOC, 501 .parent = TYPE_SYS_BUS_DEVICE, 502 .instance_size = sizeof(Exynos4210State), 503 .instance_init = exynos4210_init, 504 .class_init = exynos4210_class_init, 505 }; 506 507 static void exynos4210_register_types(void) 508 { 509 type_register_static(&exynos4210_info); 510 } 511 512 type_init(exynos4210_register_types) 513