1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "hw/cpu/a9mpcore.h" 28 #include "hw/irq.h" 29 #include "sysemu/blockdev.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/sysbus.h" 32 #include "hw/arm/boot.h" 33 #include "hw/loader.h" 34 #include "hw/qdev-properties.h" 35 #include "hw/arm/exynos4210.h" 36 #include "hw/sd/sdhci.h" 37 #include "hw/usb/hcd-ehci.h" 38 39 #define EXYNOS4210_CHIPID_ADDR 0x10000000 40 41 /* PWM */ 42 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 43 44 /* RTC */ 45 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 46 47 /* MCT */ 48 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 49 50 /* I2C */ 51 #define EXYNOS4210_I2C_SHIFT 0x00010000 52 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 53 /* Interrupt Group of External Interrupt Combiner for I2C */ 54 #define EXYNOS4210_I2C_INTG 27 55 #define EXYNOS4210_HDMI_INTG 16 56 57 /* UART's definitions */ 58 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 59 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 60 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 61 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 62 #define EXYNOS4210_UART0_FIFO_SIZE 256 63 #define EXYNOS4210_UART1_FIFO_SIZE 64 64 #define EXYNOS4210_UART2_FIFO_SIZE 16 65 #define EXYNOS4210_UART3_FIFO_SIZE 16 66 /* Interrupt Group of External Interrupt Combiner for UART */ 67 #define EXYNOS4210_UART_INT_GRP 26 68 69 /* External GIC */ 70 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 71 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 72 73 /* Combiner */ 74 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 75 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 76 77 /* SD/MMC host controllers */ 78 #define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 79 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 80 #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ 81 0x00010000 * (n)) 82 #define EXYNOS4210_SDHCI_NUMBER 4 83 84 /* PMU SFR base address */ 85 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 86 87 /* Clock controller SFR base address */ 88 #define EXYNOS4210_CLK_BASE_ADDR 0x10030000 89 90 /* PRNG/HASH SFR base address */ 91 #define EXYNOS4210_RNG_BASE_ADDR 0x10830400 92 93 /* Display controllers (FIMD) */ 94 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 95 96 /* EHCI */ 97 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 98 99 /* DMA */ 100 #define EXYNOS4210_PL330_BASE0_ADDR 0x12680000 101 #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 102 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 103 104 enum ExtGicId { 105 EXT_GIC_ID_MDMA_LCD0 = 66, 106 EXT_GIC_ID_PDMA0, 107 EXT_GIC_ID_PDMA1, 108 EXT_GIC_ID_TIMER0, 109 EXT_GIC_ID_TIMER1, 110 EXT_GIC_ID_TIMER2, 111 EXT_GIC_ID_TIMER3, 112 EXT_GIC_ID_TIMER4, 113 EXT_GIC_ID_MCT_L0, 114 EXT_GIC_ID_WDT, 115 EXT_GIC_ID_RTC_ALARM, 116 EXT_GIC_ID_RTC_TIC, 117 EXT_GIC_ID_GPIO_XB, 118 EXT_GIC_ID_GPIO_XA, 119 EXT_GIC_ID_MCT_L1, 120 EXT_GIC_ID_IEM_APC, 121 EXT_GIC_ID_IEM_IEC, 122 EXT_GIC_ID_NFC, 123 EXT_GIC_ID_UART0, 124 EXT_GIC_ID_UART1, 125 EXT_GIC_ID_UART2, 126 EXT_GIC_ID_UART3, 127 EXT_GIC_ID_UART4, 128 EXT_GIC_ID_MCT_G0, 129 EXT_GIC_ID_I2C0, 130 EXT_GIC_ID_I2C1, 131 EXT_GIC_ID_I2C2, 132 EXT_GIC_ID_I2C3, 133 EXT_GIC_ID_I2C4, 134 EXT_GIC_ID_I2C5, 135 EXT_GIC_ID_I2C6, 136 EXT_GIC_ID_I2C7, 137 EXT_GIC_ID_SPI0, 138 EXT_GIC_ID_SPI1, 139 EXT_GIC_ID_SPI2, 140 EXT_GIC_ID_MCT_G1, 141 EXT_GIC_ID_USB_HOST, 142 EXT_GIC_ID_USB_DEVICE, 143 EXT_GIC_ID_MODEMIF, 144 EXT_GIC_ID_HSMMC0, 145 EXT_GIC_ID_HSMMC1, 146 EXT_GIC_ID_HSMMC2, 147 EXT_GIC_ID_HSMMC3, 148 EXT_GIC_ID_SDMMC, 149 EXT_GIC_ID_MIPI_CSI_4LANE, 150 EXT_GIC_ID_MIPI_DSI_4LANE, 151 EXT_GIC_ID_MIPI_CSI_2LANE, 152 EXT_GIC_ID_MIPI_DSI_2LANE, 153 EXT_GIC_ID_ONENAND_AUDI, 154 EXT_GIC_ID_ROTATOR, 155 EXT_GIC_ID_FIMC0, 156 EXT_GIC_ID_FIMC1, 157 EXT_GIC_ID_FIMC2, 158 EXT_GIC_ID_FIMC3, 159 EXT_GIC_ID_JPEG, 160 EXT_GIC_ID_2D, 161 EXT_GIC_ID_PCIe, 162 EXT_GIC_ID_MIXER, 163 EXT_GIC_ID_HDMI, 164 EXT_GIC_ID_HDMI_I2C, 165 EXT_GIC_ID_MFC, 166 EXT_GIC_ID_TVENC, 167 }; 168 169 enum ExtInt { 170 EXT_GIC_ID_EXTINT0 = 48, 171 EXT_GIC_ID_EXTINT1, 172 EXT_GIC_ID_EXTINT2, 173 EXT_GIC_ID_EXTINT3, 174 EXT_GIC_ID_EXTINT4, 175 EXT_GIC_ID_EXTINT5, 176 EXT_GIC_ID_EXTINT6, 177 EXT_GIC_ID_EXTINT7, 178 EXT_GIC_ID_EXTINT8, 179 EXT_GIC_ID_EXTINT9, 180 EXT_GIC_ID_EXTINT10, 181 EXT_GIC_ID_EXTINT11, 182 EXT_GIC_ID_EXTINT12, 183 EXT_GIC_ID_EXTINT13, 184 EXT_GIC_ID_EXTINT14, 185 EXT_GIC_ID_EXTINT15 186 }; 187 188 /* 189 * External GIC sources which are not from External Interrupt Combiner or 190 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, 191 * which is INTG16 in Internal Interrupt Combiner. 192 */ 193 194 static const uint32_t 195 combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { 196 /* int combiner groups 16-19 */ 197 { }, { }, { }, { }, 198 /* int combiner group 20 */ 199 { 0, EXT_GIC_ID_MDMA_LCD0 }, 200 /* int combiner group 21 */ 201 { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, 202 /* int combiner group 22 */ 203 { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, 204 EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, 205 /* int combiner group 23 */ 206 { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, 207 /* int combiner group 24 */ 208 { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, 209 /* int combiner group 25 */ 210 { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, 211 /* int combiner group 26 */ 212 { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, 213 EXT_GIC_ID_UART4 }, 214 /* int combiner group 27 */ 215 { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, 216 EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, 217 EXT_GIC_ID_I2C7 }, 218 /* int combiner group 28 */ 219 { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, 220 /* int combiner group 29 */ 221 { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, 222 EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, 223 /* int combiner group 30 */ 224 { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, 225 /* int combiner group 31 */ 226 { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, 227 /* int combiner group 32 */ 228 { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, 229 /* int combiner group 33 */ 230 { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, 231 /* int combiner group 34 */ 232 { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, 233 /* int combiner group 35 */ 234 { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 235 /* int combiner group 36 */ 236 { EXT_GIC_ID_MIXER }, 237 /* int combiner group 37 */ 238 { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, 239 EXT_GIC_ID_EXTINT7 }, 240 /* groups 38-50 */ 241 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, 242 /* int combiner group 51 */ 243 { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 244 /* group 52 */ 245 { }, 246 /* int combiner group 53 */ 247 { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, 248 /* groups 54-63 */ 249 { }, { }, { }, { }, { }, { }, { }, { }, { }, { } 250 }; 251 252 #define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit)) 253 #define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) 254 #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ 255 ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) 256 257 /* 258 * Initialize board IRQs. 259 * These IRQs contain splitted Int/External Combiner and External Gic IRQs. 260 */ 261 static void exynos4210_init_board_irqs(Exynos4210State *s) 262 { 263 uint32_t grp, bit, irq_id, n; 264 Exynos4210Irq *is = &s->irqs; 265 DeviceState *extgicdev = DEVICE(&s->ext_gic); 266 267 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { 268 irq_id = 0; 269 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || 270 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { 271 /* MCT_G0 is passed to External GIC */ 272 irq_id = EXT_GIC_ID_MCT_G0; 273 } 274 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || 275 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { 276 /* MCT_G1 is passed to External and GIC */ 277 irq_id = EXT_GIC_ID_MCT_G1; 278 } 279 if (irq_id) { 280 s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], 281 qdev_get_gpio_in(extgicdev, 282 irq_id - 32)); 283 } else { 284 s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], 285 is->ext_combiner_irq[n]); 286 } 287 } 288 for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { 289 /* these IDs are passed to Internal Combiner and External GIC */ 290 grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); 291 bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); 292 irq_id = combiner_grp_to_gic_id[grp - 293 EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; 294 295 if (irq_id) { 296 s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], 297 qdev_get_gpio_in(extgicdev, 298 irq_id - 32)); 299 } 300 } 301 } 302 303 /* 304 * Get IRQ number from exynos4210 IRQ subsystem stub. 305 * To identify IRQ source use internal combiner group and bit number 306 * grp - group number 307 * bit - bit number inside group 308 */ 309 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) 310 { 311 return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); 312 } 313 314 /* 315 * Get Combiner input GPIO into irqs structure 316 */ 317 static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, 318 DeviceState *dev, int ext) 319 { 320 int n; 321 int bit; 322 int max; 323 qemu_irq *irq; 324 325 max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : 326 EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; 327 irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; 328 329 /* 330 * Some IRQs of Int/External Combiner are going to two Combiners groups, 331 * so let split them. 332 */ 333 for (n = 0; n < max; n++) { 334 335 bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); 336 337 switch (n) { 338 /* MDNIE_LCD1 INTG1 */ 339 case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... 340 EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): 341 irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), 342 irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); 343 continue; 344 345 /* TMU INTG3 */ 346 case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): 347 irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), 348 irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); 349 continue; 350 351 /* LCD1 INTG12 */ 352 case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... 353 EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): 354 irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), 355 irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); 356 continue; 357 358 /* Multi-Core Timer INTG12 */ 359 case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... 360 EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): 361 irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), 362 irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); 363 continue; 364 365 /* Multi-Core Timer INTG35 */ 366 case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... 367 EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): 368 irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), 369 irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); 370 continue; 371 372 /* Multi-Core Timer INTG51 */ 373 case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... 374 EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): 375 irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), 376 irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); 377 continue; 378 379 /* Multi-Core Timer INTG53 */ 380 case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... 381 EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): 382 irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), 383 irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); 384 continue; 385 } 386 387 irq[n] = qdev_get_gpio_in(dev, n); 388 } 389 } 390 391 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 392 0x09, 0x00, 0x00, 0x00 }; 393 394 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 395 unsigned size) 396 { 397 assert(offset < sizeof(chipid_and_omr)); 398 return chipid_and_omr[offset]; 399 } 400 401 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 402 uint64_t value, unsigned size) 403 { 404 return; 405 } 406 407 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 408 .read = exynos4210_chipid_and_omr_read, 409 .write = exynos4210_chipid_and_omr_write, 410 .endianness = DEVICE_NATIVE_ENDIAN, 411 .impl = { 412 .max_access_size = 1, 413 } 414 }; 415 416 void exynos4210_write_secondary(ARMCPU *cpu, 417 const struct arm_boot_info *info) 418 { 419 int n; 420 uint32_t smpboot[] = { 421 0xe59f3034, /* ldr r3, External gic_cpu_if */ 422 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 423 0xe59f0034, /* ldr r0, startaddr */ 424 0xe3a01001, /* mov r1, #1 */ 425 0xe5821000, /* str r1, [r2] */ 426 0xe5831000, /* str r1, [r3] */ 427 0xe3a010ff, /* mov r1, #0xff */ 428 0xe5821004, /* str r1, [r2, #4] */ 429 0xe5831004, /* str r1, [r3, #4] */ 430 0xf57ff04f, /* dsb */ 431 0xe320f003, /* wfi */ 432 0xe5901000, /* ldr r1, [r0] */ 433 0xe1110001, /* tst r1, r1 */ 434 0x0afffffb, /* beq <wfi> */ 435 0xe12fff11, /* bx r1 */ 436 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 437 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 438 0 /* bootreg: Boot register address is held here */ 439 }; 440 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 441 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 442 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 443 smpboot[n] = tswap32(smpboot[n]); 444 } 445 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 446 info->smp_loader_start); 447 } 448 449 static uint64_t exynos4210_calc_affinity(int cpu) 450 { 451 /* Exynos4210 has 0x9 as cluster ID */ 452 return (0x9 << ARM_AFF1_SHIFT) | cpu; 453 } 454 455 static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate, 456 qemu_irq irq, int nreq, int nevents, int width) 457 { 458 SysBusDevice *busdev; 459 DeviceState *dev; 460 int i; 461 462 dev = qdev_new("pl330"); 463 object_property_set_link(OBJECT(dev), "memory", 464 OBJECT(get_system_memory()), 465 &error_fatal); 466 qdev_prop_set_uint8(dev, "num_events", nevents); 467 qdev_prop_set_uint8(dev, "num_chnls", 8); 468 qdev_prop_set_uint8(dev, "num_periph_req", nreq); 469 470 qdev_prop_set_uint8(dev, "wr_cap", 4); 471 qdev_prop_set_uint8(dev, "wr_q_dep", 8); 472 qdev_prop_set_uint8(dev, "rd_cap", 4); 473 qdev_prop_set_uint8(dev, "rd_q_dep", 8); 474 qdev_prop_set_uint8(dev, "data_width", width); 475 qdev_prop_set_uint16(dev, "data_buffer_dep", width); 476 busdev = SYS_BUS_DEVICE(dev); 477 sysbus_realize_and_unref(busdev, &error_fatal); 478 sysbus_mmio_map(busdev, 0, base); 479 480 object_property_set_int(OBJECT(orgate), "num-lines", nevents + 1, 481 &error_abort); 482 qdev_realize(DEVICE(orgate), NULL, &error_abort); 483 484 for (i = 0; i < nevents + 1; i++) { 485 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i)); 486 } 487 qdev_connect_gpio_out(DEVICE(orgate), 0, irq); 488 return dev; 489 } 490 491 static void exynos4210_realize(DeviceState *socdev, Error **errp) 492 { 493 Exynos4210State *s = EXYNOS4210_SOC(socdev); 494 MemoryRegion *system_mem = get_system_memory(); 495 SysBusDevice *busdev; 496 DeviceState *dev, *uart[4], *pl330[3]; 497 int i, n; 498 499 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 500 Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); 501 502 /* By default A9 CPUs have EL3 enabled. This board does not currently 503 * support EL3 so the CPU EL3 property is disabled before realization. 504 */ 505 if (object_property_find(cpuobj, "has_el3")) { 506 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 507 } 508 509 s->cpu[n] = ARM_CPU(cpuobj); 510 object_property_set_int(cpuobj, "mp-affinity", 511 exynos4210_calc_affinity(n), &error_abort); 512 object_property_set_int(cpuobj, "reset-cbar", 513 EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 514 &error_abort); 515 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 516 } 517 518 /* IRQ Gate */ 519 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 520 DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); 521 object_property_set_int(OBJECT(orgate), "num-lines", 522 EXYNOS4210_IRQ_GATE_NINPUTS, 523 &error_abort); 524 qdev_realize(orgate, NULL, &error_abort); 525 qdev_connect_gpio_out(orgate, 0, 526 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 527 } 528 529 /* Private memory region and Internal GIC */ 530 qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); 531 busdev = SYS_BUS_DEVICE(&s->a9mpcore); 532 sysbus_realize(busdev, &error_fatal); 533 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 534 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 535 sysbus_connect_irq(busdev, n, 536 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); 537 } 538 539 /* Cache controller */ 540 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 541 542 /* External GIC */ 543 qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS); 544 busdev = SYS_BUS_DEVICE(&s->ext_gic); 545 sysbus_realize(busdev, &error_fatal); 546 /* Map CPU interface */ 547 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 548 /* Map Distributer interface */ 549 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 550 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 551 sysbus_connect_irq(busdev, n, 552 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); 553 } 554 555 /* Internal Interrupt Combiner */ 556 dev = qdev_new("exynos4210.combiner"); 557 busdev = SYS_BUS_DEVICE(dev); 558 sysbus_realize_and_unref(busdev, &error_fatal); 559 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 560 sysbus_connect_irq(busdev, n, 561 qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); 562 } 563 exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); 564 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 565 566 /* External Interrupt Combiner */ 567 dev = qdev_new("exynos4210.combiner"); 568 qdev_prop_set_uint32(dev, "external", 1); 569 busdev = SYS_BUS_DEVICE(dev); 570 sysbus_realize_and_unref(busdev, &error_fatal); 571 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 572 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); 573 } 574 exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); 575 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 576 577 /* Initialize board IRQs. */ 578 exynos4210_init_board_irqs(s); 579 580 /*** Memory ***/ 581 582 /* Chip-ID and OMR */ 583 memory_region_init_io(&s->chipid_mem, OBJECT(socdev), 584 &exynos4210_chipid_and_omr_ops, NULL, 585 "exynos4210.chipid", sizeof(chipid_and_omr)); 586 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 587 &s->chipid_mem); 588 589 /* Internal ROM */ 590 memory_region_init_rom(&s->irom_mem, OBJECT(socdev), "exynos4210.irom", 591 EXYNOS4210_IROM_SIZE, &error_fatal); 592 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 593 &s->irom_mem); 594 /* mirror of iROM */ 595 memory_region_init_alias(&s->irom_alias_mem, OBJECT(socdev), 596 "exynos4210.irom_alias", &s->irom_mem, 0, 597 EXYNOS4210_IROM_SIZE); 598 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 599 &s->irom_alias_mem); 600 601 /* Internal RAM */ 602 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 603 EXYNOS4210_IRAM_SIZE, &error_fatal); 604 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 605 &s->iram_mem); 606 607 /* PMU. 608 * The only reason of existence at the moment is that secondary CPU boot 609 * loader uses PMU INFORM5 register as a holding pen. 610 */ 611 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 612 613 sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL); 614 sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL); 615 616 /* PWM */ 617 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 618 s->irq_table[exynos4210_get_irq(22, 0)], 619 s->irq_table[exynos4210_get_irq(22, 1)], 620 s->irq_table[exynos4210_get_irq(22, 2)], 621 s->irq_table[exynos4210_get_irq(22, 3)], 622 s->irq_table[exynos4210_get_irq(22, 4)], 623 NULL); 624 /* RTC */ 625 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 626 s->irq_table[exynos4210_get_irq(23, 0)], 627 s->irq_table[exynos4210_get_irq(23, 1)], 628 NULL); 629 630 /* Multi Core Timer */ 631 dev = qdev_new("exynos4210.mct"); 632 busdev = SYS_BUS_DEVICE(dev); 633 sysbus_realize_and_unref(busdev, &error_fatal); 634 for (n = 0; n < 4; n++) { 635 /* Connect global timer interrupts to Combiner gpio_in */ 636 sysbus_connect_irq(busdev, n, 637 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 638 } 639 /* Connect local timer interrupts to Combiner gpio_in */ 640 sysbus_connect_irq(busdev, 4, 641 s->irq_table[exynos4210_get_irq(51, 0)]); 642 sysbus_connect_irq(busdev, 5, 643 s->irq_table[exynos4210_get_irq(35, 3)]); 644 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 645 646 /*** I2C ***/ 647 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 648 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 649 qemu_irq i2c_irq; 650 651 if (n < 8) { 652 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 653 } else { 654 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 655 } 656 657 dev = qdev_new("exynos4210.i2c"); 658 busdev = SYS_BUS_DEVICE(dev); 659 sysbus_realize_and_unref(busdev, &error_fatal); 660 sysbus_connect_irq(busdev, 0, i2c_irq); 661 sysbus_mmio_map(busdev, 0, addr); 662 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 663 } 664 665 666 /*** UARTs ***/ 667 uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 668 EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0), 669 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 670 671 uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 672 EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1), 673 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 674 675 uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 676 EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2), 677 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 678 679 uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 680 EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3), 681 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 682 683 /*** SD/MMC host controllers ***/ 684 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { 685 DeviceState *carddev; 686 BlockBackend *blk; 687 DriveInfo *di; 688 689 /* Compatible with: 690 * - SD Host Controller Specification Version 2.0 691 * - SDIO Specification Version 2.0 692 * - MMC Specification Version 4.3 693 * - SDMA 694 * - ADMA2 695 * 696 * As this part of the Exynos4210 is not publically available, 697 * we used the "HS-MMC Controller S3C2416X RISC Microprocessor" 698 * public datasheet which is very similar (implementing 699 * MMC Specification Version 4.0 being the only difference noted) 700 */ 701 dev = qdev_new(TYPE_S3C_SDHCI); 702 qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); 703 704 busdev = SYS_BUS_DEVICE(dev); 705 sysbus_realize_and_unref(busdev, &error_fatal); 706 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); 707 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); 708 709 di = drive_get(IF_SD, 0, n); 710 blk = di ? blk_by_legacy_dinfo(di) : NULL; 711 carddev = qdev_new(TYPE_SD_CARD); 712 qdev_prop_set_drive(carddev, "drive", blk); 713 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), 714 &error_fatal); 715 } 716 717 /*** Display controller (FIMD) ***/ 718 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, 719 s->irq_table[exynos4210_get_irq(11, 0)], 720 s->irq_table[exynos4210_get_irq(11, 1)], 721 s->irq_table[exynos4210_get_irq(11, 2)], 722 NULL); 723 724 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 725 s->irq_table[exynos4210_get_irq(28, 3)]); 726 727 /*** DMA controllers ***/ 728 pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR, 729 &s->pl330_irq_orgate[0], 730 s->irq_table[exynos4210_get_irq(21, 0)], 731 32, 32, 32); 732 pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR, 733 &s->pl330_irq_orgate[1], 734 s->irq_table[exynos4210_get_irq(21, 1)], 735 32, 32, 32); 736 pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR, 737 &s->pl330_irq_orgate[2], 738 s->irq_table[exynos4210_get_irq(20, 1)], 739 1, 31, 64); 740 741 sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1, 742 qdev_get_gpio_in(pl330[0], 15)); 743 sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1, 744 qdev_get_gpio_in(pl330[1], 15)); 745 sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1, 746 qdev_get_gpio_in(pl330[0], 17)); 747 sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1, 748 qdev_get_gpio_in(pl330[1], 17)); 749 } 750 751 static void exynos4210_init(Object *obj) 752 { 753 Exynos4210State *s = EXYNOS4210_SOC(obj); 754 int i; 755 756 for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { 757 char *name = g_strdup_printf("pl330-irq-orgate%d", i); 758 qemu_or_irq *orgate = &s->pl330_irq_orgate[i]; 759 760 object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); 761 g_free(name); 762 } 763 764 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { 765 g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); 766 object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); 767 } 768 769 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 770 object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); 771 } 772 773 static void exynos4210_class_init(ObjectClass *klass, void *data) 774 { 775 DeviceClass *dc = DEVICE_CLASS(klass); 776 777 dc->realize = exynos4210_realize; 778 } 779 780 static const TypeInfo exynos4210_info = { 781 .name = TYPE_EXYNOS4210_SOC, 782 .parent = TYPE_SYS_BUS_DEVICE, 783 .instance_size = sizeof(Exynos4210State), 784 .instance_init = exynos4210_init, 785 .class_init = exynos4210_class_init, 786 }; 787 788 static void exynos4210_register_types(void) 789 { 790 type_register_static(&exynos4210_info); 791 } 792 793 type_init(exynos4210_register_types) 794