xref: /openbmc/qemu/hw/arm/digic.c (revision 59a3a1c0)
1 /*
2  * QEMU model of the Canon DIGIC SoC.
3  *
4  * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
5  *
6  * This model is based on reverse engineering efforts
7  * made by CHDK (http://chdk.wikia.com) and
8  * Magic Lantern (http://www.magiclantern.fm) projects
9  * contributors.
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  */
22 
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qemu/module.h"
26 #include "hw/arm/digic.h"
27 #include "hw/qdev-properties.h"
28 #include "sysemu/sysemu.h"
29 
30 #define DIGIC4_TIMER_BASE(n)    (0xc0210000 + (n) * 0x100)
31 
32 #define DIGIC_UART_BASE          0xc0800000
33 
34 static void digic_init(Object *obj)
35 {
36     DigicState *s = DIGIC(obj);
37     int i;
38 
39     object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
40                             "arm946-" TYPE_ARM_CPU, &error_abort, NULL);
41 
42     for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
43 #define DIGIC_TIMER_NAME_MLEN    11
44         char name[DIGIC_TIMER_NAME_MLEN];
45 
46         snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);
47         sysbus_init_child_obj(obj, name, &s->timer[i], sizeof(s->timer[i]),
48                               TYPE_DIGIC_TIMER);
49     }
50 
51     sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
52                           TYPE_DIGIC_UART);
53 }
54 
55 static void digic_realize(DeviceState *dev, Error **errp)
56 {
57     DigicState *s = DIGIC(dev);
58     Error *err = NULL;
59     SysBusDevice *sbd;
60     int i;
61 
62     object_property_set_bool(OBJECT(&s->cpu), true, "reset-hivecs", &err);
63     if (err != NULL) {
64         error_propagate(errp, err);
65         return;
66     }
67 
68     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
69     if (err != NULL) {
70         error_propagate(errp, err);
71         return;
72     }
73 
74     for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
75         object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
76         if (err != NULL) {
77             error_propagate(errp, err);
78             return;
79         }
80 
81         sbd = SYS_BUS_DEVICE(&s->timer[i]);
82         sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i));
83     }
84 
85     qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0));
86     object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
87     if (err != NULL) {
88         error_propagate(errp, err);
89         return;
90     }
91 
92     sbd = SYS_BUS_DEVICE(&s->uart);
93     sysbus_mmio_map(sbd, 0, DIGIC_UART_BASE);
94 }
95 
96 static void digic_class_init(ObjectClass *oc, void *data)
97 {
98     DeviceClass *dc = DEVICE_CLASS(oc);
99 
100     dc->realize = digic_realize;
101     /* Reason: Uses serial_hds in the realize function --> not usable twice */
102     dc->user_creatable = false;
103 }
104 
105 static const TypeInfo digic_type_info = {
106     .name = TYPE_DIGIC,
107     .parent = TYPE_DEVICE,
108     .instance_size = sizeof(DigicState),
109     .instance_init = digic_init,
110     .class_init = digic_class_init,
111 };
112 
113 static void digic_register_types(void)
114 {
115     type_register_static(&digic_type_info);
116 }
117 
118 type_init(digic_register_types)
119