xref: /openbmc/qemu/hw/arm/digic.c (revision 576e99cb951e9c1a289555a31cfd5b9040e80037)
1 /*
2  * QEMU model of the Canon DIGIC SoC.
3  *
4  * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
5  *
6  * This model is based on reverse engineering efforts
7  * made by CHDK (http://chdk.wikia.com) and
8  * Magic Lantern (http://www.magiclantern.fm) projects
9  * contributors.
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  */
22 
23 #include "hw/arm/digic.h"
24 
25 #define DIGIC4_TIMER_BASE(n)    (0xc0210000 + (n) * 0x100)
26 
27 static void digic_init(Object *obj)
28 {
29     DigicState *s = DIGIC(obj);
30     DeviceState *dev;
31     int i;
32 
33     object_initialize(&s->cpu, sizeof(s->cpu), "arm946-" TYPE_ARM_CPU);
34     object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
35 
36     for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
37 #define DIGIC_TIMER_NAME_MLEN    11
38         char name[DIGIC_TIMER_NAME_MLEN];
39 
40         object_initialize(&s->timer[i], sizeof(s->timer[i]), TYPE_DIGIC_TIMER);
41         dev = DEVICE(&s->timer[i]);
42         qdev_set_parent_bus(dev, sysbus_get_default());
43         snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);
44         object_property_add_child(obj, name, OBJECT(&s->timer[i]), NULL);
45     }
46 }
47 
48 static void digic_realize(DeviceState *dev, Error **errp)
49 {
50     DigicState *s = DIGIC(dev);
51     Error *err = NULL;
52     SysBusDevice *sbd;
53     int i;
54 
55     object_property_set_bool(OBJECT(&s->cpu), true, "reset-hivecs", &err);
56     if (err != NULL) {
57         error_propagate(errp, err);
58         return;
59     }
60 
61     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
62     if (err != NULL) {
63         error_propagate(errp, err);
64         return;
65     }
66 
67     for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
68         object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
69         if (err != NULL) {
70             error_propagate(errp, err);
71             return;
72         }
73 
74         sbd = SYS_BUS_DEVICE(&s->timer[i]);
75         sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i));
76     }
77 }
78 
79 static void digic_class_init(ObjectClass *oc, void *data)
80 {
81     DeviceClass *dc = DEVICE_CLASS(oc);
82 
83     dc->realize = digic_realize;
84 }
85 
86 static const TypeInfo digic_type_info = {
87     .name = TYPE_DIGIC,
88     .parent = TYPE_DEVICE,
89     .instance_size = sizeof(DigicState),
90     .instance_init = digic_init,
91     .class_init = digic_class_init,
92 };
93 
94 static void digic_register_types(void)
95 {
96     type_register_static(&digic_type_info);
97 }
98 
99 type_init(digic_register_types)
100