1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/error-report.h" 12 #include "qapi/error.h" 13 #include <libfdt.h> 14 #include "hw/hw.h" 15 #include "hw/arm/arm.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "sysemu/kvm.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/numa.h" 20 #include "hw/boards.h" 21 #include "hw/loader.h" 22 #include "elf.h" 23 #include "sysemu/device_tree.h" 24 #include "qemu/config-file.h" 25 #include "exec/address-spaces.h" 26 27 /* Kernel boot protocol is specified in the kernel docs 28 * Documentation/arm/Booting and Documentation/arm64/booting.txt 29 * They have different preferred image load offsets from system RAM base. 30 */ 31 #define KERNEL_ARGS_ADDR 0x100 32 #define KERNEL_LOAD_ADDR 0x00010000 33 #define KERNEL64_LOAD_ADDR 0x00080000 34 35 #define ARM64_TEXT_OFFSET_OFFSET 8 36 #define ARM64_MAGIC_OFFSET 56 37 38 typedef enum { 39 FIXUP_NONE = 0, /* do nothing */ 40 FIXUP_TERMINATOR, /* end of insns */ 41 FIXUP_BOARDID, /* overwrite with board ID number */ 42 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 43 FIXUP_ARGPTR, /* overwrite with pointer to kernel args */ 44 FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */ 45 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 46 FIXUP_BOOTREG, /* overwrite with boot register address */ 47 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 48 FIXUP_MAX, 49 } FixupType; 50 51 typedef struct ARMInsnFixup { 52 uint32_t insn; 53 FixupType fixup; 54 } ARMInsnFixup; 55 56 static const ARMInsnFixup bootloader_aarch64[] = { 57 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 58 { 0xaa1f03e1 }, /* mov x1, xzr */ 59 { 0xaa1f03e2 }, /* mov x2, xzr */ 60 { 0xaa1f03e3 }, /* mov x3, xzr */ 61 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 62 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 63 { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */ 64 { 0 }, /* .word @DTB Higher 32-bits */ 65 { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */ 66 { 0 }, /* .word @Kernel Entry Higher 32-bits */ 67 { 0, FIXUP_TERMINATOR } 68 }; 69 70 /* A very small bootloader: call the board-setup code (if needed), 71 * set r0-r2, then jump to the kernel. 72 * If we're not calling boot setup code then we don't copy across 73 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 74 */ 75 76 static const ARMInsnFixup bootloader[] = { 77 { 0xe28fe004 }, /* add lr, pc, #4 */ 78 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 79 { 0, FIXUP_BOARD_SETUP }, 80 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 81 { 0xe3a00000 }, /* mov r0, #0 */ 82 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 83 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 84 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 85 { 0, FIXUP_BOARDID }, 86 { 0, FIXUP_ARGPTR }, 87 { 0, FIXUP_ENTRYPOINT }, 88 { 0, FIXUP_TERMINATOR } 89 }; 90 91 /* Handling for secondary CPU boot in a multicore system. 92 * Unlike the uniprocessor/primary CPU boot, this is platform 93 * dependent. The default code here is based on the secondary 94 * CPU boot protocol used on realview/vexpress boards, with 95 * some parameterisation to increase its flexibility. 96 * QEMU platform models for which this code is not appropriate 97 * should override write_secondary_boot and secondary_cpu_reset_hook 98 * instead. 99 * 100 * This code enables the interrupt controllers for the secondary 101 * CPUs and then puts all the secondary CPUs into a loop waiting 102 * for an interprocessor interrupt and polling a configurable 103 * location for the kernel secondary CPU entry point. 104 */ 105 #define DSB_INSN 0xf57ff04f 106 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 107 108 static const ARMInsnFixup smpboot[] = { 109 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 110 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 111 { 0xe3a01001 }, /* mov r1, #1 */ 112 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 113 { 0xe3a010ff }, /* mov r1, #0xff */ 114 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 115 { 0, FIXUP_DSB }, /* dsb */ 116 { 0xe320f003 }, /* wfi */ 117 { 0xe5901000 }, /* ldr r1, [r0] */ 118 { 0xe1110001 }, /* tst r1, r1 */ 119 { 0x0afffffb }, /* beq <wfi> */ 120 { 0xe12fff11 }, /* bx r1 */ 121 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 122 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 123 { 0, FIXUP_TERMINATOR } 124 }; 125 126 static void write_bootloader(const char *name, hwaddr addr, 127 const ARMInsnFixup *insns, uint32_t *fixupcontext) 128 { 129 /* Fix up the specified bootloader fragment and write it into 130 * guest memory using rom_add_blob_fixed(). fixupcontext is 131 * an array giving the values to write in for the fixup types 132 * which write a value into the code array. 133 */ 134 int i, len; 135 uint32_t *code; 136 137 len = 0; 138 while (insns[len].fixup != FIXUP_TERMINATOR) { 139 len++; 140 } 141 142 code = g_new0(uint32_t, len); 143 144 for (i = 0; i < len; i++) { 145 uint32_t insn = insns[i].insn; 146 FixupType fixup = insns[i].fixup; 147 148 switch (fixup) { 149 case FIXUP_NONE: 150 break; 151 case FIXUP_BOARDID: 152 case FIXUP_BOARD_SETUP: 153 case FIXUP_ARGPTR: 154 case FIXUP_ENTRYPOINT: 155 case FIXUP_GIC_CPU_IF: 156 case FIXUP_BOOTREG: 157 case FIXUP_DSB: 158 insn = fixupcontext[fixup]; 159 break; 160 default: 161 abort(); 162 } 163 code[i] = tswap32(insn); 164 } 165 166 rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr); 167 168 g_free(code); 169 } 170 171 static void default_write_secondary(ARMCPU *cpu, 172 const struct arm_boot_info *info) 173 { 174 uint32_t fixupcontext[FIXUP_MAX]; 175 176 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 177 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 178 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 179 fixupcontext[FIXUP_DSB] = DSB_INSN; 180 } else { 181 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 182 } 183 184 write_bootloader("smpboot", info->smp_loader_start, 185 smpboot, fixupcontext); 186 } 187 188 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 189 const struct arm_boot_info *info, 190 hwaddr mvbar_addr) 191 { 192 int n; 193 uint32_t mvbar_blob[] = { 194 /* mvbar_addr: secure monitor vectors 195 * Default unimplemented and unused vectors to spin. Makes it 196 * easier to debug (as opposed to the CPU running away). 197 */ 198 0xeafffffe, /* (spin) */ 199 0xeafffffe, /* (spin) */ 200 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 201 0xeafffffe, /* (spin) */ 202 0xeafffffe, /* (spin) */ 203 0xeafffffe, /* (spin) */ 204 0xeafffffe, /* (spin) */ 205 0xeafffffe, /* (spin) */ 206 }; 207 uint32_t board_setup_blob[] = { 208 /* board setup addr */ 209 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 210 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 211 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 212 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 213 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 214 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 215 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 216 0xe1a0f001, /* mov pc, r1 ;return */ 217 }; 218 219 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 220 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 221 222 /* check that these blobs don't overlap */ 223 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 224 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 225 226 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 227 mvbar_blob[n] = tswap32(mvbar_blob[n]); 228 } 229 rom_add_blob_fixed("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 230 mvbar_addr); 231 232 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 233 board_setup_blob[n] = tswap32(board_setup_blob[n]); 234 } 235 rom_add_blob_fixed("board-setup", board_setup_blob, 236 sizeof(board_setup_blob), info->board_setup_addr); 237 } 238 239 static void default_reset_secondary(ARMCPU *cpu, 240 const struct arm_boot_info *info) 241 { 242 CPUState *cs = CPU(cpu); 243 244 address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr, 245 0, MEMTXATTRS_UNSPECIFIED, NULL); 246 cpu_set_pc(cs, info->smp_loader_start); 247 } 248 249 static inline bool have_dtb(const struct arm_boot_info *info) 250 { 251 return info->dtb_filename || info->get_dtb; 252 } 253 254 #define WRITE_WORD(p, value) do { \ 255 address_space_stl_notdirty(&address_space_memory, p, value, \ 256 MEMTXATTRS_UNSPECIFIED, NULL); \ 257 p += 4; \ 258 } while (0) 259 260 static void set_kernel_args(const struct arm_boot_info *info) 261 { 262 int initrd_size = info->initrd_size; 263 hwaddr base = info->loader_start; 264 hwaddr p; 265 266 p = base + KERNEL_ARGS_ADDR; 267 /* ATAG_CORE */ 268 WRITE_WORD(p, 5); 269 WRITE_WORD(p, 0x54410001); 270 WRITE_WORD(p, 1); 271 WRITE_WORD(p, 0x1000); 272 WRITE_WORD(p, 0); 273 /* ATAG_MEM */ 274 /* TODO: handle multiple chips on one ATAG list */ 275 WRITE_WORD(p, 4); 276 WRITE_WORD(p, 0x54410002); 277 WRITE_WORD(p, info->ram_size); 278 WRITE_WORD(p, info->loader_start); 279 if (initrd_size) { 280 /* ATAG_INITRD2 */ 281 WRITE_WORD(p, 4); 282 WRITE_WORD(p, 0x54420005); 283 WRITE_WORD(p, info->initrd_start); 284 WRITE_WORD(p, initrd_size); 285 } 286 if (info->kernel_cmdline && *info->kernel_cmdline) { 287 /* ATAG_CMDLINE */ 288 int cmdline_size; 289 290 cmdline_size = strlen(info->kernel_cmdline); 291 cpu_physical_memory_write(p + 8, info->kernel_cmdline, 292 cmdline_size + 1); 293 cmdline_size = (cmdline_size >> 2) + 1; 294 WRITE_WORD(p, cmdline_size + 2); 295 WRITE_WORD(p, 0x54410009); 296 p += cmdline_size * 4; 297 } 298 if (info->atag_board) { 299 /* ATAG_BOARD */ 300 int atag_board_len; 301 uint8_t atag_board_buf[0x1000]; 302 303 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 304 WRITE_WORD(p, (atag_board_len + 8) >> 2); 305 WRITE_WORD(p, 0x414f4d50); 306 cpu_physical_memory_write(p, atag_board_buf, atag_board_len); 307 p += atag_board_len; 308 } 309 /* ATAG_END */ 310 WRITE_WORD(p, 0); 311 WRITE_WORD(p, 0); 312 } 313 314 static void set_kernel_args_old(const struct arm_boot_info *info) 315 { 316 hwaddr p; 317 const char *s; 318 int initrd_size = info->initrd_size; 319 hwaddr base = info->loader_start; 320 321 /* see linux/include/asm-arm/setup.h */ 322 p = base + KERNEL_ARGS_ADDR; 323 /* page_size */ 324 WRITE_WORD(p, 4096); 325 /* nr_pages */ 326 WRITE_WORD(p, info->ram_size / 4096); 327 /* ramdisk_size */ 328 WRITE_WORD(p, 0); 329 #define FLAG_READONLY 1 330 #define FLAG_RDLOAD 4 331 #define FLAG_RDPROMPT 8 332 /* flags */ 333 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 334 /* rootdev */ 335 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 336 /* video_num_cols */ 337 WRITE_WORD(p, 0); 338 /* video_num_rows */ 339 WRITE_WORD(p, 0); 340 /* video_x */ 341 WRITE_WORD(p, 0); 342 /* video_y */ 343 WRITE_WORD(p, 0); 344 /* memc_control_reg */ 345 WRITE_WORD(p, 0); 346 /* unsigned char sounddefault */ 347 /* unsigned char adfsdrives */ 348 /* unsigned char bytes_per_char_h */ 349 /* unsigned char bytes_per_char_v */ 350 WRITE_WORD(p, 0); 351 /* pages_in_bank[4] */ 352 WRITE_WORD(p, 0); 353 WRITE_WORD(p, 0); 354 WRITE_WORD(p, 0); 355 WRITE_WORD(p, 0); 356 /* pages_in_vram */ 357 WRITE_WORD(p, 0); 358 /* initrd_start */ 359 if (initrd_size) { 360 WRITE_WORD(p, info->initrd_start); 361 } else { 362 WRITE_WORD(p, 0); 363 } 364 /* initrd_size */ 365 WRITE_WORD(p, initrd_size); 366 /* rd_start */ 367 WRITE_WORD(p, 0); 368 /* system_rev */ 369 WRITE_WORD(p, 0); 370 /* system_serial_low */ 371 WRITE_WORD(p, 0); 372 /* system_serial_high */ 373 WRITE_WORD(p, 0); 374 /* mem_fclk_21285 */ 375 WRITE_WORD(p, 0); 376 /* zero unused fields */ 377 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 378 WRITE_WORD(p, 0); 379 } 380 s = info->kernel_cmdline; 381 if (s) { 382 cpu_physical_memory_write(p, s, strlen(s) + 1); 383 } else { 384 WRITE_WORD(p, 0); 385 } 386 } 387 388 static void fdt_add_psci_node(void *fdt) 389 { 390 uint32_t cpu_suspend_fn; 391 uint32_t cpu_off_fn; 392 uint32_t cpu_on_fn; 393 uint32_t migrate_fn; 394 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 395 const char *psci_method; 396 int64_t psci_conduit; 397 398 psci_conduit = object_property_get_int(OBJECT(armcpu), 399 "psci-conduit", 400 &error_abort); 401 switch (psci_conduit) { 402 case QEMU_PSCI_CONDUIT_DISABLED: 403 return; 404 case QEMU_PSCI_CONDUIT_HVC: 405 psci_method = "hvc"; 406 break; 407 case QEMU_PSCI_CONDUIT_SMC: 408 psci_method = "smc"; 409 break; 410 default: 411 g_assert_not_reached(); 412 } 413 414 qemu_fdt_add_subnode(fdt, "/psci"); 415 if (armcpu->psci_version == 2) { 416 const char comp[] = "arm,psci-0.2\0arm,psci"; 417 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 418 419 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 420 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 421 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 422 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 423 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 424 } else { 425 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 426 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 427 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 428 } 429 } else { 430 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 431 432 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 433 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 434 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 435 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 436 } 437 438 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 439 * to the instruction that should be used to invoke PSCI functions. 440 * However, the device tree binding uses 'method' instead, so that is 441 * what we should use here. 442 */ 443 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 444 445 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 446 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 447 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 448 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 449 } 450 451 /** 452 * load_dtb() - load a device tree binary image into memory 453 * @addr: the address to load the image at 454 * @binfo: struct describing the boot environment 455 * @addr_limit: upper limit of the available memory area at @addr 456 * 457 * Load a device tree supplied by the machine or by the user with the 458 * '-dtb' command line option, and put it at offset @addr in target 459 * memory. 460 * 461 * If @addr_limit contains a meaningful value (i.e., it is strictly greater 462 * than @addr), the device tree is only loaded if its size does not exceed 463 * the limit. 464 * 465 * Returns: the size of the device tree image on success, 466 * 0 if the image size exceeds the limit, 467 * -1 on errors. 468 * 469 * Note: Must not be called unless have_dtb(binfo) is true. 470 */ 471 static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 472 hwaddr addr_limit) 473 { 474 void *fdt = NULL; 475 int size, rc; 476 uint32_t acells, scells; 477 char *nodename; 478 unsigned int i; 479 hwaddr mem_base, mem_len; 480 481 if (binfo->dtb_filename) { 482 char *filename; 483 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 484 if (!filename) { 485 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 486 goto fail; 487 } 488 489 fdt = load_device_tree(filename, &size); 490 if (!fdt) { 491 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 492 g_free(filename); 493 goto fail; 494 } 495 g_free(filename); 496 } else { 497 fdt = binfo->get_dtb(binfo, &size); 498 if (!fdt) { 499 fprintf(stderr, "Board was unable to create a dtb blob\n"); 500 goto fail; 501 } 502 } 503 504 if (addr_limit > addr && size > (addr_limit - addr)) { 505 /* Installing the device tree blob at addr would exceed addr_limit. 506 * Whether this constitutes failure is up to the caller to decide, 507 * so just return 0 as size, i.e., no error. 508 */ 509 g_free(fdt); 510 return 0; 511 } 512 513 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 514 NULL, &error_fatal); 515 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 516 NULL, &error_fatal); 517 if (acells == 0 || scells == 0) { 518 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 519 goto fail; 520 } 521 522 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { 523 /* This is user error so deserves a friendlier error message 524 * than the failure of setprop_sized_cells would provide 525 */ 526 fprintf(stderr, "qemu: dtb file not compatible with " 527 "RAM size > 4GB\n"); 528 goto fail; 529 } 530 531 if (nb_numa_nodes > 0) { 532 /* 533 * Turn the /memory node created before into a NOP node, then create 534 * /memory@addr nodes for all numa nodes respectively. 535 */ 536 qemu_fdt_nop_node(fdt, "/memory"); 537 mem_base = binfo->loader_start; 538 for (i = 0; i < nb_numa_nodes; i++) { 539 mem_len = numa_info[i].node_mem; 540 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 541 qemu_fdt_add_subnode(fdt, nodename); 542 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 543 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 544 acells, mem_base, 545 scells, mem_len); 546 if (rc < 0) { 547 fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename, 548 i); 549 goto fail; 550 } 551 552 qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i); 553 mem_base += mem_len; 554 g_free(nodename); 555 } 556 } else { 557 Error *err = NULL; 558 559 rc = fdt_path_offset(fdt, "/memory"); 560 if (rc < 0) { 561 qemu_fdt_add_subnode(fdt, "/memory"); 562 } 563 564 if (!qemu_fdt_getprop(fdt, "/memory", "device_type", NULL, &err)) { 565 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 566 } 567 568 rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg", 569 acells, binfo->loader_start, 570 scells, binfo->ram_size); 571 if (rc < 0) { 572 fprintf(stderr, "couldn't set /memory/reg\n"); 573 goto fail; 574 } 575 } 576 577 rc = fdt_path_offset(fdt, "/chosen"); 578 if (rc < 0) { 579 qemu_fdt_add_subnode(fdt, "/chosen"); 580 } 581 582 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { 583 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 584 binfo->kernel_cmdline); 585 if (rc < 0) { 586 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 587 goto fail; 588 } 589 } 590 591 if (binfo->initrd_size) { 592 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 593 binfo->initrd_start); 594 if (rc < 0) { 595 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 596 goto fail; 597 } 598 599 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 600 binfo->initrd_start + binfo->initrd_size); 601 if (rc < 0) { 602 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 603 goto fail; 604 } 605 } 606 607 fdt_add_psci_node(fdt); 608 609 if (binfo->modify_dtb) { 610 binfo->modify_dtb(binfo, fdt); 611 } 612 613 qemu_fdt_dumpdtb(fdt, size); 614 615 /* Put the DTB into the memory map as a ROM image: this will ensure 616 * the DTB is copied again upon reset, even if addr points into RAM. 617 */ 618 rom_add_blob_fixed("dtb", fdt, size, addr); 619 620 g_free(fdt); 621 622 return size; 623 624 fail: 625 g_free(fdt); 626 return -1; 627 } 628 629 static void do_cpu_reset(void *opaque) 630 { 631 ARMCPU *cpu = opaque; 632 CPUState *cs = CPU(cpu); 633 CPUARMState *env = &cpu->env; 634 const struct arm_boot_info *info = env->boot_info; 635 636 cpu_reset(cs); 637 if (info) { 638 if (!info->is_linux) { 639 int i; 640 /* Jump to the entry point. */ 641 uint64_t entry = info->entry; 642 643 switch (info->endianness) { 644 case ARM_ENDIANNESS_LE: 645 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 646 for (i = 1; i < 4; ++i) { 647 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 648 } 649 env->uncached_cpsr &= ~CPSR_E; 650 break; 651 case ARM_ENDIANNESS_BE8: 652 env->cp15.sctlr_el[1] |= SCTLR_E0E; 653 for (i = 1; i < 4; ++i) { 654 env->cp15.sctlr_el[i] |= SCTLR_EE; 655 } 656 env->uncached_cpsr |= CPSR_E; 657 break; 658 case ARM_ENDIANNESS_BE32: 659 env->cp15.sctlr_el[1] |= SCTLR_B; 660 break; 661 case ARM_ENDIANNESS_UNKNOWN: 662 break; /* Board's decision */ 663 default: 664 g_assert_not_reached(); 665 } 666 667 if (!env->aarch64) { 668 env->thumb = info->entry & 1; 669 entry &= 0xfffffffe; 670 } 671 cpu_set_pc(cs, entry); 672 } else { 673 /* If we are booting Linux then we need to check whether we are 674 * booting into secure or non-secure state and adjust the state 675 * accordingly. Out of reset, ARM is defined to be in secure state 676 * (SCR.NS = 0), we change that here if non-secure boot has been 677 * requested. 678 */ 679 if (arm_feature(env, ARM_FEATURE_EL3)) { 680 /* AArch64 is defined to come out of reset into EL3 if enabled. 681 * If we are booting Linux then we need to adjust our EL as 682 * Linux expects us to be in EL2 or EL1. AArch32 resets into 683 * SVC, which Linux expects, so no privilege/exception level to 684 * adjust. 685 */ 686 if (env->aarch64) { 687 env->cp15.scr_el3 |= SCR_RW; 688 if (arm_feature(env, ARM_FEATURE_EL2)) { 689 env->cp15.hcr_el2 |= HCR_RW; 690 env->pstate = PSTATE_MODE_EL2h; 691 } else { 692 env->pstate = PSTATE_MODE_EL1h; 693 } 694 } 695 696 /* Set to non-secure if not a secure boot */ 697 if (!info->secure_boot && 698 (cs != first_cpu || !info->secure_board_setup)) { 699 /* Linux expects non-secure state */ 700 env->cp15.scr_el3 |= SCR_NS; 701 } 702 } 703 704 if (cs == first_cpu) { 705 cpu_set_pc(cs, info->loader_start); 706 707 if (!have_dtb(info)) { 708 if (old_param) { 709 set_kernel_args_old(info); 710 } else { 711 set_kernel_args(info); 712 } 713 } 714 } else { 715 info->secondary_cpu_reset_hook(cpu, info); 716 } 717 } 718 } 719 } 720 721 /** 722 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 723 * by key. 724 * @fw_cfg: The firmware config instance to store the data in. 725 * @size_key: The firmware config key to store the size of the loaded 726 * data under, with fw_cfg_add_i32(). 727 * @data_key: The firmware config key to store the loaded data under, 728 * with fw_cfg_add_bytes(). 729 * @image_name: The name of the image file to load. If it is NULL, the 730 * function returns without doing anything. 731 * @try_decompress: Whether the image should be decompressed (gunzipped) before 732 * adding it to fw_cfg. If decompression fails, the image is 733 * loaded as-is. 734 * 735 * In case of failure, the function prints an error message to stderr and the 736 * process exits with status 1. 737 */ 738 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 739 uint16_t data_key, const char *image_name, 740 bool try_decompress) 741 { 742 size_t size = -1; 743 uint8_t *data; 744 745 if (image_name == NULL) { 746 return; 747 } 748 749 if (try_decompress) { 750 size = load_image_gzipped_buffer(image_name, 751 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 752 } 753 754 if (size == (size_t)-1) { 755 gchar *contents; 756 gsize length; 757 758 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 759 error_report("failed to load \"%s\"", image_name); 760 exit(1); 761 } 762 size = length; 763 data = (uint8_t *)contents; 764 } 765 766 fw_cfg_add_i32(fw_cfg, size_key, size); 767 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 768 } 769 770 static int do_arm_linux_init(Object *obj, void *opaque) 771 { 772 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 773 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 774 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 775 struct arm_boot_info *info = opaque; 776 777 if (albifc->arm_linux_init) { 778 albifc->arm_linux_init(albif, info->secure_boot); 779 } 780 } 781 return 0; 782 } 783 784 static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 785 uint64_t *lowaddr, uint64_t *highaddr, 786 int elf_machine) 787 { 788 bool elf_is64; 789 union { 790 Elf32_Ehdr h32; 791 Elf64_Ehdr h64; 792 } elf_header; 793 int data_swab = 0; 794 bool big_endian; 795 uint64_t ret = -1; 796 Error *err = NULL; 797 798 799 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 800 if (err) { 801 return ret; 802 } 803 804 if (elf_is64) { 805 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 806 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 807 : ARM_ENDIANNESS_LE; 808 } else { 809 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 810 if (big_endian) { 811 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 812 info->endianness = ARM_ENDIANNESS_BE8; 813 } else { 814 info->endianness = ARM_ENDIANNESS_BE32; 815 /* In BE32, the CPU has a different view of the per-byte 816 * address map than the rest of the system. BE32 ELF files 817 * are organised such that they can be programmed through 818 * the CPU's per-word byte-reversed view of the world. QEMU 819 * however loads ELF files independently of the CPU. So 820 * tell the ELF loader to byte reverse the data for us. 821 */ 822 data_swab = 2; 823 } 824 } else { 825 info->endianness = ARM_ENDIANNESS_LE; 826 } 827 } 828 829 ret = load_elf(info->kernel_filename, NULL, NULL, 830 pentry, lowaddr, highaddr, big_endian, elf_machine, 831 1, data_swab); 832 if (ret <= 0) { 833 /* The header loaded but the image didn't */ 834 exit(1); 835 } 836 837 return ret; 838 } 839 840 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 841 hwaddr *entry) 842 { 843 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 844 uint8_t *buffer; 845 int size; 846 847 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 848 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 849 &buffer); 850 851 if (size < 0) { 852 gsize len; 853 854 /* Load as raw file otherwise */ 855 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 856 return -1; 857 } 858 size = len; 859 } 860 861 /* check the arm64 magic header value -- very old kernels may not have it */ 862 if (memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 863 uint64_t hdrvals[2]; 864 865 /* The arm64 Image header has text_offset and image_size fields at 8 and 866 * 16 bytes into the Image header, respectively. The text_offset field 867 * is only valid if the image_size is non-zero. 868 */ 869 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 870 if (hdrvals[1] != 0) { 871 kernel_load_offset = le64_to_cpu(hdrvals[0]); 872 } 873 } 874 875 *entry = mem_base + kernel_load_offset; 876 rom_add_blob_fixed(filename, buffer, size, *entry); 877 878 g_free(buffer); 879 880 return size; 881 } 882 883 static void arm_load_kernel_notify(Notifier *notifier, void *data) 884 { 885 CPUState *cs; 886 int kernel_size; 887 int initrd_size; 888 int is_linux = 0; 889 uint64_t elf_entry, elf_low_addr, elf_high_addr; 890 int elf_machine; 891 hwaddr entry; 892 static const ARMInsnFixup *primary_loader; 893 ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier, 894 notifier, notifier); 895 ARMCPU *cpu = n->cpu; 896 struct arm_boot_info *info = 897 container_of(n, struct arm_boot_info, load_kernel_notifier); 898 899 /* The board code is not supposed to set secure_board_setup unless 900 * running its code in secure mode is actually possible, and KVM 901 * doesn't support secure. 902 */ 903 assert(!(info->secure_board_setup && kvm_enabled())); 904 905 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 906 907 /* Load the kernel. */ 908 if (!info->kernel_filename || info->firmware_loaded) { 909 910 if (have_dtb(info)) { 911 /* If we have a device tree blob, but no kernel to supply it to (or 912 * the kernel is supposed to be loaded by the bootloader), copy the 913 * DTB to the base of RAM for the bootloader to pick up. 914 */ 915 if (load_dtb(info->loader_start, info, 0) < 0) { 916 exit(1); 917 } 918 } 919 920 if (info->kernel_filename) { 921 FWCfgState *fw_cfg; 922 bool try_decompressing_kernel; 923 924 fw_cfg = fw_cfg_find(); 925 try_decompressing_kernel = arm_feature(&cpu->env, 926 ARM_FEATURE_AARCH64); 927 928 /* Expose the kernel, the command line, and the initrd in fw_cfg. 929 * We don't process them here at all, it's all left to the 930 * firmware. 931 */ 932 load_image_to_fw_cfg(fw_cfg, 933 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 934 info->kernel_filename, 935 try_decompressing_kernel); 936 load_image_to_fw_cfg(fw_cfg, 937 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 938 info->initrd_filename, false); 939 940 if (info->kernel_cmdline) { 941 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 942 strlen(info->kernel_cmdline) + 1); 943 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 944 info->kernel_cmdline); 945 } 946 } 947 948 /* We will start from address 0 (typically a boot ROM image) in the 949 * same way as hardware. 950 */ 951 return; 952 } 953 954 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 955 primary_loader = bootloader_aarch64; 956 elf_machine = EM_AARCH64; 957 } else { 958 primary_loader = bootloader; 959 if (!info->write_board_setup) { 960 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 961 } 962 elf_machine = EM_ARM; 963 } 964 965 if (!info->secondary_cpu_reset_hook) { 966 info->secondary_cpu_reset_hook = default_reset_secondary; 967 } 968 if (!info->write_secondary_boot) { 969 info->write_secondary_boot = default_write_secondary; 970 } 971 972 if (info->nb_cpus == 0) 973 info->nb_cpus = 1; 974 975 /* We want to put the initrd far enough into RAM that when the 976 * kernel is uncompressed it will not clobber the initrd. However 977 * on boards without much RAM we must ensure that we still leave 978 * enough room for a decent sized initrd, and on boards with large 979 * amounts of RAM we must avoid the initrd being so far up in RAM 980 * that it is outside lowmem and inaccessible to the kernel. 981 * So for boards with less than 256MB of RAM we put the initrd 982 * halfway into RAM, and for boards with 256MB of RAM or more we put 983 * the initrd at 128MB. 984 */ 985 info->initrd_start = info->loader_start + 986 MIN(info->ram_size / 2, 128 * 1024 * 1024); 987 988 /* Assume that raw images are linux kernels, and ELF images are not. */ 989 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, 990 &elf_high_addr, elf_machine); 991 if (kernel_size > 0 && have_dtb(info)) { 992 /* If there is still some room left at the base of RAM, try and put 993 * the DTB there like we do for images loaded with -bios or -pflash. 994 */ 995 if (elf_low_addr > info->loader_start 996 || elf_high_addr < info->loader_start) { 997 /* Pass elf_low_addr as address limit to load_dtb if it may be 998 * pointing into RAM, otherwise pass '0' (no limit) 999 */ 1000 if (elf_low_addr < info->loader_start) { 1001 elf_low_addr = 0; 1002 } 1003 if (load_dtb(info->loader_start, info, elf_low_addr) < 0) { 1004 exit(1); 1005 } 1006 } 1007 } 1008 entry = elf_entry; 1009 if (kernel_size < 0) { 1010 kernel_size = load_uimage(info->kernel_filename, &entry, NULL, 1011 &is_linux, NULL, NULL); 1012 } 1013 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1014 kernel_size = load_aarch64_image(info->kernel_filename, 1015 info->loader_start, &entry); 1016 is_linux = 1; 1017 } else if (kernel_size < 0) { 1018 /* 32-bit ARM */ 1019 entry = info->loader_start + KERNEL_LOAD_ADDR; 1020 kernel_size = load_image_targphys(info->kernel_filename, entry, 1021 info->ram_size - KERNEL_LOAD_ADDR); 1022 is_linux = 1; 1023 } 1024 if (kernel_size < 0) { 1025 error_report("could not load kernel '%s'", info->kernel_filename); 1026 exit(1); 1027 } 1028 info->entry = entry; 1029 if (is_linux) { 1030 uint32_t fixupcontext[FIXUP_MAX]; 1031 1032 if (info->initrd_filename) { 1033 initrd_size = load_ramdisk(info->initrd_filename, 1034 info->initrd_start, 1035 info->ram_size - 1036 info->initrd_start); 1037 if (initrd_size < 0) { 1038 initrd_size = load_image_targphys(info->initrd_filename, 1039 info->initrd_start, 1040 info->ram_size - 1041 info->initrd_start); 1042 } 1043 if (initrd_size < 0) { 1044 error_report("could not load initrd '%s'", 1045 info->initrd_filename); 1046 exit(1); 1047 } 1048 } else { 1049 initrd_size = 0; 1050 } 1051 info->initrd_size = initrd_size; 1052 1053 fixupcontext[FIXUP_BOARDID] = info->board_id; 1054 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1055 1056 /* for device tree boot, we pass the DTB directly in r2. Otherwise 1057 * we point to the kernel args. 1058 */ 1059 if (have_dtb(info)) { 1060 hwaddr align; 1061 hwaddr dtb_start; 1062 1063 if (elf_machine == EM_AARCH64) { 1064 /* 1065 * Some AArch64 kernels on early bootup map the fdt region as 1066 * 1067 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1068 * 1069 * Let's play safe and prealign it to 2MB to give us some space. 1070 */ 1071 align = 2 * 1024 * 1024; 1072 } else { 1073 /* 1074 * Some 32bit kernels will trash anything in the 4K page the 1075 * initrd ends in, so make sure the DTB isn't caught up in that. 1076 */ 1077 align = 4096; 1078 } 1079 1080 /* Place the DTB after the initrd in memory with alignment. */ 1081 dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); 1082 if (load_dtb(dtb_start, info, 0) < 0) { 1083 exit(1); 1084 } 1085 fixupcontext[FIXUP_ARGPTR] = dtb_start; 1086 } else { 1087 fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR; 1088 if (info->ram_size >= (1ULL << 32)) { 1089 error_report("RAM size must be less than 4GB to boot" 1090 " Linux kernel using ATAGS (try passing a device tree" 1091 " using -dtb)"); 1092 exit(1); 1093 } 1094 } 1095 fixupcontext[FIXUP_ENTRYPOINT] = entry; 1096 1097 write_bootloader("bootloader", info->loader_start, 1098 primary_loader, fixupcontext); 1099 1100 if (info->nb_cpus > 1) { 1101 info->write_secondary_boot(cpu, info); 1102 } 1103 if (info->write_board_setup) { 1104 info->write_board_setup(cpu, info); 1105 } 1106 1107 /* Notify devices which need to fake up firmware initialization 1108 * that we're doing a direct kernel boot. 1109 */ 1110 object_child_foreach_recursive(object_get_root(), 1111 do_arm_linux_init, info); 1112 } 1113 info->is_linux = is_linux; 1114 1115 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { 1116 ARM_CPU(cs)->env.boot_info = info; 1117 } 1118 } 1119 1120 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 1121 { 1122 CPUState *cs; 1123 1124 info->load_kernel_notifier.cpu = cpu; 1125 info->load_kernel_notifier.notifier.notify = arm_load_kernel_notify; 1126 qemu_add_machine_init_done_notifier(&info->load_kernel_notifier.notifier); 1127 1128 /* CPU objects (unlike devices) are not automatically reset on system 1129 * reset, so we must always register a handler to do so. If we're 1130 * actually loading a kernel, the handler is also responsible for 1131 * arranging that we start it correctly. 1132 */ 1133 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { 1134 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1135 } 1136 } 1137 1138 static const TypeInfo arm_linux_boot_if_info = { 1139 .name = TYPE_ARM_LINUX_BOOT_IF, 1140 .parent = TYPE_INTERFACE, 1141 .class_size = sizeof(ARMLinuxBootIfClass), 1142 }; 1143 1144 static void arm_linux_boot_register_types(void) 1145 { 1146 type_register_static(&arm_linux_boot_if_info); 1147 } 1148 1149 type_init(arm_linux_boot_register_types) 1150