1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu-common.h" 12 #include "qemu/datadir.h" 13 #include "qemu/error-report.h" 14 #include "qapi/error.h" 15 #include <libfdt.h> 16 #include "hw/arm/boot.h" 17 #include "hw/arm/linux-boot-if.h" 18 #include "sysemu/kvm.h" 19 #include "sysemu/sysemu.h" 20 #include "sysemu/numa.h" 21 #include "hw/boards.h" 22 #include "sysemu/reset.h" 23 #include "hw/loader.h" 24 #include "elf.h" 25 #include "sysemu/device_tree.h" 26 #include "qemu/config-file.h" 27 #include "qemu/option.h" 28 #include "qemu/units.h" 29 30 /* Kernel boot protocol is specified in the kernel docs 31 * Documentation/arm/Booting and Documentation/arm64/booting.txt 32 * They have different preferred image load offsets from system RAM base. 33 */ 34 #define KERNEL_ARGS_ADDR 0x100 35 #define KERNEL_NOLOAD_ADDR 0x02000000 36 #define KERNEL_LOAD_ADDR 0x00010000 37 #define KERNEL64_LOAD_ADDR 0x00080000 38 39 #define ARM64_TEXT_OFFSET_OFFSET 8 40 #define ARM64_MAGIC_OFFSET 56 41 42 #define BOOTLOADER_MAX_SIZE (4 * KiB) 43 44 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 45 const struct arm_boot_info *info) 46 { 47 /* Return the address space to use for bootloader reads and writes. 48 * We prefer the secure address space if the CPU has it and we're 49 * going to boot the guest into it. 50 */ 51 int asidx; 52 CPUState *cs = CPU(cpu); 53 54 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 55 asidx = ARMASIdx_S; 56 } else { 57 asidx = ARMASIdx_NS; 58 } 59 60 return cpu_get_address_space(cs, asidx); 61 } 62 63 typedef enum { 64 FIXUP_NONE = 0, /* do nothing */ 65 FIXUP_TERMINATOR, /* end of insns */ 66 FIXUP_BOARDID, /* overwrite with board ID number */ 67 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 68 FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */ 69 FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */ 70 FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */ 71 FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */ 72 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 73 FIXUP_BOOTREG, /* overwrite with boot register address */ 74 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 75 FIXUP_MAX, 76 } FixupType; 77 78 typedef struct ARMInsnFixup { 79 uint32_t insn; 80 FixupType fixup; 81 } ARMInsnFixup; 82 83 static const ARMInsnFixup bootloader_aarch64[] = { 84 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 85 { 0xaa1f03e1 }, /* mov x1, xzr */ 86 { 0xaa1f03e2 }, /* mov x2, xzr */ 87 { 0xaa1f03e3 }, /* mov x3, xzr */ 88 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 89 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 90 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ 91 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ 92 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ 93 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ 94 { 0, FIXUP_TERMINATOR } 95 }; 96 97 /* A very small bootloader: call the board-setup code (if needed), 98 * set r0-r2, then jump to the kernel. 99 * If we're not calling boot setup code then we don't copy across 100 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 101 */ 102 103 static const ARMInsnFixup bootloader[] = { 104 { 0xe28fe004 }, /* add lr, pc, #4 */ 105 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 106 { 0, FIXUP_BOARD_SETUP }, 107 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 108 { 0xe3a00000 }, /* mov r0, #0 */ 109 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 110 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 111 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 112 { 0, FIXUP_BOARDID }, 113 { 0, FIXUP_ARGPTR_LO }, 114 { 0, FIXUP_ENTRYPOINT_LO }, 115 { 0, FIXUP_TERMINATOR } 116 }; 117 118 /* Handling for secondary CPU boot in a multicore system. 119 * Unlike the uniprocessor/primary CPU boot, this is platform 120 * dependent. The default code here is based on the secondary 121 * CPU boot protocol used on realview/vexpress boards, with 122 * some parameterisation to increase its flexibility. 123 * QEMU platform models for which this code is not appropriate 124 * should override write_secondary_boot and secondary_cpu_reset_hook 125 * instead. 126 * 127 * This code enables the interrupt controllers for the secondary 128 * CPUs and then puts all the secondary CPUs into a loop waiting 129 * for an interprocessor interrupt and polling a configurable 130 * location for the kernel secondary CPU entry point. 131 */ 132 #define DSB_INSN 0xf57ff04f 133 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 134 135 static const ARMInsnFixup smpboot[] = { 136 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 137 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 138 { 0xe3a01001 }, /* mov r1, #1 */ 139 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 140 { 0xe3a010ff }, /* mov r1, #0xff */ 141 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 142 { 0, FIXUP_DSB }, /* dsb */ 143 { 0xe320f003 }, /* wfi */ 144 { 0xe5901000 }, /* ldr r1, [r0] */ 145 { 0xe1110001 }, /* tst r1, r1 */ 146 { 0x0afffffb }, /* beq <wfi> */ 147 { 0xe12fff11 }, /* bx r1 */ 148 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 149 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 150 { 0, FIXUP_TERMINATOR } 151 }; 152 153 static void write_bootloader(const char *name, hwaddr addr, 154 const ARMInsnFixup *insns, uint32_t *fixupcontext, 155 AddressSpace *as) 156 { 157 /* Fix up the specified bootloader fragment and write it into 158 * guest memory using rom_add_blob_fixed(). fixupcontext is 159 * an array giving the values to write in for the fixup types 160 * which write a value into the code array. 161 */ 162 int i, len; 163 uint32_t *code; 164 165 len = 0; 166 while (insns[len].fixup != FIXUP_TERMINATOR) { 167 len++; 168 } 169 170 code = g_new0(uint32_t, len); 171 172 for (i = 0; i < len; i++) { 173 uint32_t insn = insns[i].insn; 174 FixupType fixup = insns[i].fixup; 175 176 switch (fixup) { 177 case FIXUP_NONE: 178 break; 179 case FIXUP_BOARDID: 180 case FIXUP_BOARD_SETUP: 181 case FIXUP_ARGPTR_LO: 182 case FIXUP_ARGPTR_HI: 183 case FIXUP_ENTRYPOINT_LO: 184 case FIXUP_ENTRYPOINT_HI: 185 case FIXUP_GIC_CPU_IF: 186 case FIXUP_BOOTREG: 187 case FIXUP_DSB: 188 insn = fixupcontext[fixup]; 189 break; 190 default: 191 abort(); 192 } 193 code[i] = tswap32(insn); 194 } 195 196 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 197 198 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 199 200 g_free(code); 201 } 202 203 static void default_write_secondary(ARMCPU *cpu, 204 const struct arm_boot_info *info) 205 { 206 uint32_t fixupcontext[FIXUP_MAX]; 207 AddressSpace *as = arm_boot_address_space(cpu, info); 208 209 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 210 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 211 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 212 fixupcontext[FIXUP_DSB] = DSB_INSN; 213 } else { 214 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 215 } 216 217 write_bootloader("smpboot", info->smp_loader_start, 218 smpboot, fixupcontext, as); 219 } 220 221 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 222 const struct arm_boot_info *info, 223 hwaddr mvbar_addr) 224 { 225 AddressSpace *as = arm_boot_address_space(cpu, info); 226 int n; 227 uint32_t mvbar_blob[] = { 228 /* mvbar_addr: secure monitor vectors 229 * Default unimplemented and unused vectors to spin. Makes it 230 * easier to debug (as opposed to the CPU running away). 231 */ 232 0xeafffffe, /* (spin) */ 233 0xeafffffe, /* (spin) */ 234 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 235 0xeafffffe, /* (spin) */ 236 0xeafffffe, /* (spin) */ 237 0xeafffffe, /* (spin) */ 238 0xeafffffe, /* (spin) */ 239 0xeafffffe, /* (spin) */ 240 }; 241 uint32_t board_setup_blob[] = { 242 /* board setup addr */ 243 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ 244 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ 245 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ 246 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 247 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 248 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 249 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 250 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 251 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 252 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 253 0xe1a0f001, /* mov pc, r1 ;return */ 254 }; 255 256 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 257 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 258 259 /* check that these blobs don't overlap */ 260 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 261 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 262 263 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 264 mvbar_blob[n] = tswap32(mvbar_blob[n]); 265 } 266 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 267 mvbar_addr, as); 268 269 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 270 board_setup_blob[n] = tswap32(board_setup_blob[n]); 271 } 272 rom_add_blob_fixed_as("board-setup", board_setup_blob, 273 sizeof(board_setup_blob), info->board_setup_addr, as); 274 } 275 276 static void default_reset_secondary(ARMCPU *cpu, 277 const struct arm_boot_info *info) 278 { 279 AddressSpace *as = arm_boot_address_space(cpu, info); 280 CPUState *cs = CPU(cpu); 281 282 address_space_stl_notdirty(as, info->smp_bootreg_addr, 283 0, MEMTXATTRS_UNSPECIFIED, NULL); 284 cpu_set_pc(cs, info->smp_loader_start); 285 } 286 287 static inline bool have_dtb(const struct arm_boot_info *info) 288 { 289 return info->dtb_filename || info->get_dtb; 290 } 291 292 #define WRITE_WORD(p, value) do { \ 293 address_space_stl_notdirty(as, p, value, \ 294 MEMTXATTRS_UNSPECIFIED, NULL); \ 295 p += 4; \ 296 } while (0) 297 298 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 299 { 300 int initrd_size = info->initrd_size; 301 hwaddr base = info->loader_start; 302 hwaddr p; 303 304 p = base + KERNEL_ARGS_ADDR; 305 /* ATAG_CORE */ 306 WRITE_WORD(p, 5); 307 WRITE_WORD(p, 0x54410001); 308 WRITE_WORD(p, 1); 309 WRITE_WORD(p, 0x1000); 310 WRITE_WORD(p, 0); 311 /* ATAG_MEM */ 312 /* TODO: handle multiple chips on one ATAG list */ 313 WRITE_WORD(p, 4); 314 WRITE_WORD(p, 0x54410002); 315 WRITE_WORD(p, info->ram_size); 316 WRITE_WORD(p, info->loader_start); 317 if (initrd_size) { 318 /* ATAG_INITRD2 */ 319 WRITE_WORD(p, 4); 320 WRITE_WORD(p, 0x54420005); 321 WRITE_WORD(p, info->initrd_start); 322 WRITE_WORD(p, initrd_size); 323 } 324 if (info->kernel_cmdline && *info->kernel_cmdline) { 325 /* ATAG_CMDLINE */ 326 int cmdline_size; 327 328 cmdline_size = strlen(info->kernel_cmdline); 329 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 330 info->kernel_cmdline, cmdline_size + 1); 331 cmdline_size = (cmdline_size >> 2) + 1; 332 WRITE_WORD(p, cmdline_size + 2); 333 WRITE_WORD(p, 0x54410009); 334 p += cmdline_size * 4; 335 } 336 if (info->atag_board) { 337 /* ATAG_BOARD */ 338 int atag_board_len; 339 uint8_t atag_board_buf[0x1000]; 340 341 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 342 WRITE_WORD(p, (atag_board_len + 8) >> 2); 343 WRITE_WORD(p, 0x414f4d50); 344 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 345 atag_board_buf, atag_board_len); 346 p += atag_board_len; 347 } 348 /* ATAG_END */ 349 WRITE_WORD(p, 0); 350 WRITE_WORD(p, 0); 351 } 352 353 static void set_kernel_args_old(const struct arm_boot_info *info, 354 AddressSpace *as) 355 { 356 hwaddr p; 357 const char *s; 358 int initrd_size = info->initrd_size; 359 hwaddr base = info->loader_start; 360 361 /* see linux/include/asm-arm/setup.h */ 362 p = base + KERNEL_ARGS_ADDR; 363 /* page_size */ 364 WRITE_WORD(p, 4096); 365 /* nr_pages */ 366 WRITE_WORD(p, info->ram_size / 4096); 367 /* ramdisk_size */ 368 WRITE_WORD(p, 0); 369 #define FLAG_READONLY 1 370 #define FLAG_RDLOAD 4 371 #define FLAG_RDPROMPT 8 372 /* flags */ 373 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 374 /* rootdev */ 375 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 376 /* video_num_cols */ 377 WRITE_WORD(p, 0); 378 /* video_num_rows */ 379 WRITE_WORD(p, 0); 380 /* video_x */ 381 WRITE_WORD(p, 0); 382 /* video_y */ 383 WRITE_WORD(p, 0); 384 /* memc_control_reg */ 385 WRITE_WORD(p, 0); 386 /* unsigned char sounddefault */ 387 /* unsigned char adfsdrives */ 388 /* unsigned char bytes_per_char_h */ 389 /* unsigned char bytes_per_char_v */ 390 WRITE_WORD(p, 0); 391 /* pages_in_bank[4] */ 392 WRITE_WORD(p, 0); 393 WRITE_WORD(p, 0); 394 WRITE_WORD(p, 0); 395 WRITE_WORD(p, 0); 396 /* pages_in_vram */ 397 WRITE_WORD(p, 0); 398 /* initrd_start */ 399 if (initrd_size) { 400 WRITE_WORD(p, info->initrd_start); 401 } else { 402 WRITE_WORD(p, 0); 403 } 404 /* initrd_size */ 405 WRITE_WORD(p, initrd_size); 406 /* rd_start */ 407 WRITE_WORD(p, 0); 408 /* system_rev */ 409 WRITE_WORD(p, 0); 410 /* system_serial_low */ 411 WRITE_WORD(p, 0); 412 /* system_serial_high */ 413 WRITE_WORD(p, 0); 414 /* mem_fclk_21285 */ 415 WRITE_WORD(p, 0); 416 /* zero unused fields */ 417 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 418 WRITE_WORD(p, 0); 419 } 420 s = info->kernel_cmdline; 421 if (s) { 422 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1); 423 } else { 424 WRITE_WORD(p, 0); 425 } 426 } 427 428 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, 429 uint32_t scells, hwaddr mem_len, 430 int numa_node_id) 431 { 432 char *nodename; 433 int ret; 434 435 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 436 qemu_fdt_add_subnode(fdt, nodename); 437 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 438 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base, 439 scells, mem_len); 440 if (ret < 0) { 441 goto out; 442 } 443 444 /* only set the NUMA ID if it is specified */ 445 if (numa_node_id >= 0) { 446 ret = qemu_fdt_setprop_cell(fdt, nodename, 447 "numa-node-id", numa_node_id); 448 } 449 out: 450 g_free(nodename); 451 return ret; 452 } 453 454 static void fdt_add_psci_node(void *fdt) 455 { 456 uint32_t cpu_suspend_fn; 457 uint32_t cpu_off_fn; 458 uint32_t cpu_on_fn; 459 uint32_t migrate_fn; 460 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 461 const char *psci_method; 462 int64_t psci_conduit; 463 int rc; 464 465 psci_conduit = object_property_get_int(OBJECT(armcpu), 466 "psci-conduit", 467 &error_abort); 468 switch (psci_conduit) { 469 case QEMU_PSCI_CONDUIT_DISABLED: 470 return; 471 case QEMU_PSCI_CONDUIT_HVC: 472 psci_method = "hvc"; 473 break; 474 case QEMU_PSCI_CONDUIT_SMC: 475 psci_method = "smc"; 476 break; 477 default: 478 g_assert_not_reached(); 479 } 480 481 /* 482 * If /psci node is present in provided DTB, assume that no fixup 483 * is necessary and all PSCI configuration should be taken as-is 484 */ 485 rc = fdt_path_offset(fdt, "/psci"); 486 if (rc >= 0) { 487 return; 488 } 489 490 qemu_fdt_add_subnode(fdt, "/psci"); 491 if (armcpu->psci_version == 2) { 492 const char comp[] = "arm,psci-0.2\0arm,psci"; 493 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 494 495 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 496 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 497 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 498 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 499 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 500 } else { 501 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 502 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 503 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 504 } 505 } else { 506 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 507 508 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 509 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 510 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 511 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 512 } 513 514 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 515 * to the instruction that should be used to invoke PSCI functions. 516 * However, the device tree binding uses 'method' instead, so that is 517 * what we should use here. 518 */ 519 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 520 521 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 522 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 523 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 524 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 525 } 526 527 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 528 hwaddr addr_limit, AddressSpace *as, MachineState *ms) 529 { 530 void *fdt = NULL; 531 int size, rc, n = 0; 532 uint32_t acells, scells; 533 unsigned int i; 534 hwaddr mem_base, mem_len; 535 char **node_path; 536 Error *err = NULL; 537 538 if (binfo->dtb_filename) { 539 char *filename; 540 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 541 if (!filename) { 542 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 543 goto fail; 544 } 545 546 fdt = load_device_tree(filename, &size); 547 if (!fdt) { 548 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 549 g_free(filename); 550 goto fail; 551 } 552 g_free(filename); 553 } else { 554 fdt = binfo->get_dtb(binfo, &size); 555 if (!fdt) { 556 fprintf(stderr, "Board was unable to create a dtb blob\n"); 557 goto fail; 558 } 559 } 560 561 if (addr_limit > addr && size > (addr_limit - addr)) { 562 /* Installing the device tree blob at addr would exceed addr_limit. 563 * Whether this constitutes failure is up to the caller to decide, 564 * so just return 0 as size, i.e., no error. 565 */ 566 g_free(fdt); 567 return 0; 568 } 569 570 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 571 NULL, &error_fatal); 572 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 573 NULL, &error_fatal); 574 if (acells == 0 || scells == 0) { 575 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 576 goto fail; 577 } 578 579 if (scells < 2 && binfo->ram_size >= 4 * GiB) { 580 /* This is user error so deserves a friendlier error message 581 * than the failure of setprop_sized_cells would provide 582 */ 583 fprintf(stderr, "qemu: dtb file not compatible with " 584 "RAM size > 4GB\n"); 585 goto fail; 586 } 587 588 /* nop all root nodes matching /memory or /memory@unit-address */ 589 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 590 if (err) { 591 error_report_err(err); 592 goto fail; 593 } 594 while (node_path[n]) { 595 if (g_str_has_prefix(node_path[n], "/memory")) { 596 qemu_fdt_nop_node(fdt, node_path[n]); 597 } 598 n++; 599 } 600 g_strfreev(node_path); 601 602 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) { 603 mem_base = binfo->loader_start; 604 for (i = 0; i < ms->numa_state->num_nodes; i++) { 605 mem_len = ms->numa_state->nodes[i].node_mem; 606 rc = fdt_add_memory_node(fdt, acells, mem_base, 607 scells, mem_len, i); 608 if (rc < 0) { 609 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 610 mem_base); 611 goto fail; 612 } 613 614 mem_base += mem_len; 615 } 616 } else { 617 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start, 618 scells, binfo->ram_size, -1); 619 if (rc < 0) { 620 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 621 binfo->loader_start); 622 goto fail; 623 } 624 } 625 626 rc = fdt_path_offset(fdt, "/chosen"); 627 if (rc < 0) { 628 qemu_fdt_add_subnode(fdt, "/chosen"); 629 } 630 631 if (ms->kernel_cmdline && *ms->kernel_cmdline) { 632 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 633 ms->kernel_cmdline); 634 if (rc < 0) { 635 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 636 goto fail; 637 } 638 } 639 640 if (binfo->initrd_size) { 641 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 642 binfo->initrd_start); 643 if (rc < 0) { 644 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 645 goto fail; 646 } 647 648 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 649 binfo->initrd_start + binfo->initrd_size); 650 if (rc < 0) { 651 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 652 goto fail; 653 } 654 } 655 656 fdt_add_psci_node(fdt); 657 658 if (binfo->modify_dtb) { 659 binfo->modify_dtb(binfo, fdt); 660 } 661 662 qemu_fdt_dumpdtb(fdt, size); 663 664 /* Put the DTB into the memory map as a ROM image: this will ensure 665 * the DTB is copied again upon reset, even if addr points into RAM. 666 */ 667 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 668 669 g_free(fdt); 670 671 return size; 672 673 fail: 674 g_free(fdt); 675 return -1; 676 } 677 678 static void do_cpu_reset(void *opaque) 679 { 680 ARMCPU *cpu = opaque; 681 CPUState *cs = CPU(cpu); 682 CPUARMState *env = &cpu->env; 683 const struct arm_boot_info *info = env->boot_info; 684 685 cpu_reset(cs); 686 if (info) { 687 if (!info->is_linux) { 688 int i; 689 /* Jump to the entry point. */ 690 uint64_t entry = info->entry; 691 692 switch (info->endianness) { 693 case ARM_ENDIANNESS_LE: 694 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 695 for (i = 1; i < 4; ++i) { 696 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 697 } 698 env->uncached_cpsr &= ~CPSR_E; 699 break; 700 case ARM_ENDIANNESS_BE8: 701 env->cp15.sctlr_el[1] |= SCTLR_E0E; 702 for (i = 1; i < 4; ++i) { 703 env->cp15.sctlr_el[i] |= SCTLR_EE; 704 } 705 env->uncached_cpsr |= CPSR_E; 706 break; 707 case ARM_ENDIANNESS_BE32: 708 env->cp15.sctlr_el[1] |= SCTLR_B; 709 break; 710 case ARM_ENDIANNESS_UNKNOWN: 711 break; /* Board's decision */ 712 default: 713 g_assert_not_reached(); 714 } 715 716 cpu_set_pc(cs, entry); 717 } else { 718 /* If we are booting Linux then we need to check whether we are 719 * booting into secure or non-secure state and adjust the state 720 * accordingly. Out of reset, ARM is defined to be in secure state 721 * (SCR.NS = 0), we change that here if non-secure boot has been 722 * requested. 723 */ 724 if (arm_feature(env, ARM_FEATURE_EL3)) { 725 /* AArch64 is defined to come out of reset into EL3 if enabled. 726 * If we are booting Linux then we need to adjust our EL as 727 * Linux expects us to be in EL2 or EL1. AArch32 resets into 728 * SVC, which Linux expects, so no privilege/exception level to 729 * adjust. 730 */ 731 if (env->aarch64) { 732 env->cp15.scr_el3 |= SCR_RW; 733 if (arm_feature(env, ARM_FEATURE_EL2)) { 734 env->cp15.hcr_el2 |= HCR_RW; 735 env->pstate = PSTATE_MODE_EL2h; 736 } else { 737 env->pstate = PSTATE_MODE_EL1h; 738 } 739 if (cpu_isar_feature(aa64_pauth, cpu)) { 740 env->cp15.scr_el3 |= SCR_API | SCR_APK; 741 } 742 if (cpu_isar_feature(aa64_mte, cpu)) { 743 env->cp15.scr_el3 |= SCR_ATA; 744 } 745 if (cpu_isar_feature(aa64_sve, cpu)) { 746 env->cp15.cptr_el[3] |= CPTR_EZ; 747 } 748 /* AArch64 kernels never boot in secure mode */ 749 assert(!info->secure_boot); 750 /* This hook is only supported for AArch32 currently: 751 * bootloader_aarch64[] will not call the hook, and 752 * the code above has already dropped us into EL2 or EL1. 753 */ 754 assert(!info->secure_board_setup); 755 } 756 757 if (arm_feature(env, ARM_FEATURE_EL2)) { 758 /* If we have EL2 then Linux expects the HVC insn to work */ 759 env->cp15.scr_el3 |= SCR_HCE; 760 } 761 762 /* Set to non-secure if not a secure boot */ 763 if (!info->secure_boot && 764 (cs != first_cpu || !info->secure_board_setup)) { 765 /* Linux expects non-secure state */ 766 env->cp15.scr_el3 |= SCR_NS; 767 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 768 env->cp15.nsacr |= 3 << 10; 769 } 770 } 771 772 if (!env->aarch64 && !info->secure_boot && 773 arm_feature(env, ARM_FEATURE_EL2)) { 774 /* 775 * This is an AArch32 boot not to Secure state, and 776 * we have Hyp mode available, so boot the kernel into 777 * Hyp mode. This is not how the CPU comes out of reset, 778 * so we need to manually put it there. 779 */ 780 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw); 781 } 782 783 if (cs == first_cpu) { 784 AddressSpace *as = arm_boot_address_space(cpu, info); 785 786 cpu_set_pc(cs, info->loader_start); 787 788 if (!have_dtb(info)) { 789 if (old_param) { 790 set_kernel_args_old(info, as); 791 } else { 792 set_kernel_args(info, as); 793 } 794 } 795 } else { 796 info->secondary_cpu_reset_hook(cpu, info); 797 } 798 } 799 arm_rebuild_hflags(env); 800 } 801 } 802 803 /** 804 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 805 * by key. 806 * @fw_cfg: The firmware config instance to store the data in. 807 * @size_key: The firmware config key to store the size of the loaded 808 * data under, with fw_cfg_add_i32(). 809 * @data_key: The firmware config key to store the loaded data under, 810 * with fw_cfg_add_bytes(). 811 * @image_name: The name of the image file to load. If it is NULL, the 812 * function returns without doing anything. 813 * @try_decompress: Whether the image should be decompressed (gunzipped) before 814 * adding it to fw_cfg. If decompression fails, the image is 815 * loaded as-is. 816 * 817 * In case of failure, the function prints an error message to stderr and the 818 * process exits with status 1. 819 */ 820 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 821 uint16_t data_key, const char *image_name, 822 bool try_decompress) 823 { 824 size_t size = -1; 825 uint8_t *data; 826 827 if (image_name == NULL) { 828 return; 829 } 830 831 if (try_decompress) { 832 size = load_image_gzipped_buffer(image_name, 833 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 834 } 835 836 if (size == (size_t)-1) { 837 gchar *contents; 838 gsize length; 839 840 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 841 error_report("failed to load \"%s\"", image_name); 842 exit(1); 843 } 844 size = length; 845 data = (uint8_t *)contents; 846 } 847 848 fw_cfg_add_i32(fw_cfg, size_key, size); 849 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 850 } 851 852 static int do_arm_linux_init(Object *obj, void *opaque) 853 { 854 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 855 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 856 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 857 struct arm_boot_info *info = opaque; 858 859 if (albifc->arm_linux_init) { 860 albifc->arm_linux_init(albif, info->secure_boot); 861 } 862 } 863 return 0; 864 } 865 866 static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 867 uint64_t *lowaddr, uint64_t *highaddr, 868 int elf_machine, AddressSpace *as) 869 { 870 bool elf_is64; 871 union { 872 Elf32_Ehdr h32; 873 Elf64_Ehdr h64; 874 } elf_header; 875 int data_swab = 0; 876 bool big_endian; 877 int64_t ret = -1; 878 Error *err = NULL; 879 880 881 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 882 if (err) { 883 error_free(err); 884 return ret; 885 } 886 887 if (elf_is64) { 888 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 889 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 890 : ARM_ENDIANNESS_LE; 891 } else { 892 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 893 if (big_endian) { 894 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 895 info->endianness = ARM_ENDIANNESS_BE8; 896 } else { 897 info->endianness = ARM_ENDIANNESS_BE32; 898 /* In BE32, the CPU has a different view of the per-byte 899 * address map than the rest of the system. BE32 ELF files 900 * are organised such that they can be programmed through 901 * the CPU's per-word byte-reversed view of the world. QEMU 902 * however loads ELF files independently of the CPU. So 903 * tell the ELF loader to byte reverse the data for us. 904 */ 905 data_swab = 2; 906 } 907 } else { 908 info->endianness = ARM_ENDIANNESS_LE; 909 } 910 } 911 912 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL, 913 pentry, lowaddr, highaddr, NULL, big_endian, elf_machine, 914 1, data_swab, as); 915 if (ret <= 0) { 916 /* The header loaded but the image didn't */ 917 exit(1); 918 } 919 920 return ret; 921 } 922 923 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 924 hwaddr *entry, AddressSpace *as) 925 { 926 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 927 uint64_t kernel_size = 0; 928 uint8_t *buffer; 929 int size; 930 931 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 932 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 933 &buffer); 934 935 if (size < 0) { 936 gsize len; 937 938 /* Load as raw file otherwise */ 939 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 940 return -1; 941 } 942 size = len; 943 } 944 945 /* check the arm64 magic header value -- very old kernels may not have it */ 946 if (size > ARM64_MAGIC_OFFSET + 4 && 947 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 948 uint64_t hdrvals[2]; 949 950 /* The arm64 Image header has text_offset and image_size fields at 8 and 951 * 16 bytes into the Image header, respectively. The text_offset field 952 * is only valid if the image_size is non-zero. 953 */ 954 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 955 956 kernel_size = le64_to_cpu(hdrvals[1]); 957 958 if (kernel_size != 0) { 959 kernel_load_offset = le64_to_cpu(hdrvals[0]); 960 961 /* 962 * We write our startup "bootloader" at the very bottom of RAM, 963 * so that bit can't be used for the image. Luckily the Image 964 * format specification is that the image requests only an offset 965 * from a 2MB boundary, not an absolute load address. So if the 966 * image requests an offset that might mean it overlaps with the 967 * bootloader, we can just load it starting at 2MB+offset rather 968 * than 0MB + offset. 969 */ 970 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 971 kernel_load_offset += 2 * MiB; 972 } 973 } 974 } 975 976 /* 977 * Kernels before v3.17 don't populate the image_size field, and 978 * raw images have no header. For those our best guess at the size 979 * is the size of the Image file itself. 980 */ 981 if (kernel_size == 0) { 982 kernel_size = size; 983 } 984 985 *entry = mem_base + kernel_load_offset; 986 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 987 988 g_free(buffer); 989 990 return kernel_size; 991 } 992 993 static void arm_setup_direct_kernel_boot(ARMCPU *cpu, 994 struct arm_boot_info *info) 995 { 996 /* Set up for a direct boot of a kernel image file. */ 997 CPUState *cs; 998 AddressSpace *as = arm_boot_address_space(cpu, info); 999 int kernel_size; 1000 int initrd_size; 1001 int is_linux = 0; 1002 uint64_t elf_entry; 1003 /* Addresses of first byte used and first byte not used by the image */ 1004 uint64_t image_low_addr = 0, image_high_addr = 0; 1005 int elf_machine; 1006 hwaddr entry; 1007 static const ARMInsnFixup *primary_loader; 1008 uint64_t ram_end = info->loader_start + info->ram_size; 1009 1010 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1011 primary_loader = bootloader_aarch64; 1012 elf_machine = EM_AARCH64; 1013 } else { 1014 primary_loader = bootloader; 1015 if (!info->write_board_setup) { 1016 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 1017 } 1018 elf_machine = EM_ARM; 1019 } 1020 1021 if (!info->secondary_cpu_reset_hook) { 1022 info->secondary_cpu_reset_hook = default_reset_secondary; 1023 } 1024 if (!info->write_secondary_boot) { 1025 info->write_secondary_boot = default_write_secondary; 1026 } 1027 1028 if (info->nb_cpus == 0) 1029 info->nb_cpus = 1; 1030 1031 /* Assume that raw images are linux kernels, and ELF images are not. */ 1032 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr, 1033 &image_high_addr, elf_machine, as); 1034 if (kernel_size > 0 && have_dtb(info)) { 1035 /* 1036 * If there is still some room left at the base of RAM, try and put 1037 * the DTB there like we do for images loaded with -bios or -pflash. 1038 */ 1039 if (image_low_addr > info->loader_start 1040 || image_high_addr < info->loader_start) { 1041 /* 1042 * Set image_low_addr as address limit for arm_load_dtb if it may be 1043 * pointing into RAM, otherwise pass '0' (no limit) 1044 */ 1045 if (image_low_addr < info->loader_start) { 1046 image_low_addr = 0; 1047 } 1048 info->dtb_start = info->loader_start; 1049 info->dtb_limit = image_low_addr; 1050 } 1051 } 1052 entry = elf_entry; 1053 if (kernel_size < 0) { 1054 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; 1055 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, 1056 &is_linux, NULL, NULL, as); 1057 if (kernel_size >= 0) { 1058 image_low_addr = loadaddr; 1059 image_high_addr = image_low_addr + kernel_size; 1060 } 1061 } 1062 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1063 kernel_size = load_aarch64_image(info->kernel_filename, 1064 info->loader_start, &entry, as); 1065 is_linux = 1; 1066 if (kernel_size >= 0) { 1067 image_low_addr = entry; 1068 image_high_addr = image_low_addr + kernel_size; 1069 } 1070 } else if (kernel_size < 0) { 1071 /* 32-bit ARM */ 1072 entry = info->loader_start + KERNEL_LOAD_ADDR; 1073 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1074 ram_end - KERNEL_LOAD_ADDR, as); 1075 is_linux = 1; 1076 if (kernel_size >= 0) { 1077 image_low_addr = entry; 1078 image_high_addr = image_low_addr + kernel_size; 1079 } 1080 } 1081 if (kernel_size < 0) { 1082 error_report("could not load kernel '%s'", info->kernel_filename); 1083 exit(1); 1084 } 1085 1086 if (kernel_size > info->ram_size) { 1087 error_report("kernel '%s' is too large to fit in RAM " 1088 "(kernel size %d, RAM size %" PRId64 ")", 1089 info->kernel_filename, kernel_size, info->ram_size); 1090 exit(1); 1091 } 1092 1093 info->entry = entry; 1094 1095 /* 1096 * We want to put the initrd far enough into RAM that when the 1097 * kernel is uncompressed it will not clobber the initrd. However 1098 * on boards without much RAM we must ensure that we still leave 1099 * enough room for a decent sized initrd, and on boards with large 1100 * amounts of RAM we must avoid the initrd being so far up in RAM 1101 * that it is outside lowmem and inaccessible to the kernel. 1102 * So for boards with less than 256MB of RAM we put the initrd 1103 * halfway into RAM, and for boards with 256MB of RAM or more we put 1104 * the initrd at 128MB. 1105 * We also refuse to put the initrd somewhere that will definitely 1106 * overlay the kernel we just loaded, though for kernel formats which 1107 * don't tell us their exact size (eg self-decompressing 32-bit kernels) 1108 * we might still make a bad choice here. 1109 */ 1110 info->initrd_start = info->loader_start + 1111 MIN(info->ram_size / 2, 128 * MiB); 1112 if (image_high_addr) { 1113 info->initrd_start = MAX(info->initrd_start, image_high_addr); 1114 } 1115 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); 1116 1117 if (is_linux) { 1118 uint32_t fixupcontext[FIXUP_MAX]; 1119 1120 if (info->initrd_filename) { 1121 1122 if (info->initrd_start >= ram_end) { 1123 error_report("not enough space after kernel to load initrd"); 1124 exit(1); 1125 } 1126 1127 initrd_size = load_ramdisk_as(info->initrd_filename, 1128 info->initrd_start, 1129 ram_end - info->initrd_start, as); 1130 if (initrd_size < 0) { 1131 initrd_size = load_image_targphys_as(info->initrd_filename, 1132 info->initrd_start, 1133 ram_end - 1134 info->initrd_start, 1135 as); 1136 } 1137 if (initrd_size < 0) { 1138 error_report("could not load initrd '%s'", 1139 info->initrd_filename); 1140 exit(1); 1141 } 1142 if (info->initrd_start + initrd_size > ram_end) { 1143 error_report("could not load initrd '%s': " 1144 "too big to fit into RAM after the kernel", 1145 info->initrd_filename); 1146 exit(1); 1147 } 1148 } else { 1149 initrd_size = 0; 1150 } 1151 info->initrd_size = initrd_size; 1152 1153 fixupcontext[FIXUP_BOARDID] = info->board_id; 1154 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1155 1156 /* 1157 * for device tree boot, we pass the DTB directly in r2. Otherwise 1158 * we point to the kernel args. 1159 */ 1160 if (have_dtb(info)) { 1161 hwaddr align; 1162 1163 if (elf_machine == EM_AARCH64) { 1164 /* 1165 * Some AArch64 kernels on early bootup map the fdt region as 1166 * 1167 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1168 * 1169 * Let's play safe and prealign it to 2MB to give us some space. 1170 */ 1171 align = 2 * MiB; 1172 } else { 1173 /* 1174 * Some 32bit kernels will trash anything in the 4K page the 1175 * initrd ends in, so make sure the DTB isn't caught up in that. 1176 */ 1177 align = 4 * KiB; 1178 } 1179 1180 /* Place the DTB after the initrd in memory with alignment. */ 1181 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1182 align); 1183 if (info->dtb_start >= ram_end) { 1184 error_report("Not enough space for DTB after kernel/initrd"); 1185 exit(1); 1186 } 1187 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; 1188 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; 1189 } else { 1190 fixupcontext[FIXUP_ARGPTR_LO] = 1191 info->loader_start + KERNEL_ARGS_ADDR; 1192 fixupcontext[FIXUP_ARGPTR_HI] = 1193 (info->loader_start + KERNEL_ARGS_ADDR) >> 32; 1194 if (info->ram_size >= 4 * GiB) { 1195 error_report("RAM size must be less than 4GB to boot" 1196 " Linux kernel using ATAGS (try passing a device tree" 1197 " using -dtb)"); 1198 exit(1); 1199 } 1200 } 1201 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; 1202 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; 1203 1204 write_bootloader("bootloader", info->loader_start, 1205 primary_loader, fixupcontext, as); 1206 1207 if (info->nb_cpus > 1) { 1208 info->write_secondary_boot(cpu, info); 1209 } 1210 if (info->write_board_setup) { 1211 info->write_board_setup(cpu, info); 1212 } 1213 1214 /* 1215 * Notify devices which need to fake up firmware initialization 1216 * that we're doing a direct kernel boot. 1217 */ 1218 object_child_foreach_recursive(object_get_root(), 1219 do_arm_linux_init, info); 1220 } 1221 info->is_linux = is_linux; 1222 1223 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1224 ARM_CPU(cs)->env.boot_info = info; 1225 } 1226 } 1227 1228 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) 1229 { 1230 /* Set up for booting firmware (which might load a kernel via fw_cfg) */ 1231 1232 if (have_dtb(info)) { 1233 /* 1234 * If we have a device tree blob, but no kernel to supply it to (or 1235 * the kernel is supposed to be loaded by the bootloader), copy the 1236 * DTB to the base of RAM for the bootloader to pick up. 1237 */ 1238 info->dtb_start = info->loader_start; 1239 } 1240 1241 if (info->kernel_filename) { 1242 FWCfgState *fw_cfg; 1243 bool try_decompressing_kernel; 1244 1245 fw_cfg = fw_cfg_find(); 1246 1247 if (!fw_cfg) { 1248 error_report("This machine type does not support loading both " 1249 "a guest firmware/BIOS image and a guest kernel at " 1250 "the same time. You should change your QEMU command " 1251 "line to specify one or the other, but not both."); 1252 exit(1); 1253 } 1254 1255 try_decompressing_kernel = arm_feature(&cpu->env, 1256 ARM_FEATURE_AARCH64); 1257 1258 /* 1259 * Expose the kernel, the command line, and the initrd in fw_cfg. 1260 * We don't process them here at all, it's all left to the 1261 * firmware. 1262 */ 1263 load_image_to_fw_cfg(fw_cfg, 1264 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1265 info->kernel_filename, 1266 try_decompressing_kernel); 1267 load_image_to_fw_cfg(fw_cfg, 1268 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1269 info->initrd_filename, false); 1270 1271 if (info->kernel_cmdline) { 1272 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1273 strlen(info->kernel_cmdline) + 1); 1274 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1275 info->kernel_cmdline); 1276 } 1277 } 1278 1279 /* 1280 * We will start from address 0 (typically a boot ROM image) in the 1281 * same way as hardware. Leave env->boot_info NULL, so that 1282 * do_cpu_reset() knows it does not need to alter the PC on reset. 1283 */ 1284 } 1285 1286 void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) 1287 { 1288 CPUState *cs; 1289 AddressSpace *as = arm_boot_address_space(cpu, info); 1290 1291 /* 1292 * CPU objects (unlike devices) are not automatically reset on system 1293 * reset, so we must always register a handler to do so. If we're 1294 * actually loading a kernel, the handler is also responsible for 1295 * arranging that we start it correctly. 1296 */ 1297 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1298 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1299 } 1300 1301 /* 1302 * The board code is not supposed to set secure_board_setup unless 1303 * running its code in secure mode is actually possible, and KVM 1304 * doesn't support secure. 1305 */ 1306 assert(!(info->secure_board_setup && kvm_enabled())); 1307 info->kernel_filename = ms->kernel_filename; 1308 info->kernel_cmdline = ms->kernel_cmdline; 1309 info->initrd_filename = ms->initrd_filename; 1310 info->dtb_filename = ms->dtb; 1311 info->dtb_limit = 0; 1312 1313 /* Load the kernel. */ 1314 if (!info->kernel_filename || info->firmware_loaded) { 1315 arm_setup_firmware_boot(cpu, info); 1316 } else { 1317 arm_setup_direct_kernel_boot(cpu, info); 1318 } 1319 1320 if (!info->skip_dtb_autoload && have_dtb(info)) { 1321 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1322 exit(1); 1323 } 1324 } 1325 } 1326 1327 static const TypeInfo arm_linux_boot_if_info = { 1328 .name = TYPE_ARM_LINUX_BOOT_IF, 1329 .parent = TYPE_INTERFACE, 1330 .class_size = sizeof(ARMLinuxBootIfClass), 1331 }; 1332 1333 static void arm_linux_boot_register_types(void) 1334 { 1335 type_register_static(&arm_linux_boot_if_info); 1336 } 1337 1338 type_init(arm_linux_boot_register_types) 1339