1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/datadir.h" 12 #include "qemu/error-report.h" 13 #include "qapi/error.h" 14 #include <libfdt.h> 15 #include "hw/arm/boot.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "exec/target_page.h" 18 #include "system/kvm.h" 19 #include "system/tcg.h" 20 #include "system/system.h" 21 #include "system/numa.h" 22 #include "hw/boards.h" 23 #include "system/reset.h" 24 #include "hw/loader.h" 25 #include "elf.h" 26 #include "system/device_tree.h" 27 #include "qemu/config-file.h" 28 #include "qemu/option.h" 29 #include "qemu/units.h" 30 31 /* Kernel boot protocol is specified in the kernel docs 32 * Documentation/arm/Booting and Documentation/arm64/booting.txt 33 * They have different preferred image load offsets from system RAM base. 34 */ 35 #define KERNEL_ARGS_ADDR 0x100 36 #define KERNEL_NOLOAD_ADDR 0x02000000 37 #define KERNEL_LOAD_ADDR 0x00010000 38 #define KERNEL64_LOAD_ADDR 0x00080000 39 40 #define ARM64_TEXT_OFFSET_OFFSET 8 41 #define ARM64_MAGIC_OFFSET 56 42 43 #define BOOTLOADER_MAX_SIZE (4 * KiB) 44 45 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 46 const struct arm_boot_info *info) 47 { 48 /* Return the address space to use for bootloader reads and writes. 49 * We prefer the secure address space if the CPU has it and we're 50 * going to boot the guest into it. 51 */ 52 int asidx; 53 CPUState *cs = CPU(cpu); 54 55 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 56 asidx = ARMASIdx_S; 57 } else { 58 asidx = ARMASIdx_NS; 59 } 60 61 return cpu_get_address_space(cs, asidx); 62 } 63 64 static const ARMInsnFixup bootloader_aarch64[] = { 65 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 66 { 0xaa1f03e1 }, /* mov x1, xzr */ 67 { 0xaa1f03e2 }, /* mov x2, xzr */ 68 { 0xaa1f03e3 }, /* mov x3, xzr */ 69 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 70 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 71 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ 72 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ 73 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ 74 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ 75 { 0, FIXUP_TERMINATOR } 76 }; 77 78 /* A very small bootloader: call the board-setup code (if needed), 79 * set r0-r2, then jump to the kernel. 80 * If we're not calling boot setup code then we don't copy across 81 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 82 */ 83 84 static const ARMInsnFixup bootloader[] = { 85 { 0xe28fe004 }, /* add lr, pc, #4 */ 86 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 87 { 0, FIXUP_BOARD_SETUP }, 88 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 89 { 0xe3a00000 }, /* mov r0, #0 */ 90 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 91 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 92 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 93 { 0, FIXUP_BOARDID }, 94 { 0, FIXUP_ARGPTR_LO }, 95 { 0, FIXUP_ENTRYPOINT_LO }, 96 { 0, FIXUP_TERMINATOR } 97 }; 98 99 /* Handling for secondary CPU boot in a multicore system. 100 * Unlike the uniprocessor/primary CPU boot, this is platform 101 * dependent. The default code here is based on the secondary 102 * CPU boot protocol used on realview/vexpress boards, with 103 * some parameterisation to increase its flexibility. 104 * QEMU platform models for which this code is not appropriate 105 * should override write_secondary_boot and secondary_cpu_reset_hook 106 * instead. 107 * 108 * This code enables the interrupt controllers for the secondary 109 * CPUs and then puts all the secondary CPUs into a loop waiting 110 * for an interprocessor interrupt and polling a configurable 111 * location for the kernel secondary CPU entry point. 112 */ 113 #define DSB_INSN 0xf57ff04f 114 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 115 116 static const ARMInsnFixup smpboot[] = { 117 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 118 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 119 { 0xe3a01001 }, /* mov r1, #1 */ 120 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 121 { 0xe3a010ff }, /* mov r1, #0xff */ 122 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 123 { 0, FIXUP_DSB }, /* dsb */ 124 { 0xe320f003 }, /* wfi */ 125 { 0xe5901000 }, /* ldr r1, [r0] */ 126 { 0xe1110001 }, /* tst r1, r1 */ 127 { 0x0afffffb }, /* beq <wfi> */ 128 { 0xe12fff11 }, /* bx r1 */ 129 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 130 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 131 { 0, FIXUP_TERMINATOR } 132 }; 133 134 void arm_write_bootloader(const char *name, 135 AddressSpace *as, hwaddr addr, 136 const ARMInsnFixup *insns, 137 const uint32_t *fixupcontext) 138 { 139 /* Fix up the specified bootloader fragment and write it into 140 * guest memory using rom_add_blob_fixed(). fixupcontext is 141 * an array giving the values to write in for the fixup types 142 * which write a value into the code array. 143 */ 144 int i, len; 145 uint32_t *code; 146 147 len = 0; 148 while (insns[len].fixup != FIXUP_TERMINATOR) { 149 len++; 150 } 151 152 code = g_new0(uint32_t, len); 153 154 for (i = 0; i < len; i++) { 155 uint32_t insn = insns[i].insn; 156 FixupType fixup = insns[i].fixup; 157 158 switch (fixup) { 159 case FIXUP_NONE: 160 break; 161 case FIXUP_BOARDID: 162 case FIXUP_BOARD_SETUP: 163 case FIXUP_ARGPTR_LO: 164 case FIXUP_ARGPTR_HI: 165 case FIXUP_ENTRYPOINT_LO: 166 case FIXUP_ENTRYPOINT_HI: 167 case FIXUP_GIC_CPU_IF: 168 case FIXUP_BOOTREG: 169 case FIXUP_DSB: 170 insn = fixupcontext[fixup]; 171 break; 172 default: 173 abort(); 174 } 175 code[i] = tswap32(insn); 176 } 177 178 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 179 180 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 181 182 g_free(code); 183 } 184 185 static void default_write_secondary(ARMCPU *cpu, 186 const struct arm_boot_info *info) 187 { 188 uint32_t fixupcontext[FIXUP_MAX]; 189 AddressSpace *as = arm_boot_address_space(cpu, info); 190 191 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 192 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 193 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 194 fixupcontext[FIXUP_DSB] = DSB_INSN; 195 } else { 196 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 197 } 198 199 arm_write_bootloader("smpboot", as, info->smp_loader_start, 200 smpboot, fixupcontext); 201 } 202 203 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 204 const struct arm_boot_info *info, 205 hwaddr mvbar_addr) 206 { 207 AddressSpace *as = arm_boot_address_space(cpu, info); 208 int n; 209 uint32_t mvbar_blob[] = { 210 /* mvbar_addr: secure monitor vectors 211 * Default unimplemented and unused vectors to spin. Makes it 212 * easier to debug (as opposed to the CPU running away). 213 */ 214 0xeafffffe, /* (spin) */ 215 0xeafffffe, /* (spin) */ 216 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 217 0xeafffffe, /* (spin) */ 218 0xeafffffe, /* (spin) */ 219 0xeafffffe, /* (spin) */ 220 0xeafffffe, /* (spin) */ 221 0xeafffffe, /* (spin) */ 222 }; 223 uint32_t board_setup_blob[] = { 224 /* board setup addr */ 225 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ 226 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ 227 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ 228 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 229 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 230 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 231 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 232 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 233 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 234 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 235 0xe1a0f001, /* mov pc, r1 ;return */ 236 }; 237 238 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 239 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 240 241 /* check that these blobs don't overlap */ 242 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 243 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 244 245 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 246 mvbar_blob[n] = tswap32(mvbar_blob[n]); 247 } 248 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 249 mvbar_addr, as); 250 251 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 252 board_setup_blob[n] = tswap32(board_setup_blob[n]); 253 } 254 rom_add_blob_fixed_as("board-setup", board_setup_blob, 255 sizeof(board_setup_blob), info->board_setup_addr, as); 256 } 257 258 static void default_reset_secondary(ARMCPU *cpu, 259 const struct arm_boot_info *info) 260 { 261 AddressSpace *as = arm_boot_address_space(cpu, info); 262 CPUState *cs = CPU(cpu); 263 264 address_space_stl_notdirty(as, info->smp_bootreg_addr, 265 0, MEMTXATTRS_UNSPECIFIED, NULL); 266 cpu_set_pc(cs, info->smp_loader_start); 267 } 268 269 static inline bool have_dtb(const struct arm_boot_info *info) 270 { 271 return info->dtb_filename || info->get_dtb; 272 } 273 274 #define WRITE_WORD(p, value) do { \ 275 address_space_stl_notdirty(as, p, value, \ 276 MEMTXATTRS_UNSPECIFIED, NULL); \ 277 p += 4; \ 278 } while (0) 279 280 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 281 { 282 int initrd_size = info->initrd_size; 283 hwaddr base = info->loader_start; 284 hwaddr p; 285 286 p = base + KERNEL_ARGS_ADDR; 287 /* ATAG_CORE */ 288 WRITE_WORD(p, 5); 289 WRITE_WORD(p, 0x54410001); 290 WRITE_WORD(p, 1); 291 WRITE_WORD(p, 0x1000); 292 WRITE_WORD(p, 0); 293 /* ATAG_MEM */ 294 /* TODO: handle multiple chips on one ATAG list */ 295 WRITE_WORD(p, 4); 296 WRITE_WORD(p, 0x54410002); 297 WRITE_WORD(p, info->ram_size); 298 WRITE_WORD(p, info->loader_start); 299 if (initrd_size) { 300 /* ATAG_INITRD2 */ 301 WRITE_WORD(p, 4); 302 WRITE_WORD(p, 0x54420005); 303 WRITE_WORD(p, info->initrd_start); 304 WRITE_WORD(p, initrd_size); 305 } 306 if (info->kernel_cmdline && *info->kernel_cmdline) { 307 /* ATAG_CMDLINE */ 308 int cmdline_size; 309 310 cmdline_size = strlen(info->kernel_cmdline); 311 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 312 info->kernel_cmdline, cmdline_size + 1); 313 cmdline_size = (cmdline_size >> 2) + 1; 314 WRITE_WORD(p, cmdline_size + 2); 315 WRITE_WORD(p, 0x54410009); 316 p += cmdline_size * 4; 317 } 318 if (info->atag_board) { 319 /* ATAG_BOARD */ 320 int atag_board_len; 321 uint8_t atag_board_buf[0x1000]; 322 323 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 324 WRITE_WORD(p, (atag_board_len + 8) >> 2); 325 WRITE_WORD(p, 0x414f4d50); 326 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 327 atag_board_buf, atag_board_len); 328 p += atag_board_len; 329 } 330 /* ATAG_END */ 331 WRITE_WORD(p, 0); 332 WRITE_WORD(p, 0); 333 } 334 335 static void set_kernel_args_old(const struct arm_boot_info *info, 336 AddressSpace *as) 337 { 338 hwaddr p; 339 const char *s; 340 int initrd_size = info->initrd_size; 341 hwaddr base = info->loader_start; 342 343 /* see linux/include/asm-arm/setup.h */ 344 p = base + KERNEL_ARGS_ADDR; 345 /* page_size */ 346 WRITE_WORD(p, 4096); 347 /* nr_pages */ 348 WRITE_WORD(p, info->ram_size / 4096); 349 /* ramdisk_size */ 350 WRITE_WORD(p, 0); 351 #define FLAG_READONLY 1 352 #define FLAG_RDLOAD 4 353 #define FLAG_RDPROMPT 8 354 /* flags */ 355 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 356 /* rootdev */ 357 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 358 /* video_num_cols */ 359 WRITE_WORD(p, 0); 360 /* video_num_rows */ 361 WRITE_WORD(p, 0); 362 /* video_x */ 363 WRITE_WORD(p, 0); 364 /* video_y */ 365 WRITE_WORD(p, 0); 366 /* memc_control_reg */ 367 WRITE_WORD(p, 0); 368 /* unsigned char sounddefault */ 369 /* unsigned char adfsdrives */ 370 /* unsigned char bytes_per_char_h */ 371 /* unsigned char bytes_per_char_v */ 372 WRITE_WORD(p, 0); 373 /* pages_in_bank[4] */ 374 WRITE_WORD(p, 0); 375 WRITE_WORD(p, 0); 376 WRITE_WORD(p, 0); 377 WRITE_WORD(p, 0); 378 /* pages_in_vram */ 379 WRITE_WORD(p, 0); 380 /* initrd_start */ 381 if (initrd_size) { 382 WRITE_WORD(p, info->initrd_start); 383 } else { 384 WRITE_WORD(p, 0); 385 } 386 /* initrd_size */ 387 WRITE_WORD(p, initrd_size); 388 /* rd_start */ 389 WRITE_WORD(p, 0); 390 /* system_rev */ 391 WRITE_WORD(p, 0); 392 /* system_serial_low */ 393 WRITE_WORD(p, 0); 394 /* system_serial_high */ 395 WRITE_WORD(p, 0); 396 /* mem_fclk_21285 */ 397 WRITE_WORD(p, 0); 398 /* zero unused fields */ 399 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 400 WRITE_WORD(p, 0); 401 } 402 s = info->kernel_cmdline; 403 if (s) { 404 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1); 405 } else { 406 WRITE_WORD(p, 0); 407 } 408 } 409 410 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, 411 uint32_t scells, hwaddr mem_len, 412 int numa_node_id) 413 { 414 char *nodename; 415 int ret; 416 417 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 418 qemu_fdt_add_subnode(fdt, nodename); 419 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 420 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base, 421 scells, mem_len); 422 if (ret < 0) { 423 goto out; 424 } 425 426 /* only set the NUMA ID if it is specified */ 427 if (numa_node_id >= 0) { 428 ret = qemu_fdt_setprop_cell(fdt, nodename, 429 "numa-node-id", numa_node_id); 430 } 431 out: 432 g_free(nodename); 433 return ret; 434 } 435 436 static void fdt_add_psci_node(void *fdt, ARMCPU *armcpu) 437 { 438 uint32_t cpu_suspend_fn; 439 uint32_t cpu_off_fn; 440 uint32_t cpu_on_fn; 441 uint32_t migrate_fn; 442 const char *psci_method; 443 int64_t psci_conduit; 444 int rc; 445 446 psci_conduit = object_property_get_int(OBJECT(armcpu), 447 "psci-conduit", 448 &error_abort); 449 switch (psci_conduit) { 450 case QEMU_PSCI_CONDUIT_DISABLED: 451 return; 452 case QEMU_PSCI_CONDUIT_HVC: 453 psci_method = "hvc"; 454 break; 455 case QEMU_PSCI_CONDUIT_SMC: 456 psci_method = "smc"; 457 break; 458 default: 459 g_assert_not_reached(); 460 } 461 462 /* 463 * A pre-existing /psci node might specify function ID values 464 * that don't match QEMU's PSCI implementation. Delete the whole 465 * node and put our own in instead. 466 */ 467 rc = fdt_path_offset(fdt, "/psci"); 468 if (rc >= 0) { 469 qemu_fdt_nop_node(fdt, "/psci"); 470 } 471 472 qemu_fdt_add_subnode(fdt, "/psci"); 473 if (armcpu->psci_version >= QEMU_PSCI_VERSION_0_2) { 474 if (armcpu->psci_version < QEMU_PSCI_VERSION_1_0) { 475 const char comp[] = "arm,psci-0.2\0arm,psci"; 476 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 477 } else { 478 const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci"; 479 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 480 } 481 482 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 483 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 484 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 485 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 486 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 487 } else { 488 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 489 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 490 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 491 } 492 } else { 493 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 494 495 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 496 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 497 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 498 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 499 } 500 501 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 502 * to the instruction that should be used to invoke PSCI functions. 503 * However, the device tree binding uses 'method' instead, so that is 504 * what we should use here. 505 */ 506 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 507 508 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 509 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 510 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 511 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 512 } 513 514 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 515 hwaddr addr_limit, AddressSpace *as, MachineState *ms, 516 ARMCPU *cpu) 517 { 518 void *fdt = NULL; 519 int size, rc, n = 0; 520 uint32_t acells, scells; 521 unsigned int i; 522 hwaddr mem_base, mem_len; 523 char **node_path; 524 Error *err = NULL; 525 526 if (binfo->dtb_filename) { 527 char *filename; 528 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 529 if (!filename) { 530 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 531 goto fail; 532 } 533 534 fdt = load_device_tree(filename, &size); 535 if (!fdt) { 536 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 537 g_free(filename); 538 goto fail; 539 } 540 g_free(filename); 541 } else { 542 fdt = binfo->get_dtb(binfo, &size); 543 if (!fdt) { 544 fprintf(stderr, "Board was unable to create a dtb blob\n"); 545 goto fail; 546 } 547 } 548 549 if (addr_limit > addr && size > (addr_limit - addr)) { 550 /* Installing the device tree blob at addr would exceed addr_limit. 551 * Whether this constitutes failure is up to the caller to decide, 552 * so just return 0 as size, i.e., no error. 553 */ 554 g_free(fdt); 555 return 0; 556 } 557 558 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 559 NULL, &error_fatal); 560 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 561 NULL, &error_fatal); 562 if (acells == 0 || scells == 0) { 563 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 564 goto fail; 565 } 566 567 if (scells < 2 && binfo->ram_size >= 4 * GiB) { 568 /* This is user error so deserves a friendlier error message 569 * than the failure of setprop_sized_cells would provide 570 */ 571 fprintf(stderr, "qemu: dtb file not compatible with " 572 "RAM size > 4GB\n"); 573 goto fail; 574 } 575 576 /* nop all root nodes matching /memory or /memory@unit-address */ 577 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 578 if (err) { 579 error_report_err(err); 580 goto fail; 581 } 582 while (node_path[n]) { 583 if (g_str_has_prefix(node_path[n], "/memory")) { 584 qemu_fdt_nop_node(fdt, node_path[n]); 585 } 586 n++; 587 } 588 g_strfreev(node_path); 589 590 /* 591 * We drop all the memory nodes which correspond to empty NUMA nodes 592 * from the device tree, because the Linux NUMA binding document 593 * states they should not be generated. Linux will get the NUMA node 594 * IDs of the empty NUMA nodes from the distance map if they are needed. 595 * This means QEMU users may be obliged to provide command lines which 596 * configure distance maps when the empty NUMA node IDs are needed and 597 * Linux's default distance map isn't sufficient. 598 */ 599 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) { 600 mem_base = binfo->loader_start; 601 for (i = 0; i < ms->numa_state->num_nodes; i++) { 602 mem_len = ms->numa_state->nodes[i].node_mem; 603 if (!mem_len) { 604 continue; 605 } 606 607 rc = fdt_add_memory_node(fdt, acells, mem_base, 608 scells, mem_len, i); 609 if (rc < 0) { 610 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 611 mem_base); 612 goto fail; 613 } 614 615 mem_base += mem_len; 616 } 617 } else { 618 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start, 619 scells, binfo->ram_size, -1); 620 if (rc < 0) { 621 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 622 binfo->loader_start); 623 goto fail; 624 } 625 } 626 627 rc = fdt_path_offset(fdt, "/chosen"); 628 if (rc < 0) { 629 qemu_fdt_add_subnode(fdt, "/chosen"); 630 } 631 632 if (ms->kernel_cmdline && *ms->kernel_cmdline) { 633 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 634 ms->kernel_cmdline); 635 if (rc < 0) { 636 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 637 goto fail; 638 } 639 } 640 641 if (binfo->initrd_size) { 642 rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start", 643 acells, binfo->initrd_start); 644 if (rc < 0) { 645 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 646 goto fail; 647 } 648 649 rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end", 650 acells, 651 binfo->initrd_start + 652 binfo->initrd_size); 653 if (rc < 0) { 654 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 655 goto fail; 656 } 657 } 658 659 fdt_add_psci_node(fdt, cpu); 660 661 if (binfo->modify_dtb) { 662 binfo->modify_dtb(binfo, fdt); 663 } 664 665 /* Put the DTB into the memory map as a ROM image: this will ensure 666 * the DTB is copied again upon reset, even if addr points into RAM. 667 */ 668 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 669 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 670 rom_ptr_for_as(as, addr, size)); 671 672 if (fdt != ms->fdt) { 673 g_free(ms->fdt); 674 ms->fdt = fdt; 675 } 676 677 return size; 678 679 fail: 680 g_free(fdt); 681 return -1; 682 } 683 684 static void do_cpu_reset(void *opaque) 685 { 686 ARMCPU *cpu = opaque; 687 CPUState *cs = CPU(cpu); 688 CPUARMState *env = &cpu->env; 689 const struct arm_boot_info *info = env->boot_info; 690 691 cpu_reset(cs); 692 if (info) { 693 if (!info->is_linux) { 694 int i; 695 /* Jump to the entry point. */ 696 uint64_t entry = info->entry; 697 698 switch (info->endianness) { 699 case ARM_ENDIANNESS_LE: 700 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 701 for (i = 1; i < 4; ++i) { 702 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 703 } 704 env->uncached_cpsr &= ~CPSR_E; 705 break; 706 case ARM_ENDIANNESS_BE8: 707 env->cp15.sctlr_el[1] |= SCTLR_E0E; 708 for (i = 1; i < 4; ++i) { 709 env->cp15.sctlr_el[i] |= SCTLR_EE; 710 } 711 env->uncached_cpsr |= CPSR_E; 712 break; 713 case ARM_ENDIANNESS_BE32: 714 env->cp15.sctlr_el[1] |= SCTLR_B; 715 break; 716 case ARM_ENDIANNESS_UNKNOWN: 717 break; /* Board's decision */ 718 default: 719 g_assert_not_reached(); 720 } 721 722 cpu_set_pc(cs, entry); 723 } else { 724 /* 725 * If we are booting Linux then we might need to do so at: 726 * - AArch64 NS EL2 or NS EL1 727 * - AArch32 Secure SVC (EL3) 728 * - AArch32 NS Hyp (EL2) 729 * - AArch32 NS SVC (EL1) 730 * Configure the CPU in the way boot firmware would do to 731 * drop us down to the appropriate level. 732 */ 733 int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; 734 735 if (env->aarch64) { 736 /* 737 * AArch64 kernels never boot in secure mode, and we don't 738 * support the secure_board_setup hook for AArch64. 739 */ 740 assert(!info->secure_boot); 741 assert(!info->secure_board_setup); 742 } else { 743 if (arm_feature(env, ARM_FEATURE_EL3) && 744 (info->secure_boot || 745 (info->secure_board_setup && cs == first_cpu))) { 746 /* Start this CPU in Secure SVC */ 747 target_el = 3; 748 } 749 } 750 751 arm_emulate_firmware_reset(cs, target_el); 752 753 if (cs == first_cpu) { 754 AddressSpace *as = arm_boot_address_space(cpu, info); 755 756 cpu_set_pc(cs, info->loader_start); 757 758 if (!have_dtb(info)) { 759 if (old_param) { 760 set_kernel_args_old(info, as); 761 } else { 762 set_kernel_args(info, as); 763 } 764 } 765 } else if (info->secondary_cpu_reset_hook) { 766 info->secondary_cpu_reset_hook(cpu, info); 767 } 768 } 769 770 if (tcg_enabled()) { 771 arm_rebuild_hflags(env); 772 } 773 } 774 } 775 776 static int do_arm_linux_init(Object *obj, void *opaque) 777 { 778 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 779 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 780 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 781 struct arm_boot_info *info = opaque; 782 783 if (albifc->arm_linux_init) { 784 albifc->arm_linux_init(albif, info->secure_boot); 785 } 786 } 787 return 0; 788 } 789 790 static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 791 uint64_t *lowaddr, uint64_t *highaddr, 792 int elf_machine, AddressSpace *as) 793 { 794 bool elf_is64; 795 union { 796 Elf32_Ehdr h32; 797 Elf64_Ehdr h64; 798 } elf_header; 799 int data_swab = 0; 800 int elf_data_order; 801 ssize_t ret; 802 Error *err = NULL; 803 804 805 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 806 if (err) { 807 /* 808 * If the file is not an ELF file we silently return. 809 * The caller will fall back to try other formats. 810 */ 811 error_free(err); 812 return -1; 813 } 814 815 if (elf_is64) { 816 elf_data_order = elf_header.h64.e_ident[EI_DATA]; 817 info->endianness = elf_data_order == ELFDATA2MSB ? ARM_ENDIANNESS_BE8 818 : ARM_ENDIANNESS_LE; 819 } else { 820 elf_data_order = elf_header.h32.e_ident[EI_DATA]; 821 if (elf_data_order == ELFDATA2MSB) { 822 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 823 info->endianness = ARM_ENDIANNESS_BE8; 824 } else { 825 info->endianness = ARM_ENDIANNESS_BE32; 826 /* In BE32, the CPU has a different view of the per-byte 827 * address map than the rest of the system. BE32 ELF files 828 * are organised such that they can be programmed through 829 * the CPU's per-word byte-reversed view of the world. QEMU 830 * however loads ELF files independently of the CPU. So 831 * tell the ELF loader to byte reverse the data for us. 832 */ 833 data_swab = 2; 834 } 835 } else { 836 info->endianness = ARM_ENDIANNESS_LE; 837 } 838 } 839 840 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL, 841 pentry, lowaddr, highaddr, NULL, elf_data_order, 842 elf_machine, 1, data_swab, as); 843 if (ret <= 0) { 844 /* The header loaded but the image didn't */ 845 error_report("Couldn't load elf '%s': %s", 846 info->kernel_filename, load_elf_strerror(ret)); 847 exit(1); 848 } 849 850 return ret; 851 } 852 853 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 854 hwaddr *entry, AddressSpace *as) 855 { 856 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 857 uint64_t kernel_size = 0; 858 uint8_t *buffer; 859 ssize_t size; 860 861 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 862 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 863 &buffer); 864 865 if (size < 0) { 866 gsize len; 867 868 /* Load as raw file otherwise */ 869 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 870 return -1; 871 } 872 size = len; 873 874 /* Unpack the image if it is a EFI zboot image */ 875 if (unpack_efi_zboot_image(&buffer, &size) < 0) { 876 g_free(buffer); 877 return -1; 878 } 879 } 880 881 /* check the arm64 magic header value -- very old kernels may not have it */ 882 if (size > ARM64_MAGIC_OFFSET + 4 && 883 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 884 uint64_t hdrvals[2]; 885 886 /* The arm64 Image header has text_offset and image_size fields at 8 and 887 * 16 bytes into the Image header, respectively. The text_offset field 888 * is only valid if the image_size is non-zero. 889 */ 890 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 891 892 kernel_size = le64_to_cpu(hdrvals[1]); 893 894 if (kernel_size != 0) { 895 kernel_load_offset = le64_to_cpu(hdrvals[0]); 896 897 /* 898 * We write our startup "bootloader" at the very bottom of RAM, 899 * so that bit can't be used for the image. Luckily the Image 900 * format specification is that the image requests only an offset 901 * from a 2MB boundary, not an absolute load address. So if the 902 * image requests an offset that might mean it overlaps with the 903 * bootloader, we can just load it starting at 2MB+offset rather 904 * than 0MB + offset. 905 */ 906 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 907 kernel_load_offset += 2 * MiB; 908 } 909 } 910 } 911 912 /* 913 * Kernels before v3.17 don't populate the image_size field, and 914 * raw images have no header. For those our best guess at the size 915 * is the size of the Image file itself. 916 */ 917 if (kernel_size == 0) { 918 kernel_size = size; 919 } 920 921 *entry = mem_base + kernel_load_offset; 922 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 923 924 g_free(buffer); 925 926 return kernel_size; 927 } 928 929 static void arm_setup_direct_kernel_boot(ARMCPU *cpu, 930 struct arm_boot_info *info) 931 { 932 /* Set up for a direct boot of a kernel image file. */ 933 CPUState *cs; 934 AddressSpace *as = arm_boot_address_space(cpu, info); 935 ssize_t kernel_size; 936 int initrd_size; 937 int is_linux = 0; 938 uint64_t elf_entry; 939 /* Addresses of first byte used and first byte not used by the image */ 940 uint64_t image_low_addr = 0, image_high_addr = 0; 941 int elf_machine; 942 hwaddr entry; 943 static const ARMInsnFixup *primary_loader; 944 uint64_t ram_end = info->loader_start + info->ram_size; 945 946 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 947 primary_loader = bootloader_aarch64; 948 elf_machine = EM_AARCH64; 949 } else { 950 primary_loader = bootloader; 951 if (!info->write_board_setup) { 952 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 953 } 954 elf_machine = EM_ARM; 955 } 956 957 /* Assume that raw images are linux kernels, and ELF images are not. */ 958 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr, 959 &image_high_addr, elf_machine, as); 960 if (kernel_size > 0 && have_dtb(info)) { 961 /* 962 * If there is still some room left at the base of RAM, try and put 963 * the DTB there like we do for images loaded with -bios or -pflash. 964 */ 965 if (image_low_addr > info->loader_start 966 || image_high_addr < info->loader_start) { 967 /* 968 * Set image_low_addr as address limit for arm_load_dtb if it may be 969 * pointing into RAM, otherwise pass '0' (no limit) 970 */ 971 if (image_low_addr < info->loader_start) { 972 image_low_addr = 0; 973 } 974 info->dtb_start = info->loader_start; 975 info->dtb_limit = image_low_addr; 976 } 977 } 978 entry = elf_entry; 979 if (kernel_size < 0) { 980 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; 981 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, 982 &is_linux, NULL, NULL, as); 983 if (kernel_size >= 0) { 984 image_low_addr = loadaddr; 985 image_high_addr = image_low_addr + kernel_size; 986 } 987 } 988 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 989 kernel_size = load_aarch64_image(info->kernel_filename, 990 info->loader_start, &entry, as); 991 is_linux = 1; 992 if (kernel_size >= 0) { 993 image_low_addr = entry; 994 image_high_addr = image_low_addr + kernel_size; 995 } 996 } else if (kernel_size < 0) { 997 /* 32-bit ARM */ 998 entry = info->loader_start + KERNEL_LOAD_ADDR; 999 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1000 ram_end - KERNEL_LOAD_ADDR, as); 1001 is_linux = 1; 1002 if (kernel_size >= 0) { 1003 image_low_addr = entry; 1004 image_high_addr = image_low_addr + kernel_size; 1005 } 1006 } 1007 if (kernel_size < 0) { 1008 error_report("could not load kernel '%s'", info->kernel_filename); 1009 exit(1); 1010 } 1011 1012 if (kernel_size > info->ram_size) { 1013 error_report("kernel '%s' is too large to fit in RAM " 1014 "(kernel size %zd, RAM size %" PRId64 ")", 1015 info->kernel_filename, kernel_size, info->ram_size); 1016 exit(1); 1017 } 1018 1019 info->entry = entry; 1020 1021 /* 1022 * We want to put the initrd far enough into RAM that when the 1023 * kernel is uncompressed it will not clobber the initrd. However 1024 * on boards without much RAM we must ensure that we still leave 1025 * enough room for a decent sized initrd, and on boards with large 1026 * amounts of RAM we must avoid the initrd being so far up in RAM 1027 * that it is outside lowmem and inaccessible to the kernel. 1028 * So for boards with less than 256MB of RAM we put the initrd 1029 * halfway into RAM, and for boards with 256MB of RAM or more we put 1030 * the initrd at 128MB. 1031 * We also refuse to put the initrd somewhere that will definitely 1032 * overlay the kernel we just loaded, though for kernel formats which 1033 * don't tell us their exact size (eg self-decompressing 32-bit kernels) 1034 * we might still make a bad choice here. 1035 */ 1036 info->initrd_start = info->loader_start + 1037 MIN(info->ram_size / 2, 128 * MiB); 1038 if (image_high_addr) { 1039 info->initrd_start = MAX(info->initrd_start, image_high_addr); 1040 } 1041 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); 1042 1043 if (is_linux) { 1044 uint32_t fixupcontext[FIXUP_MAX]; 1045 1046 if (info->initrd_filename) { 1047 1048 if (info->initrd_start >= ram_end) { 1049 error_report("not enough space after kernel to load initrd"); 1050 exit(1); 1051 } 1052 1053 initrd_size = load_ramdisk_as(info->initrd_filename, 1054 info->initrd_start, 1055 ram_end - info->initrd_start, as); 1056 if (initrd_size < 0) { 1057 initrd_size = load_image_targphys_as(info->initrd_filename, 1058 info->initrd_start, 1059 ram_end - 1060 info->initrd_start, 1061 as); 1062 } 1063 if (initrd_size < 0) { 1064 error_report("could not load initrd '%s'", 1065 info->initrd_filename); 1066 exit(1); 1067 } 1068 if (info->initrd_start + initrd_size > ram_end) { 1069 error_report("could not load initrd '%s': " 1070 "too big to fit into RAM after the kernel", 1071 info->initrd_filename); 1072 exit(1); 1073 } 1074 } else { 1075 initrd_size = 0; 1076 } 1077 info->initrd_size = initrd_size; 1078 1079 fixupcontext[FIXUP_BOARDID] = info->board_id; 1080 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1081 1082 /* 1083 * for device tree boot, we pass the DTB directly in r2. Otherwise 1084 * we point to the kernel args. 1085 */ 1086 if (have_dtb(info)) { 1087 hwaddr align; 1088 1089 if (elf_machine == EM_AARCH64) { 1090 /* 1091 * Some AArch64 kernels on early bootup map the fdt region as 1092 * 1093 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1094 * 1095 * Let's play safe and prealign it to 2MB to give us some space. 1096 */ 1097 align = 2 * MiB; 1098 } else { 1099 /* 1100 * Some 32bit kernels will trash anything in the 4K page the 1101 * initrd ends in, so make sure the DTB isn't caught up in that. 1102 */ 1103 align = 4 * KiB; 1104 } 1105 1106 /* Place the DTB after the initrd in memory with alignment. */ 1107 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1108 align); 1109 if (info->dtb_start >= ram_end) { 1110 error_report("Not enough space for DTB after kernel/initrd"); 1111 exit(1); 1112 } 1113 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; 1114 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; 1115 } else { 1116 fixupcontext[FIXUP_ARGPTR_LO] = 1117 info->loader_start + KERNEL_ARGS_ADDR; 1118 fixupcontext[FIXUP_ARGPTR_HI] = 1119 (info->loader_start + KERNEL_ARGS_ADDR) >> 32; 1120 if (info->ram_size >= 4 * GiB) { 1121 error_report("RAM size must be less than 4GB to boot" 1122 " Linux kernel using ATAGS (try passing a device tree" 1123 " using -dtb)"); 1124 exit(1); 1125 } 1126 } 1127 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; 1128 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; 1129 1130 arm_write_bootloader("bootloader", as, info->loader_start, 1131 primary_loader, fixupcontext); 1132 1133 if (info->write_board_setup) { 1134 info->write_board_setup(cpu, info); 1135 } 1136 1137 /* 1138 * Notify devices which need to fake up firmware initialization 1139 * that we're doing a direct kernel boot. 1140 */ 1141 object_child_foreach_recursive(object_get_root(), 1142 do_arm_linux_init, info); 1143 } 1144 info->is_linux = is_linux; 1145 1146 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1147 ARM_CPU(cs)->env.boot_info = info; 1148 } 1149 } 1150 1151 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) 1152 { 1153 /* Set up for booting firmware (which might load a kernel via fw_cfg) */ 1154 1155 if (have_dtb(info)) { 1156 /* 1157 * If we have a device tree blob, but no kernel to supply it to (or 1158 * the kernel is supposed to be loaded by the bootloader), copy the 1159 * DTB to the base of RAM for the bootloader to pick up. 1160 */ 1161 info->dtb_start = info->loader_start; 1162 } 1163 1164 if (info->kernel_filename) { 1165 FWCfgState *fw_cfg; 1166 bool try_decompressing_kernel; 1167 1168 fw_cfg = fw_cfg_find(); 1169 1170 if (!fw_cfg) { 1171 error_report("This machine type does not support loading both " 1172 "a guest firmware/BIOS image and a guest kernel at " 1173 "the same time. You should change your QEMU command " 1174 "line to specify one or the other, but not both."); 1175 exit(1); 1176 } 1177 1178 try_decompressing_kernel = arm_feature(&cpu->env, 1179 ARM_FEATURE_AARCH64); 1180 1181 /* 1182 * Expose the kernel, the command line, and the initrd in fw_cfg. 1183 * We don't process them here at all, it's all left to the 1184 * firmware. 1185 */ 1186 load_image_to_fw_cfg(fw_cfg, 1187 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1188 info->kernel_filename, 1189 try_decompressing_kernel); 1190 load_image_to_fw_cfg(fw_cfg, 1191 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1192 info->initrd_filename, false); 1193 1194 if (info->kernel_cmdline) { 1195 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1196 strlen(info->kernel_cmdline) + 1); 1197 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1198 info->kernel_cmdline); 1199 } 1200 } 1201 1202 /* 1203 * We will start from address 0 (typically a boot ROM image) in the 1204 * same way as hardware. Leave env->boot_info NULL, so that 1205 * do_cpu_reset() knows it does not need to alter the PC on reset. 1206 */ 1207 } 1208 1209 void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) 1210 { 1211 CPUState *cs; 1212 AddressSpace *as = arm_boot_address_space(cpu, info); 1213 int boot_el; 1214 CPUARMState *env = &cpu->env; 1215 int nb_cpus = 0; 1216 1217 /* 1218 * CPU objects (unlike devices) are not automatically reset on system 1219 * reset, so we must always register a handler to do so. If we're 1220 * actually loading a kernel, the handler is also responsible for 1221 * arranging that we start it correctly. 1222 */ 1223 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1224 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1225 nb_cpus++; 1226 } 1227 1228 /* 1229 * The board code is not supposed to set secure_board_setup unless 1230 * running its code in secure mode is actually possible, and KVM 1231 * doesn't support secure. 1232 */ 1233 assert(!(info->secure_board_setup && kvm_enabled())); 1234 info->kernel_filename = ms->kernel_filename; 1235 info->kernel_cmdline = ms->kernel_cmdline; 1236 info->initrd_filename = ms->initrd_filename; 1237 info->dtb_filename = ms->dtb; 1238 info->dtb_limit = 0; 1239 1240 /* Load the kernel. */ 1241 if (!info->kernel_filename || info->firmware_loaded) { 1242 arm_setup_firmware_boot(cpu, info); 1243 } else { 1244 arm_setup_direct_kernel_boot(cpu, info); 1245 } 1246 1247 /* 1248 * Disable the PSCI conduit if it is set up to target the same 1249 * or a lower EL than the one we're going to start the guest code in. 1250 * This logic needs to agree with the code in do_cpu_reset() which 1251 * decides whether we're going to boot the guest in the highest 1252 * supported exception level or in a lower one. 1253 */ 1254 1255 /* 1256 * If PSCI is enabled, then SMC calls all go to the PSCI handler and 1257 * are never emulated to trap into guest code. It therefore does not 1258 * make sense for the board to have a setup code fragment that runs 1259 * in Secure, because this will probably need to itself issue an SMC of some 1260 * kind as part of its operation. 1261 */ 1262 assert(info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED || 1263 !info->secure_board_setup); 1264 1265 /* Boot into highest supported EL ... */ 1266 if (arm_feature(env, ARM_FEATURE_EL3)) { 1267 boot_el = 3; 1268 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 1269 boot_el = 2; 1270 } else { 1271 boot_el = 1; 1272 } 1273 /* ...except that if we're booting Linux we adjust the EL we boot into */ 1274 if (info->is_linux && !info->secure_boot) { 1275 boot_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; 1276 } 1277 1278 if ((info->psci_conduit == QEMU_PSCI_CONDUIT_HVC && boot_el >= 2) || 1279 (info->psci_conduit == QEMU_PSCI_CONDUIT_SMC && boot_el == 3)) { 1280 info->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1281 } 1282 1283 if (info->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1284 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1285 Object *cpuobj = OBJECT(cs); 1286 1287 object_property_set_int(cpuobj, "psci-conduit", info->psci_conduit, 1288 &error_abort); 1289 /* 1290 * Secondary CPUs start in PSCI powered-down state. Like the 1291 * code in do_cpu_reset(), we assume first_cpu is the primary 1292 * CPU. 1293 */ 1294 if (cs != first_cpu) { 1295 object_property_set_bool(cpuobj, "start-powered-off", true, 1296 &error_abort); 1297 } 1298 } 1299 } 1300 1301 if (info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED && 1302 info->is_linux && nb_cpus > 1) { 1303 /* 1304 * We're booting Linux but not using PSCI, so for SMP we need 1305 * to write a custom secondary CPU boot loader stub, and arrange 1306 * for the secondary CPU reset to make the accompanying initialization. 1307 */ 1308 if (!info->secondary_cpu_reset_hook) { 1309 info->secondary_cpu_reset_hook = default_reset_secondary; 1310 } 1311 if (!info->write_secondary_boot) { 1312 info->write_secondary_boot = default_write_secondary; 1313 } 1314 info->write_secondary_boot(cpu, info); 1315 } else { 1316 /* 1317 * No secondary boot stub; don't use the reset hook that would 1318 * have set the CPU up to call it 1319 */ 1320 info->write_secondary_boot = NULL; 1321 info->secondary_cpu_reset_hook = NULL; 1322 } 1323 1324 /* 1325 * arm_load_dtb() may add a PSCI node so it must be called after we have 1326 * decided whether to enable PSCI and set the psci-conduit CPU properties. 1327 */ 1328 if (!info->skip_dtb_autoload && have_dtb(info)) { 1329 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, 1330 as, ms, cpu) < 0) { 1331 exit(1); 1332 } 1333 } 1334 } 1335 1336 static const TypeInfo arm_linux_boot_if_info = { 1337 .name = TYPE_ARM_LINUX_BOOT_IF, 1338 .parent = TYPE_INTERFACE, 1339 .class_size = sizeof(ARMLinuxBootIfClass), 1340 }; 1341 1342 static void arm_linux_boot_register_types(void) 1343 { 1344 type_register_static(&arm_linux_boot_if_info); 1345 } 1346 1347 type_init(arm_linux_boot_register_types) 1348