1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/error-report.h" 12 #include "qapi/error.h" 13 #include <libfdt.h> 14 #include "hw/hw.h" 15 #include "hw/arm/arm.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "sysemu/kvm.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/numa.h" 20 #include "hw/boards.h" 21 #include "hw/loader.h" 22 #include "elf.h" 23 #include "sysemu/device_tree.h" 24 #include "qemu/config-file.h" 25 #include "qemu/option.h" 26 #include "exec/address-spaces.h" 27 28 /* Kernel boot protocol is specified in the kernel docs 29 * Documentation/arm/Booting and Documentation/arm64/booting.txt 30 * They have different preferred image load offsets from system RAM base. 31 */ 32 #define KERNEL_ARGS_ADDR 0x100 33 #define KERNEL_LOAD_ADDR 0x00010000 34 #define KERNEL64_LOAD_ADDR 0x00080000 35 36 #define ARM64_TEXT_OFFSET_OFFSET 8 37 #define ARM64_MAGIC_OFFSET 56 38 39 static AddressSpace *arm_boot_address_space(ARMCPU *cpu, 40 const struct arm_boot_info *info) 41 { 42 /* Return the address space to use for bootloader reads and writes. 43 * We prefer the secure address space if the CPU has it and we're 44 * going to boot the guest into it. 45 */ 46 int asidx; 47 CPUState *cs = CPU(cpu); 48 49 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 50 asidx = ARMASIdx_S; 51 } else { 52 asidx = ARMASIdx_NS; 53 } 54 55 return cpu_get_address_space(cs, asidx); 56 } 57 58 typedef enum { 59 FIXUP_NONE = 0, /* do nothing */ 60 FIXUP_TERMINATOR, /* end of insns */ 61 FIXUP_BOARDID, /* overwrite with board ID number */ 62 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 63 FIXUP_ARGPTR, /* overwrite with pointer to kernel args */ 64 FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */ 65 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 66 FIXUP_BOOTREG, /* overwrite with boot register address */ 67 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 68 FIXUP_MAX, 69 } FixupType; 70 71 typedef struct ARMInsnFixup { 72 uint32_t insn; 73 FixupType fixup; 74 } ARMInsnFixup; 75 76 static const ARMInsnFixup bootloader_aarch64[] = { 77 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 78 { 0xaa1f03e1 }, /* mov x1, xzr */ 79 { 0xaa1f03e2 }, /* mov x2, xzr */ 80 { 0xaa1f03e3 }, /* mov x3, xzr */ 81 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 82 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 83 { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */ 84 { 0 }, /* .word @DTB Higher 32-bits */ 85 { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */ 86 { 0 }, /* .word @Kernel Entry Higher 32-bits */ 87 { 0, FIXUP_TERMINATOR } 88 }; 89 90 /* A very small bootloader: call the board-setup code (if needed), 91 * set r0-r2, then jump to the kernel. 92 * If we're not calling boot setup code then we don't copy across 93 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 94 */ 95 96 static const ARMInsnFixup bootloader[] = { 97 { 0xe28fe004 }, /* add lr, pc, #4 */ 98 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 99 { 0, FIXUP_BOARD_SETUP }, 100 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 101 { 0xe3a00000 }, /* mov r0, #0 */ 102 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 103 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 104 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 105 { 0, FIXUP_BOARDID }, 106 { 0, FIXUP_ARGPTR }, 107 { 0, FIXUP_ENTRYPOINT }, 108 { 0, FIXUP_TERMINATOR } 109 }; 110 111 /* Handling for secondary CPU boot in a multicore system. 112 * Unlike the uniprocessor/primary CPU boot, this is platform 113 * dependent. The default code here is based on the secondary 114 * CPU boot protocol used on realview/vexpress boards, with 115 * some parameterisation to increase its flexibility. 116 * QEMU platform models for which this code is not appropriate 117 * should override write_secondary_boot and secondary_cpu_reset_hook 118 * instead. 119 * 120 * This code enables the interrupt controllers for the secondary 121 * CPUs and then puts all the secondary CPUs into a loop waiting 122 * for an interprocessor interrupt and polling a configurable 123 * location for the kernel secondary CPU entry point. 124 */ 125 #define DSB_INSN 0xf57ff04f 126 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 127 128 static const ARMInsnFixup smpboot[] = { 129 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 130 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 131 { 0xe3a01001 }, /* mov r1, #1 */ 132 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 133 { 0xe3a010ff }, /* mov r1, #0xff */ 134 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 135 { 0, FIXUP_DSB }, /* dsb */ 136 { 0xe320f003 }, /* wfi */ 137 { 0xe5901000 }, /* ldr r1, [r0] */ 138 { 0xe1110001 }, /* tst r1, r1 */ 139 { 0x0afffffb }, /* beq <wfi> */ 140 { 0xe12fff11 }, /* bx r1 */ 141 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 142 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 143 { 0, FIXUP_TERMINATOR } 144 }; 145 146 static void write_bootloader(const char *name, hwaddr addr, 147 const ARMInsnFixup *insns, uint32_t *fixupcontext, 148 AddressSpace *as) 149 { 150 /* Fix up the specified bootloader fragment and write it into 151 * guest memory using rom_add_blob_fixed(). fixupcontext is 152 * an array giving the values to write in for the fixup types 153 * which write a value into the code array. 154 */ 155 int i, len; 156 uint32_t *code; 157 158 len = 0; 159 while (insns[len].fixup != FIXUP_TERMINATOR) { 160 len++; 161 } 162 163 code = g_new0(uint32_t, len); 164 165 for (i = 0; i < len; i++) { 166 uint32_t insn = insns[i].insn; 167 FixupType fixup = insns[i].fixup; 168 169 switch (fixup) { 170 case FIXUP_NONE: 171 break; 172 case FIXUP_BOARDID: 173 case FIXUP_BOARD_SETUP: 174 case FIXUP_ARGPTR: 175 case FIXUP_ENTRYPOINT: 176 case FIXUP_GIC_CPU_IF: 177 case FIXUP_BOOTREG: 178 case FIXUP_DSB: 179 insn = fixupcontext[fixup]; 180 break; 181 default: 182 abort(); 183 } 184 code[i] = tswap32(insn); 185 } 186 187 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 188 189 g_free(code); 190 } 191 192 static void default_write_secondary(ARMCPU *cpu, 193 const struct arm_boot_info *info) 194 { 195 uint32_t fixupcontext[FIXUP_MAX]; 196 AddressSpace *as = arm_boot_address_space(cpu, info); 197 198 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 199 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 200 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 201 fixupcontext[FIXUP_DSB] = DSB_INSN; 202 } else { 203 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 204 } 205 206 write_bootloader("smpboot", info->smp_loader_start, 207 smpboot, fixupcontext, as); 208 } 209 210 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 211 const struct arm_boot_info *info, 212 hwaddr mvbar_addr) 213 { 214 AddressSpace *as = arm_boot_address_space(cpu, info); 215 int n; 216 uint32_t mvbar_blob[] = { 217 /* mvbar_addr: secure monitor vectors 218 * Default unimplemented and unused vectors to spin. Makes it 219 * easier to debug (as opposed to the CPU running away). 220 */ 221 0xeafffffe, /* (spin) */ 222 0xeafffffe, /* (spin) */ 223 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 224 0xeafffffe, /* (spin) */ 225 0xeafffffe, /* (spin) */ 226 0xeafffffe, /* (spin) */ 227 0xeafffffe, /* (spin) */ 228 0xeafffffe, /* (spin) */ 229 }; 230 uint32_t board_setup_blob[] = { 231 /* board setup addr */ 232 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 233 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 234 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 235 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 236 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 237 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 238 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 239 0xe1a0f001, /* mov pc, r1 ;return */ 240 }; 241 242 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 243 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 244 245 /* check that these blobs don't overlap */ 246 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 247 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 248 249 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 250 mvbar_blob[n] = tswap32(mvbar_blob[n]); 251 } 252 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 253 mvbar_addr, as); 254 255 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 256 board_setup_blob[n] = tswap32(board_setup_blob[n]); 257 } 258 rom_add_blob_fixed_as("board-setup", board_setup_blob, 259 sizeof(board_setup_blob), info->board_setup_addr, as); 260 } 261 262 static void default_reset_secondary(ARMCPU *cpu, 263 const struct arm_boot_info *info) 264 { 265 AddressSpace *as = arm_boot_address_space(cpu, info); 266 CPUState *cs = CPU(cpu); 267 268 address_space_stl_notdirty(as, info->smp_bootreg_addr, 269 0, MEMTXATTRS_UNSPECIFIED, NULL); 270 cpu_set_pc(cs, info->smp_loader_start); 271 } 272 273 static inline bool have_dtb(const struct arm_boot_info *info) 274 { 275 return info->dtb_filename || info->get_dtb; 276 } 277 278 #define WRITE_WORD(p, value) do { \ 279 address_space_stl_notdirty(as, p, value, \ 280 MEMTXATTRS_UNSPECIFIED, NULL); \ 281 p += 4; \ 282 } while (0) 283 284 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 285 { 286 int initrd_size = info->initrd_size; 287 hwaddr base = info->loader_start; 288 hwaddr p; 289 290 p = base + KERNEL_ARGS_ADDR; 291 /* ATAG_CORE */ 292 WRITE_WORD(p, 5); 293 WRITE_WORD(p, 0x54410001); 294 WRITE_WORD(p, 1); 295 WRITE_WORD(p, 0x1000); 296 WRITE_WORD(p, 0); 297 /* ATAG_MEM */ 298 /* TODO: handle multiple chips on one ATAG list */ 299 WRITE_WORD(p, 4); 300 WRITE_WORD(p, 0x54410002); 301 WRITE_WORD(p, info->ram_size); 302 WRITE_WORD(p, info->loader_start); 303 if (initrd_size) { 304 /* ATAG_INITRD2 */ 305 WRITE_WORD(p, 4); 306 WRITE_WORD(p, 0x54420005); 307 WRITE_WORD(p, info->initrd_start); 308 WRITE_WORD(p, initrd_size); 309 } 310 if (info->kernel_cmdline && *info->kernel_cmdline) { 311 /* ATAG_CMDLINE */ 312 int cmdline_size; 313 314 cmdline_size = strlen(info->kernel_cmdline); 315 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 316 (const uint8_t *)info->kernel_cmdline, 317 cmdline_size + 1); 318 cmdline_size = (cmdline_size >> 2) + 1; 319 WRITE_WORD(p, cmdline_size + 2); 320 WRITE_WORD(p, 0x54410009); 321 p += cmdline_size * 4; 322 } 323 if (info->atag_board) { 324 /* ATAG_BOARD */ 325 int atag_board_len; 326 uint8_t atag_board_buf[0x1000]; 327 328 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 329 WRITE_WORD(p, (atag_board_len + 8) >> 2); 330 WRITE_WORD(p, 0x414f4d50); 331 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 332 atag_board_buf, atag_board_len); 333 p += atag_board_len; 334 } 335 /* ATAG_END */ 336 WRITE_WORD(p, 0); 337 WRITE_WORD(p, 0); 338 } 339 340 static void set_kernel_args_old(const struct arm_boot_info *info, 341 AddressSpace *as) 342 { 343 hwaddr p; 344 const char *s; 345 int initrd_size = info->initrd_size; 346 hwaddr base = info->loader_start; 347 348 /* see linux/include/asm-arm/setup.h */ 349 p = base + KERNEL_ARGS_ADDR; 350 /* page_size */ 351 WRITE_WORD(p, 4096); 352 /* nr_pages */ 353 WRITE_WORD(p, info->ram_size / 4096); 354 /* ramdisk_size */ 355 WRITE_WORD(p, 0); 356 #define FLAG_READONLY 1 357 #define FLAG_RDLOAD 4 358 #define FLAG_RDPROMPT 8 359 /* flags */ 360 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 361 /* rootdev */ 362 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 363 /* video_num_cols */ 364 WRITE_WORD(p, 0); 365 /* video_num_rows */ 366 WRITE_WORD(p, 0); 367 /* video_x */ 368 WRITE_WORD(p, 0); 369 /* video_y */ 370 WRITE_WORD(p, 0); 371 /* memc_control_reg */ 372 WRITE_WORD(p, 0); 373 /* unsigned char sounddefault */ 374 /* unsigned char adfsdrives */ 375 /* unsigned char bytes_per_char_h */ 376 /* unsigned char bytes_per_char_v */ 377 WRITE_WORD(p, 0); 378 /* pages_in_bank[4] */ 379 WRITE_WORD(p, 0); 380 WRITE_WORD(p, 0); 381 WRITE_WORD(p, 0); 382 WRITE_WORD(p, 0); 383 /* pages_in_vram */ 384 WRITE_WORD(p, 0); 385 /* initrd_start */ 386 if (initrd_size) { 387 WRITE_WORD(p, info->initrd_start); 388 } else { 389 WRITE_WORD(p, 0); 390 } 391 /* initrd_size */ 392 WRITE_WORD(p, initrd_size); 393 /* rd_start */ 394 WRITE_WORD(p, 0); 395 /* system_rev */ 396 WRITE_WORD(p, 0); 397 /* system_serial_low */ 398 WRITE_WORD(p, 0); 399 /* system_serial_high */ 400 WRITE_WORD(p, 0); 401 /* mem_fclk_21285 */ 402 WRITE_WORD(p, 0); 403 /* zero unused fields */ 404 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 405 WRITE_WORD(p, 0); 406 } 407 s = info->kernel_cmdline; 408 if (s) { 409 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 410 (const uint8_t *)s, strlen(s) + 1); 411 } else { 412 WRITE_WORD(p, 0); 413 } 414 } 415 416 static void fdt_add_psci_node(void *fdt) 417 { 418 uint32_t cpu_suspend_fn; 419 uint32_t cpu_off_fn; 420 uint32_t cpu_on_fn; 421 uint32_t migrate_fn; 422 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 423 const char *psci_method; 424 int64_t psci_conduit; 425 426 psci_conduit = object_property_get_int(OBJECT(armcpu), 427 "psci-conduit", 428 &error_abort); 429 switch (psci_conduit) { 430 case QEMU_PSCI_CONDUIT_DISABLED: 431 return; 432 case QEMU_PSCI_CONDUIT_HVC: 433 psci_method = "hvc"; 434 break; 435 case QEMU_PSCI_CONDUIT_SMC: 436 psci_method = "smc"; 437 break; 438 default: 439 g_assert_not_reached(); 440 } 441 442 qemu_fdt_add_subnode(fdt, "/psci"); 443 if (armcpu->psci_version == 2) { 444 const char comp[] = "arm,psci-0.2\0arm,psci"; 445 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 446 447 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 448 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 449 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 450 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 451 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 452 } else { 453 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 454 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 455 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 456 } 457 } else { 458 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 459 460 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 461 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 462 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 463 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 464 } 465 466 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 467 * to the instruction that should be used to invoke PSCI functions. 468 * However, the device tree binding uses 'method' instead, so that is 469 * what we should use here. 470 */ 471 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 472 473 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 474 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 475 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 476 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 477 } 478 479 /** 480 * load_dtb() - load a device tree binary image into memory 481 * @addr: the address to load the image at 482 * @binfo: struct describing the boot environment 483 * @addr_limit: upper limit of the available memory area at @addr 484 * @as: address space to load image to 485 * 486 * Load a device tree supplied by the machine or by the user with the 487 * '-dtb' command line option, and put it at offset @addr in target 488 * memory. 489 * 490 * If @addr_limit contains a meaningful value (i.e., it is strictly greater 491 * than @addr), the device tree is only loaded if its size does not exceed 492 * the limit. 493 * 494 * Returns: the size of the device tree image on success, 495 * 0 if the image size exceeds the limit, 496 * -1 on errors. 497 * 498 * Note: Must not be called unless have_dtb(binfo) is true. 499 */ 500 static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 501 hwaddr addr_limit, AddressSpace *as) 502 { 503 void *fdt = NULL; 504 int size, rc; 505 uint32_t acells, scells; 506 char *nodename; 507 unsigned int i; 508 hwaddr mem_base, mem_len; 509 510 if (binfo->dtb_filename) { 511 char *filename; 512 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 513 if (!filename) { 514 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 515 goto fail; 516 } 517 518 fdt = load_device_tree(filename, &size); 519 if (!fdt) { 520 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 521 g_free(filename); 522 goto fail; 523 } 524 g_free(filename); 525 } else { 526 fdt = binfo->get_dtb(binfo, &size); 527 if (!fdt) { 528 fprintf(stderr, "Board was unable to create a dtb blob\n"); 529 goto fail; 530 } 531 } 532 533 if (addr_limit > addr && size > (addr_limit - addr)) { 534 /* Installing the device tree blob at addr would exceed addr_limit. 535 * Whether this constitutes failure is up to the caller to decide, 536 * so just return 0 as size, i.e., no error. 537 */ 538 g_free(fdt); 539 return 0; 540 } 541 542 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 543 NULL, &error_fatal); 544 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 545 NULL, &error_fatal); 546 if (acells == 0 || scells == 0) { 547 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 548 goto fail; 549 } 550 551 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { 552 /* This is user error so deserves a friendlier error message 553 * than the failure of setprop_sized_cells would provide 554 */ 555 fprintf(stderr, "qemu: dtb file not compatible with " 556 "RAM size > 4GB\n"); 557 goto fail; 558 } 559 560 if (nb_numa_nodes > 0) { 561 /* 562 * Turn the /memory node created before into a NOP node, then create 563 * /memory@addr nodes for all numa nodes respectively. 564 */ 565 qemu_fdt_nop_node(fdt, "/memory"); 566 mem_base = binfo->loader_start; 567 for (i = 0; i < nb_numa_nodes; i++) { 568 mem_len = numa_info[i].node_mem; 569 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 570 qemu_fdt_add_subnode(fdt, nodename); 571 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 572 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 573 acells, mem_base, 574 scells, mem_len); 575 if (rc < 0) { 576 fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename, 577 i); 578 goto fail; 579 } 580 581 qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i); 582 mem_base += mem_len; 583 g_free(nodename); 584 } 585 } else { 586 Error *err = NULL; 587 588 rc = fdt_path_offset(fdt, "/memory"); 589 if (rc < 0) { 590 qemu_fdt_add_subnode(fdt, "/memory"); 591 } 592 593 if (!qemu_fdt_getprop(fdt, "/memory", "device_type", NULL, &err)) { 594 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 595 } 596 597 rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg", 598 acells, binfo->loader_start, 599 scells, binfo->ram_size); 600 if (rc < 0) { 601 fprintf(stderr, "couldn't set /memory/reg\n"); 602 goto fail; 603 } 604 } 605 606 rc = fdt_path_offset(fdt, "/chosen"); 607 if (rc < 0) { 608 qemu_fdt_add_subnode(fdt, "/chosen"); 609 } 610 611 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { 612 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 613 binfo->kernel_cmdline); 614 if (rc < 0) { 615 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 616 goto fail; 617 } 618 } 619 620 if (binfo->initrd_size) { 621 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 622 binfo->initrd_start); 623 if (rc < 0) { 624 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 625 goto fail; 626 } 627 628 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 629 binfo->initrd_start + binfo->initrd_size); 630 if (rc < 0) { 631 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 632 goto fail; 633 } 634 } 635 636 fdt_add_psci_node(fdt); 637 638 if (binfo->modify_dtb) { 639 binfo->modify_dtb(binfo, fdt); 640 } 641 642 qemu_fdt_dumpdtb(fdt, size); 643 644 /* Put the DTB into the memory map as a ROM image: this will ensure 645 * the DTB is copied again upon reset, even if addr points into RAM. 646 */ 647 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 648 649 g_free(fdt); 650 651 return size; 652 653 fail: 654 g_free(fdt); 655 return -1; 656 } 657 658 static void do_cpu_reset(void *opaque) 659 { 660 ARMCPU *cpu = opaque; 661 CPUState *cs = CPU(cpu); 662 CPUARMState *env = &cpu->env; 663 const struct arm_boot_info *info = env->boot_info; 664 665 cpu_reset(cs); 666 if (info) { 667 if (!info->is_linux) { 668 int i; 669 /* Jump to the entry point. */ 670 uint64_t entry = info->entry; 671 672 switch (info->endianness) { 673 case ARM_ENDIANNESS_LE: 674 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 675 for (i = 1; i < 4; ++i) { 676 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 677 } 678 env->uncached_cpsr &= ~CPSR_E; 679 break; 680 case ARM_ENDIANNESS_BE8: 681 env->cp15.sctlr_el[1] |= SCTLR_E0E; 682 for (i = 1; i < 4; ++i) { 683 env->cp15.sctlr_el[i] |= SCTLR_EE; 684 } 685 env->uncached_cpsr |= CPSR_E; 686 break; 687 case ARM_ENDIANNESS_BE32: 688 env->cp15.sctlr_el[1] |= SCTLR_B; 689 break; 690 case ARM_ENDIANNESS_UNKNOWN: 691 break; /* Board's decision */ 692 default: 693 g_assert_not_reached(); 694 } 695 696 if (!env->aarch64) { 697 env->thumb = info->entry & 1; 698 entry &= 0xfffffffe; 699 } 700 cpu_set_pc(cs, entry); 701 } else { 702 /* If we are booting Linux then we need to check whether we are 703 * booting into secure or non-secure state and adjust the state 704 * accordingly. Out of reset, ARM is defined to be in secure state 705 * (SCR.NS = 0), we change that here if non-secure boot has been 706 * requested. 707 */ 708 if (arm_feature(env, ARM_FEATURE_EL3)) { 709 /* AArch64 is defined to come out of reset into EL3 if enabled. 710 * If we are booting Linux then we need to adjust our EL as 711 * Linux expects us to be in EL2 or EL1. AArch32 resets into 712 * SVC, which Linux expects, so no privilege/exception level to 713 * adjust. 714 */ 715 if (env->aarch64) { 716 env->cp15.scr_el3 |= SCR_RW; 717 if (arm_feature(env, ARM_FEATURE_EL2)) { 718 env->cp15.hcr_el2 |= HCR_RW; 719 env->pstate = PSTATE_MODE_EL2h; 720 } else { 721 env->pstate = PSTATE_MODE_EL1h; 722 } 723 } 724 725 /* Set to non-secure if not a secure boot */ 726 if (!info->secure_boot && 727 (cs != first_cpu || !info->secure_board_setup)) { 728 /* Linux expects non-secure state */ 729 env->cp15.scr_el3 |= SCR_NS; 730 } 731 } 732 733 if (cs == first_cpu) { 734 AddressSpace *as = arm_boot_address_space(cpu, info); 735 736 cpu_set_pc(cs, info->loader_start); 737 738 if (!have_dtb(info)) { 739 if (old_param) { 740 set_kernel_args_old(info, as); 741 } else { 742 set_kernel_args(info, as); 743 } 744 } 745 } else { 746 info->secondary_cpu_reset_hook(cpu, info); 747 } 748 } 749 } 750 } 751 752 /** 753 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 754 * by key. 755 * @fw_cfg: The firmware config instance to store the data in. 756 * @size_key: The firmware config key to store the size of the loaded 757 * data under, with fw_cfg_add_i32(). 758 * @data_key: The firmware config key to store the loaded data under, 759 * with fw_cfg_add_bytes(). 760 * @image_name: The name of the image file to load. If it is NULL, the 761 * function returns without doing anything. 762 * @try_decompress: Whether the image should be decompressed (gunzipped) before 763 * adding it to fw_cfg. If decompression fails, the image is 764 * loaded as-is. 765 * 766 * In case of failure, the function prints an error message to stderr and the 767 * process exits with status 1. 768 */ 769 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 770 uint16_t data_key, const char *image_name, 771 bool try_decompress) 772 { 773 size_t size = -1; 774 uint8_t *data; 775 776 if (image_name == NULL) { 777 return; 778 } 779 780 if (try_decompress) { 781 size = load_image_gzipped_buffer(image_name, 782 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 783 } 784 785 if (size == (size_t)-1) { 786 gchar *contents; 787 gsize length; 788 789 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 790 error_report("failed to load \"%s\"", image_name); 791 exit(1); 792 } 793 size = length; 794 data = (uint8_t *)contents; 795 } 796 797 fw_cfg_add_i32(fw_cfg, size_key, size); 798 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 799 } 800 801 static int do_arm_linux_init(Object *obj, void *opaque) 802 { 803 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 804 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 805 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 806 struct arm_boot_info *info = opaque; 807 808 if (albifc->arm_linux_init) { 809 albifc->arm_linux_init(albif, info->secure_boot); 810 } 811 } 812 return 0; 813 } 814 815 static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 816 uint64_t *lowaddr, uint64_t *highaddr, 817 int elf_machine, AddressSpace *as) 818 { 819 bool elf_is64; 820 union { 821 Elf32_Ehdr h32; 822 Elf64_Ehdr h64; 823 } elf_header; 824 int data_swab = 0; 825 bool big_endian; 826 uint64_t ret = -1; 827 Error *err = NULL; 828 829 830 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 831 if (err) { 832 return ret; 833 } 834 835 if (elf_is64) { 836 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 837 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 838 : ARM_ENDIANNESS_LE; 839 } else { 840 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 841 if (big_endian) { 842 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 843 info->endianness = ARM_ENDIANNESS_BE8; 844 } else { 845 info->endianness = ARM_ENDIANNESS_BE32; 846 /* In BE32, the CPU has a different view of the per-byte 847 * address map than the rest of the system. BE32 ELF files 848 * are organised such that they can be programmed through 849 * the CPU's per-word byte-reversed view of the world. QEMU 850 * however loads ELF files independently of the CPU. So 851 * tell the ELF loader to byte reverse the data for us. 852 */ 853 data_swab = 2; 854 } 855 } else { 856 info->endianness = ARM_ENDIANNESS_LE; 857 } 858 } 859 860 ret = load_elf_as(info->kernel_filename, NULL, NULL, 861 pentry, lowaddr, highaddr, big_endian, elf_machine, 862 1, data_swab, as); 863 if (ret <= 0) { 864 /* The header loaded but the image didn't */ 865 exit(1); 866 } 867 868 return ret; 869 } 870 871 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 872 hwaddr *entry, AddressSpace *as) 873 { 874 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 875 uint8_t *buffer; 876 int size; 877 878 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 879 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 880 &buffer); 881 882 if (size < 0) { 883 gsize len; 884 885 /* Load as raw file otherwise */ 886 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 887 return -1; 888 } 889 size = len; 890 } 891 892 /* check the arm64 magic header value -- very old kernels may not have it */ 893 if (memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 894 uint64_t hdrvals[2]; 895 896 /* The arm64 Image header has text_offset and image_size fields at 8 and 897 * 16 bytes into the Image header, respectively. The text_offset field 898 * is only valid if the image_size is non-zero. 899 */ 900 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 901 if (hdrvals[1] != 0) { 902 kernel_load_offset = le64_to_cpu(hdrvals[0]); 903 } 904 } 905 906 *entry = mem_base + kernel_load_offset; 907 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 908 909 g_free(buffer); 910 911 return size; 912 } 913 914 static void arm_load_kernel_notify(Notifier *notifier, void *data) 915 { 916 CPUState *cs; 917 int kernel_size; 918 int initrd_size; 919 int is_linux = 0; 920 uint64_t elf_entry, elf_low_addr, elf_high_addr; 921 int elf_machine; 922 hwaddr entry; 923 static const ARMInsnFixup *primary_loader; 924 ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier, 925 notifier, notifier); 926 ARMCPU *cpu = n->cpu; 927 struct arm_boot_info *info = 928 container_of(n, struct arm_boot_info, load_kernel_notifier); 929 AddressSpace *as = arm_boot_address_space(cpu, info); 930 931 /* The board code is not supposed to set secure_board_setup unless 932 * running its code in secure mode is actually possible, and KVM 933 * doesn't support secure. 934 */ 935 assert(!(info->secure_board_setup && kvm_enabled())); 936 937 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 938 939 /* Load the kernel. */ 940 if (!info->kernel_filename || info->firmware_loaded) { 941 942 if (have_dtb(info)) { 943 /* If we have a device tree blob, but no kernel to supply it to (or 944 * the kernel is supposed to be loaded by the bootloader), copy the 945 * DTB to the base of RAM for the bootloader to pick up. 946 */ 947 if (load_dtb(info->loader_start, info, 0, as) < 0) { 948 exit(1); 949 } 950 } 951 952 if (info->kernel_filename) { 953 FWCfgState *fw_cfg; 954 bool try_decompressing_kernel; 955 956 fw_cfg = fw_cfg_find(); 957 try_decompressing_kernel = arm_feature(&cpu->env, 958 ARM_FEATURE_AARCH64); 959 960 /* Expose the kernel, the command line, and the initrd in fw_cfg. 961 * We don't process them here at all, it's all left to the 962 * firmware. 963 */ 964 load_image_to_fw_cfg(fw_cfg, 965 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 966 info->kernel_filename, 967 try_decompressing_kernel); 968 load_image_to_fw_cfg(fw_cfg, 969 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 970 info->initrd_filename, false); 971 972 if (info->kernel_cmdline) { 973 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 974 strlen(info->kernel_cmdline) + 1); 975 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 976 info->kernel_cmdline); 977 } 978 } 979 980 /* We will start from address 0 (typically a boot ROM image) in the 981 * same way as hardware. 982 */ 983 return; 984 } 985 986 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 987 primary_loader = bootloader_aarch64; 988 elf_machine = EM_AARCH64; 989 } else { 990 primary_loader = bootloader; 991 if (!info->write_board_setup) { 992 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 993 } 994 elf_machine = EM_ARM; 995 } 996 997 if (!info->secondary_cpu_reset_hook) { 998 info->secondary_cpu_reset_hook = default_reset_secondary; 999 } 1000 if (!info->write_secondary_boot) { 1001 info->write_secondary_boot = default_write_secondary; 1002 } 1003 1004 if (info->nb_cpus == 0) 1005 info->nb_cpus = 1; 1006 1007 /* We want to put the initrd far enough into RAM that when the 1008 * kernel is uncompressed it will not clobber the initrd. However 1009 * on boards without much RAM we must ensure that we still leave 1010 * enough room for a decent sized initrd, and on boards with large 1011 * amounts of RAM we must avoid the initrd being so far up in RAM 1012 * that it is outside lowmem and inaccessible to the kernel. 1013 * So for boards with less than 256MB of RAM we put the initrd 1014 * halfway into RAM, and for boards with 256MB of RAM or more we put 1015 * the initrd at 128MB. 1016 */ 1017 info->initrd_start = info->loader_start + 1018 MIN(info->ram_size / 2, 128 * 1024 * 1024); 1019 1020 /* Assume that raw images are linux kernels, and ELF images are not. */ 1021 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, 1022 &elf_high_addr, elf_machine, as); 1023 if (kernel_size > 0 && have_dtb(info)) { 1024 /* If there is still some room left at the base of RAM, try and put 1025 * the DTB there like we do for images loaded with -bios or -pflash. 1026 */ 1027 if (elf_low_addr > info->loader_start 1028 || elf_high_addr < info->loader_start) { 1029 /* Pass elf_low_addr as address limit to load_dtb if it may be 1030 * pointing into RAM, otherwise pass '0' (no limit) 1031 */ 1032 if (elf_low_addr < info->loader_start) { 1033 elf_low_addr = 0; 1034 } 1035 if (load_dtb(info->loader_start, info, elf_low_addr, as) < 0) { 1036 exit(1); 1037 } 1038 } 1039 } 1040 entry = elf_entry; 1041 if (kernel_size < 0) { 1042 kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL, 1043 &is_linux, NULL, NULL, as); 1044 } 1045 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1046 kernel_size = load_aarch64_image(info->kernel_filename, 1047 info->loader_start, &entry, as); 1048 is_linux = 1; 1049 } else if (kernel_size < 0) { 1050 /* 32-bit ARM */ 1051 entry = info->loader_start + KERNEL_LOAD_ADDR; 1052 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1053 info->ram_size - KERNEL_LOAD_ADDR, 1054 as); 1055 is_linux = 1; 1056 } 1057 if (kernel_size < 0) { 1058 error_report("could not load kernel '%s'", info->kernel_filename); 1059 exit(1); 1060 } 1061 info->entry = entry; 1062 if (is_linux) { 1063 uint32_t fixupcontext[FIXUP_MAX]; 1064 1065 if (info->initrd_filename) { 1066 initrd_size = load_ramdisk_as(info->initrd_filename, 1067 info->initrd_start, 1068 info->ram_size - info->initrd_start, 1069 as); 1070 if (initrd_size < 0) { 1071 initrd_size = load_image_targphys_as(info->initrd_filename, 1072 info->initrd_start, 1073 info->ram_size - 1074 info->initrd_start, 1075 as); 1076 } 1077 if (initrd_size < 0) { 1078 error_report("could not load initrd '%s'", 1079 info->initrd_filename); 1080 exit(1); 1081 } 1082 } else { 1083 initrd_size = 0; 1084 } 1085 info->initrd_size = initrd_size; 1086 1087 fixupcontext[FIXUP_BOARDID] = info->board_id; 1088 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1089 1090 /* for device tree boot, we pass the DTB directly in r2. Otherwise 1091 * we point to the kernel args. 1092 */ 1093 if (have_dtb(info)) { 1094 hwaddr align; 1095 hwaddr dtb_start; 1096 1097 if (elf_machine == EM_AARCH64) { 1098 /* 1099 * Some AArch64 kernels on early bootup map the fdt region as 1100 * 1101 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1102 * 1103 * Let's play safe and prealign it to 2MB to give us some space. 1104 */ 1105 align = 2 * 1024 * 1024; 1106 } else { 1107 /* 1108 * Some 32bit kernels will trash anything in the 4K page the 1109 * initrd ends in, so make sure the DTB isn't caught up in that. 1110 */ 1111 align = 4096; 1112 } 1113 1114 /* Place the DTB after the initrd in memory with alignment. */ 1115 dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); 1116 if (load_dtb(dtb_start, info, 0, as) < 0) { 1117 exit(1); 1118 } 1119 fixupcontext[FIXUP_ARGPTR] = dtb_start; 1120 } else { 1121 fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR; 1122 if (info->ram_size >= (1ULL << 32)) { 1123 error_report("RAM size must be less than 4GB to boot" 1124 " Linux kernel using ATAGS (try passing a device tree" 1125 " using -dtb)"); 1126 exit(1); 1127 } 1128 } 1129 fixupcontext[FIXUP_ENTRYPOINT] = entry; 1130 1131 write_bootloader("bootloader", info->loader_start, 1132 primary_loader, fixupcontext, as); 1133 1134 if (info->nb_cpus > 1) { 1135 info->write_secondary_boot(cpu, info); 1136 } 1137 if (info->write_board_setup) { 1138 info->write_board_setup(cpu, info); 1139 } 1140 1141 /* Notify devices which need to fake up firmware initialization 1142 * that we're doing a direct kernel boot. 1143 */ 1144 object_child_foreach_recursive(object_get_root(), 1145 do_arm_linux_init, info); 1146 } 1147 info->is_linux = is_linux; 1148 1149 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { 1150 ARM_CPU(cs)->env.boot_info = info; 1151 } 1152 } 1153 1154 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 1155 { 1156 CPUState *cs; 1157 1158 info->load_kernel_notifier.cpu = cpu; 1159 info->load_kernel_notifier.notifier.notify = arm_load_kernel_notify; 1160 qemu_add_machine_init_done_notifier(&info->load_kernel_notifier.notifier); 1161 1162 /* CPU objects (unlike devices) are not automatically reset on system 1163 * reset, so we must always register a handler to do so. If we're 1164 * actually loading a kernel, the handler is also responsible for 1165 * arranging that we start it correctly. 1166 */ 1167 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { 1168 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1169 } 1170 } 1171 1172 static const TypeInfo arm_linux_boot_if_info = { 1173 .name = TYPE_ARM_LINUX_BOOT_IF, 1174 .parent = TYPE_INTERFACE, 1175 .class_size = sizeof(ARMLinuxBootIfClass), 1176 }; 1177 1178 static void arm_linux_boot_register_types(void) 1179 { 1180 type_register_static(&arm_linux_boot_if_info); 1181 } 1182 1183 type_init(arm_linux_boot_register_types) 1184