1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/error-report.h" 12 #include "qapi/error.h" 13 #include <libfdt.h> 14 #include "hw/hw.h" 15 #include "hw/arm/arm.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "sysemu/kvm.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/numa.h" 20 #include "hw/boards.h" 21 #include "hw/loader.h" 22 #include "elf.h" 23 #include "sysemu/device_tree.h" 24 #include "qemu/config-file.h" 25 #include "qemu/option.h" 26 #include "exec/address-spaces.h" 27 28 /* Kernel boot protocol is specified in the kernel docs 29 * Documentation/arm/Booting and Documentation/arm64/booting.txt 30 * They have different preferred image load offsets from system RAM base. 31 */ 32 #define KERNEL_ARGS_ADDR 0x100 33 #define KERNEL_LOAD_ADDR 0x00010000 34 #define KERNEL64_LOAD_ADDR 0x00080000 35 36 #define ARM64_TEXT_OFFSET_OFFSET 8 37 #define ARM64_MAGIC_OFFSET 56 38 39 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 40 const struct arm_boot_info *info) 41 { 42 /* Return the address space to use for bootloader reads and writes. 43 * We prefer the secure address space if the CPU has it and we're 44 * going to boot the guest into it. 45 */ 46 int asidx; 47 CPUState *cs = CPU(cpu); 48 49 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 50 asidx = ARMASIdx_S; 51 } else { 52 asidx = ARMASIdx_NS; 53 } 54 55 return cpu_get_address_space(cs, asidx); 56 } 57 58 typedef enum { 59 FIXUP_NONE = 0, /* do nothing */ 60 FIXUP_TERMINATOR, /* end of insns */ 61 FIXUP_BOARDID, /* overwrite with board ID number */ 62 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 63 FIXUP_ARGPTR, /* overwrite with pointer to kernel args */ 64 FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */ 65 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 66 FIXUP_BOOTREG, /* overwrite with boot register address */ 67 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 68 FIXUP_MAX, 69 } FixupType; 70 71 typedef struct ARMInsnFixup { 72 uint32_t insn; 73 FixupType fixup; 74 } ARMInsnFixup; 75 76 static const ARMInsnFixup bootloader_aarch64[] = { 77 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 78 { 0xaa1f03e1 }, /* mov x1, xzr */ 79 { 0xaa1f03e2 }, /* mov x2, xzr */ 80 { 0xaa1f03e3 }, /* mov x3, xzr */ 81 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 82 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 83 { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */ 84 { 0 }, /* .word @DTB Higher 32-bits */ 85 { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */ 86 { 0 }, /* .word @Kernel Entry Higher 32-bits */ 87 { 0, FIXUP_TERMINATOR } 88 }; 89 90 /* A very small bootloader: call the board-setup code (if needed), 91 * set r0-r2, then jump to the kernel. 92 * If we're not calling boot setup code then we don't copy across 93 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 94 */ 95 96 static const ARMInsnFixup bootloader[] = { 97 { 0xe28fe004 }, /* add lr, pc, #4 */ 98 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 99 { 0, FIXUP_BOARD_SETUP }, 100 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 101 { 0xe3a00000 }, /* mov r0, #0 */ 102 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 103 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 104 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 105 { 0, FIXUP_BOARDID }, 106 { 0, FIXUP_ARGPTR }, 107 { 0, FIXUP_ENTRYPOINT }, 108 { 0, FIXUP_TERMINATOR } 109 }; 110 111 /* Handling for secondary CPU boot in a multicore system. 112 * Unlike the uniprocessor/primary CPU boot, this is platform 113 * dependent. The default code here is based on the secondary 114 * CPU boot protocol used on realview/vexpress boards, with 115 * some parameterisation to increase its flexibility. 116 * QEMU platform models for which this code is not appropriate 117 * should override write_secondary_boot and secondary_cpu_reset_hook 118 * instead. 119 * 120 * This code enables the interrupt controllers for the secondary 121 * CPUs and then puts all the secondary CPUs into a loop waiting 122 * for an interprocessor interrupt and polling a configurable 123 * location for the kernel secondary CPU entry point. 124 */ 125 #define DSB_INSN 0xf57ff04f 126 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 127 128 static const ARMInsnFixup smpboot[] = { 129 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 130 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 131 { 0xe3a01001 }, /* mov r1, #1 */ 132 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 133 { 0xe3a010ff }, /* mov r1, #0xff */ 134 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 135 { 0, FIXUP_DSB }, /* dsb */ 136 { 0xe320f003 }, /* wfi */ 137 { 0xe5901000 }, /* ldr r1, [r0] */ 138 { 0xe1110001 }, /* tst r1, r1 */ 139 { 0x0afffffb }, /* beq <wfi> */ 140 { 0xe12fff11 }, /* bx r1 */ 141 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 142 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 143 { 0, FIXUP_TERMINATOR } 144 }; 145 146 static void write_bootloader(const char *name, hwaddr addr, 147 const ARMInsnFixup *insns, uint32_t *fixupcontext, 148 AddressSpace *as) 149 { 150 /* Fix up the specified bootloader fragment and write it into 151 * guest memory using rom_add_blob_fixed(). fixupcontext is 152 * an array giving the values to write in for the fixup types 153 * which write a value into the code array. 154 */ 155 int i, len; 156 uint32_t *code; 157 158 len = 0; 159 while (insns[len].fixup != FIXUP_TERMINATOR) { 160 len++; 161 } 162 163 code = g_new0(uint32_t, len); 164 165 for (i = 0; i < len; i++) { 166 uint32_t insn = insns[i].insn; 167 FixupType fixup = insns[i].fixup; 168 169 switch (fixup) { 170 case FIXUP_NONE: 171 break; 172 case FIXUP_BOARDID: 173 case FIXUP_BOARD_SETUP: 174 case FIXUP_ARGPTR: 175 case FIXUP_ENTRYPOINT: 176 case FIXUP_GIC_CPU_IF: 177 case FIXUP_BOOTREG: 178 case FIXUP_DSB: 179 insn = fixupcontext[fixup]; 180 break; 181 default: 182 abort(); 183 } 184 code[i] = tswap32(insn); 185 } 186 187 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 188 189 g_free(code); 190 } 191 192 static void default_write_secondary(ARMCPU *cpu, 193 const struct arm_boot_info *info) 194 { 195 uint32_t fixupcontext[FIXUP_MAX]; 196 AddressSpace *as = arm_boot_address_space(cpu, info); 197 198 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 199 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 200 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 201 fixupcontext[FIXUP_DSB] = DSB_INSN; 202 } else { 203 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 204 } 205 206 write_bootloader("smpboot", info->smp_loader_start, 207 smpboot, fixupcontext, as); 208 } 209 210 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 211 const struct arm_boot_info *info, 212 hwaddr mvbar_addr) 213 { 214 AddressSpace *as = arm_boot_address_space(cpu, info); 215 int n; 216 uint32_t mvbar_blob[] = { 217 /* mvbar_addr: secure monitor vectors 218 * Default unimplemented and unused vectors to spin. Makes it 219 * easier to debug (as opposed to the CPU running away). 220 */ 221 0xeafffffe, /* (spin) */ 222 0xeafffffe, /* (spin) */ 223 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 224 0xeafffffe, /* (spin) */ 225 0xeafffffe, /* (spin) */ 226 0xeafffffe, /* (spin) */ 227 0xeafffffe, /* (spin) */ 228 0xeafffffe, /* (spin) */ 229 }; 230 uint32_t board_setup_blob[] = { 231 /* board setup addr */ 232 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 233 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 234 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 235 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 236 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 237 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 238 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 239 0xe1a0f001, /* mov pc, r1 ;return */ 240 }; 241 242 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 243 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 244 245 /* check that these blobs don't overlap */ 246 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 247 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 248 249 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 250 mvbar_blob[n] = tswap32(mvbar_blob[n]); 251 } 252 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 253 mvbar_addr, as); 254 255 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 256 board_setup_blob[n] = tswap32(board_setup_blob[n]); 257 } 258 rom_add_blob_fixed_as("board-setup", board_setup_blob, 259 sizeof(board_setup_blob), info->board_setup_addr, as); 260 } 261 262 static void default_reset_secondary(ARMCPU *cpu, 263 const struct arm_boot_info *info) 264 { 265 AddressSpace *as = arm_boot_address_space(cpu, info); 266 CPUState *cs = CPU(cpu); 267 268 address_space_stl_notdirty(as, info->smp_bootreg_addr, 269 0, MEMTXATTRS_UNSPECIFIED, NULL); 270 cpu_set_pc(cs, info->smp_loader_start); 271 } 272 273 static inline bool have_dtb(const struct arm_boot_info *info) 274 { 275 return info->dtb_filename || info->get_dtb; 276 } 277 278 #define WRITE_WORD(p, value) do { \ 279 address_space_stl_notdirty(as, p, value, \ 280 MEMTXATTRS_UNSPECIFIED, NULL); \ 281 p += 4; \ 282 } while (0) 283 284 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 285 { 286 int initrd_size = info->initrd_size; 287 hwaddr base = info->loader_start; 288 hwaddr p; 289 290 p = base + KERNEL_ARGS_ADDR; 291 /* ATAG_CORE */ 292 WRITE_WORD(p, 5); 293 WRITE_WORD(p, 0x54410001); 294 WRITE_WORD(p, 1); 295 WRITE_WORD(p, 0x1000); 296 WRITE_WORD(p, 0); 297 /* ATAG_MEM */ 298 /* TODO: handle multiple chips on one ATAG list */ 299 WRITE_WORD(p, 4); 300 WRITE_WORD(p, 0x54410002); 301 WRITE_WORD(p, info->ram_size); 302 WRITE_WORD(p, info->loader_start); 303 if (initrd_size) { 304 /* ATAG_INITRD2 */ 305 WRITE_WORD(p, 4); 306 WRITE_WORD(p, 0x54420005); 307 WRITE_WORD(p, info->initrd_start); 308 WRITE_WORD(p, initrd_size); 309 } 310 if (info->kernel_cmdline && *info->kernel_cmdline) { 311 /* ATAG_CMDLINE */ 312 int cmdline_size; 313 314 cmdline_size = strlen(info->kernel_cmdline); 315 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 316 (const uint8_t *)info->kernel_cmdline, 317 cmdline_size + 1); 318 cmdline_size = (cmdline_size >> 2) + 1; 319 WRITE_WORD(p, cmdline_size + 2); 320 WRITE_WORD(p, 0x54410009); 321 p += cmdline_size * 4; 322 } 323 if (info->atag_board) { 324 /* ATAG_BOARD */ 325 int atag_board_len; 326 uint8_t atag_board_buf[0x1000]; 327 328 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 329 WRITE_WORD(p, (atag_board_len + 8) >> 2); 330 WRITE_WORD(p, 0x414f4d50); 331 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 332 atag_board_buf, atag_board_len); 333 p += atag_board_len; 334 } 335 /* ATAG_END */ 336 WRITE_WORD(p, 0); 337 WRITE_WORD(p, 0); 338 } 339 340 static void set_kernel_args_old(const struct arm_boot_info *info, 341 AddressSpace *as) 342 { 343 hwaddr p; 344 const char *s; 345 int initrd_size = info->initrd_size; 346 hwaddr base = info->loader_start; 347 348 /* see linux/include/asm-arm/setup.h */ 349 p = base + KERNEL_ARGS_ADDR; 350 /* page_size */ 351 WRITE_WORD(p, 4096); 352 /* nr_pages */ 353 WRITE_WORD(p, info->ram_size / 4096); 354 /* ramdisk_size */ 355 WRITE_WORD(p, 0); 356 #define FLAG_READONLY 1 357 #define FLAG_RDLOAD 4 358 #define FLAG_RDPROMPT 8 359 /* flags */ 360 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 361 /* rootdev */ 362 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 363 /* video_num_cols */ 364 WRITE_WORD(p, 0); 365 /* video_num_rows */ 366 WRITE_WORD(p, 0); 367 /* video_x */ 368 WRITE_WORD(p, 0); 369 /* video_y */ 370 WRITE_WORD(p, 0); 371 /* memc_control_reg */ 372 WRITE_WORD(p, 0); 373 /* unsigned char sounddefault */ 374 /* unsigned char adfsdrives */ 375 /* unsigned char bytes_per_char_h */ 376 /* unsigned char bytes_per_char_v */ 377 WRITE_WORD(p, 0); 378 /* pages_in_bank[4] */ 379 WRITE_WORD(p, 0); 380 WRITE_WORD(p, 0); 381 WRITE_WORD(p, 0); 382 WRITE_WORD(p, 0); 383 /* pages_in_vram */ 384 WRITE_WORD(p, 0); 385 /* initrd_start */ 386 if (initrd_size) { 387 WRITE_WORD(p, info->initrd_start); 388 } else { 389 WRITE_WORD(p, 0); 390 } 391 /* initrd_size */ 392 WRITE_WORD(p, initrd_size); 393 /* rd_start */ 394 WRITE_WORD(p, 0); 395 /* system_rev */ 396 WRITE_WORD(p, 0); 397 /* system_serial_low */ 398 WRITE_WORD(p, 0); 399 /* system_serial_high */ 400 WRITE_WORD(p, 0); 401 /* mem_fclk_21285 */ 402 WRITE_WORD(p, 0); 403 /* zero unused fields */ 404 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 405 WRITE_WORD(p, 0); 406 } 407 s = info->kernel_cmdline; 408 if (s) { 409 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 410 (const uint8_t *)s, strlen(s) + 1); 411 } else { 412 WRITE_WORD(p, 0); 413 } 414 } 415 416 static void fdt_add_psci_node(void *fdt) 417 { 418 uint32_t cpu_suspend_fn; 419 uint32_t cpu_off_fn; 420 uint32_t cpu_on_fn; 421 uint32_t migrate_fn; 422 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 423 const char *psci_method; 424 int64_t psci_conduit; 425 int rc; 426 427 psci_conduit = object_property_get_int(OBJECT(armcpu), 428 "psci-conduit", 429 &error_abort); 430 switch (psci_conduit) { 431 case QEMU_PSCI_CONDUIT_DISABLED: 432 return; 433 case QEMU_PSCI_CONDUIT_HVC: 434 psci_method = "hvc"; 435 break; 436 case QEMU_PSCI_CONDUIT_SMC: 437 psci_method = "smc"; 438 break; 439 default: 440 g_assert_not_reached(); 441 } 442 443 /* 444 * If /psci node is present in provided DTB, assume that no fixup 445 * is necessary and all PSCI configuration should be taken as-is 446 */ 447 rc = fdt_path_offset(fdt, "/psci"); 448 if (rc >= 0) { 449 return; 450 } 451 452 qemu_fdt_add_subnode(fdt, "/psci"); 453 if (armcpu->psci_version == 2) { 454 const char comp[] = "arm,psci-0.2\0arm,psci"; 455 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 456 457 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 458 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 459 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 460 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 461 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 462 } else { 463 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 464 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 465 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 466 } 467 } else { 468 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 469 470 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 471 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 472 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 473 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 474 } 475 476 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 477 * to the instruction that should be used to invoke PSCI functions. 478 * However, the device tree binding uses 'method' instead, so that is 479 * what we should use here. 480 */ 481 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 482 483 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 484 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 485 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 486 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 487 } 488 489 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 490 hwaddr addr_limit, AddressSpace *as) 491 { 492 void *fdt = NULL; 493 int size, rc, n = 0; 494 uint32_t acells, scells; 495 char *nodename; 496 unsigned int i; 497 hwaddr mem_base, mem_len; 498 char **node_path; 499 Error *err = NULL; 500 501 if (binfo->dtb_filename) { 502 char *filename; 503 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 504 if (!filename) { 505 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 506 goto fail; 507 } 508 509 fdt = load_device_tree(filename, &size); 510 if (!fdt) { 511 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 512 g_free(filename); 513 goto fail; 514 } 515 g_free(filename); 516 } else { 517 fdt = binfo->get_dtb(binfo, &size); 518 if (!fdt) { 519 fprintf(stderr, "Board was unable to create a dtb blob\n"); 520 goto fail; 521 } 522 } 523 524 if (addr_limit > addr && size > (addr_limit - addr)) { 525 /* Installing the device tree blob at addr would exceed addr_limit. 526 * Whether this constitutes failure is up to the caller to decide, 527 * so just return 0 as size, i.e., no error. 528 */ 529 g_free(fdt); 530 return 0; 531 } 532 533 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 534 NULL, &error_fatal); 535 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 536 NULL, &error_fatal); 537 if (acells == 0 || scells == 0) { 538 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 539 goto fail; 540 } 541 542 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { 543 /* This is user error so deserves a friendlier error message 544 * than the failure of setprop_sized_cells would provide 545 */ 546 fprintf(stderr, "qemu: dtb file not compatible with " 547 "RAM size > 4GB\n"); 548 goto fail; 549 } 550 551 /* nop all root nodes matching /memory or /memory@unit-address */ 552 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 553 if (err) { 554 error_report_err(err); 555 goto fail; 556 } 557 while (node_path[n]) { 558 if (g_str_has_prefix(node_path[n], "/memory")) { 559 qemu_fdt_nop_node(fdt, node_path[n]); 560 } 561 n++; 562 } 563 g_strfreev(node_path); 564 565 if (nb_numa_nodes > 0) { 566 mem_base = binfo->loader_start; 567 for (i = 0; i < nb_numa_nodes; i++) { 568 mem_len = numa_info[i].node_mem; 569 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 570 qemu_fdt_add_subnode(fdt, nodename); 571 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 572 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 573 acells, mem_base, 574 scells, mem_len); 575 if (rc < 0) { 576 fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename, 577 i); 578 goto fail; 579 } 580 581 qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i); 582 mem_base += mem_len; 583 g_free(nodename); 584 } 585 } else { 586 nodename = g_strdup_printf("/memory@%" PRIx64, binfo->loader_start); 587 qemu_fdt_add_subnode(fdt, nodename); 588 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 589 590 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 591 acells, binfo->loader_start, 592 scells, binfo->ram_size); 593 if (rc < 0) { 594 fprintf(stderr, "couldn't set %s reg\n", nodename); 595 goto fail; 596 } 597 g_free(nodename); 598 } 599 600 rc = fdt_path_offset(fdt, "/chosen"); 601 if (rc < 0) { 602 qemu_fdt_add_subnode(fdt, "/chosen"); 603 } 604 605 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { 606 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 607 binfo->kernel_cmdline); 608 if (rc < 0) { 609 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 610 goto fail; 611 } 612 } 613 614 if (binfo->initrd_size) { 615 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 616 binfo->initrd_start); 617 if (rc < 0) { 618 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 619 goto fail; 620 } 621 622 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 623 binfo->initrd_start + binfo->initrd_size); 624 if (rc < 0) { 625 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 626 goto fail; 627 } 628 } 629 630 fdt_add_psci_node(fdt); 631 632 if (binfo->modify_dtb) { 633 binfo->modify_dtb(binfo, fdt); 634 } 635 636 qemu_fdt_dumpdtb(fdt, size); 637 638 /* Put the DTB into the memory map as a ROM image: this will ensure 639 * the DTB is copied again upon reset, even if addr points into RAM. 640 */ 641 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 642 643 g_free(fdt); 644 645 return size; 646 647 fail: 648 g_free(fdt); 649 return -1; 650 } 651 652 static void do_cpu_reset(void *opaque) 653 { 654 ARMCPU *cpu = opaque; 655 CPUState *cs = CPU(cpu); 656 CPUARMState *env = &cpu->env; 657 const struct arm_boot_info *info = env->boot_info; 658 659 cpu_reset(cs); 660 if (info) { 661 if (!info->is_linux) { 662 int i; 663 /* Jump to the entry point. */ 664 uint64_t entry = info->entry; 665 666 switch (info->endianness) { 667 case ARM_ENDIANNESS_LE: 668 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 669 for (i = 1; i < 4; ++i) { 670 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 671 } 672 env->uncached_cpsr &= ~CPSR_E; 673 break; 674 case ARM_ENDIANNESS_BE8: 675 env->cp15.sctlr_el[1] |= SCTLR_E0E; 676 for (i = 1; i < 4; ++i) { 677 env->cp15.sctlr_el[i] |= SCTLR_EE; 678 } 679 env->uncached_cpsr |= CPSR_E; 680 break; 681 case ARM_ENDIANNESS_BE32: 682 env->cp15.sctlr_el[1] |= SCTLR_B; 683 break; 684 case ARM_ENDIANNESS_UNKNOWN: 685 break; /* Board's decision */ 686 default: 687 g_assert_not_reached(); 688 } 689 690 if (!env->aarch64) { 691 env->thumb = info->entry & 1; 692 entry &= 0xfffffffe; 693 } 694 cpu_set_pc(cs, entry); 695 } else { 696 /* If we are booting Linux then we need to check whether we are 697 * booting into secure or non-secure state and adjust the state 698 * accordingly. Out of reset, ARM is defined to be in secure state 699 * (SCR.NS = 0), we change that here if non-secure boot has been 700 * requested. 701 */ 702 if (arm_feature(env, ARM_FEATURE_EL3)) { 703 /* AArch64 is defined to come out of reset into EL3 if enabled. 704 * If we are booting Linux then we need to adjust our EL as 705 * Linux expects us to be in EL2 or EL1. AArch32 resets into 706 * SVC, which Linux expects, so no privilege/exception level to 707 * adjust. 708 */ 709 if (env->aarch64) { 710 env->cp15.scr_el3 |= SCR_RW; 711 if (arm_feature(env, ARM_FEATURE_EL2)) { 712 env->cp15.hcr_el2 |= HCR_RW; 713 env->pstate = PSTATE_MODE_EL2h; 714 } else { 715 env->pstate = PSTATE_MODE_EL1h; 716 } 717 /* AArch64 kernels never boot in secure mode */ 718 assert(!info->secure_boot); 719 /* This hook is only supported for AArch32 currently: 720 * bootloader_aarch64[] will not call the hook, and 721 * the code above has already dropped us into EL2 or EL1. 722 */ 723 assert(!info->secure_board_setup); 724 } 725 726 if (arm_feature(env, ARM_FEATURE_EL2)) { 727 /* If we have EL2 then Linux expects the HVC insn to work */ 728 env->cp15.scr_el3 |= SCR_HCE; 729 } 730 731 /* Set to non-secure if not a secure boot */ 732 if (!info->secure_boot && 733 (cs != first_cpu || !info->secure_board_setup)) { 734 /* Linux expects non-secure state */ 735 env->cp15.scr_el3 |= SCR_NS; 736 } 737 } 738 739 if (!env->aarch64 && !info->secure_boot && 740 arm_feature(env, ARM_FEATURE_EL2)) { 741 /* 742 * This is an AArch32 boot not to Secure state, and 743 * we have Hyp mode available, so boot the kernel into 744 * Hyp mode. This is not how the CPU comes out of reset, 745 * so we need to manually put it there. 746 */ 747 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw); 748 } 749 750 if (cs == first_cpu) { 751 AddressSpace *as = arm_boot_address_space(cpu, info); 752 753 cpu_set_pc(cs, info->loader_start); 754 755 if (!have_dtb(info)) { 756 if (old_param) { 757 set_kernel_args_old(info, as); 758 } else { 759 set_kernel_args(info, as); 760 } 761 } 762 } else { 763 info->secondary_cpu_reset_hook(cpu, info); 764 } 765 } 766 } 767 } 768 769 /** 770 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 771 * by key. 772 * @fw_cfg: The firmware config instance to store the data in. 773 * @size_key: The firmware config key to store the size of the loaded 774 * data under, with fw_cfg_add_i32(). 775 * @data_key: The firmware config key to store the loaded data under, 776 * with fw_cfg_add_bytes(). 777 * @image_name: The name of the image file to load. If it is NULL, the 778 * function returns without doing anything. 779 * @try_decompress: Whether the image should be decompressed (gunzipped) before 780 * adding it to fw_cfg. If decompression fails, the image is 781 * loaded as-is. 782 * 783 * In case of failure, the function prints an error message to stderr and the 784 * process exits with status 1. 785 */ 786 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 787 uint16_t data_key, const char *image_name, 788 bool try_decompress) 789 { 790 size_t size = -1; 791 uint8_t *data; 792 793 if (image_name == NULL) { 794 return; 795 } 796 797 if (try_decompress) { 798 size = load_image_gzipped_buffer(image_name, 799 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 800 } 801 802 if (size == (size_t)-1) { 803 gchar *contents; 804 gsize length; 805 806 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 807 error_report("failed to load \"%s\"", image_name); 808 exit(1); 809 } 810 size = length; 811 data = (uint8_t *)contents; 812 } 813 814 fw_cfg_add_i32(fw_cfg, size_key, size); 815 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 816 } 817 818 static int do_arm_linux_init(Object *obj, void *opaque) 819 { 820 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 821 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 822 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 823 struct arm_boot_info *info = opaque; 824 825 if (albifc->arm_linux_init) { 826 albifc->arm_linux_init(albif, info->secure_boot); 827 } 828 } 829 return 0; 830 } 831 832 static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 833 uint64_t *lowaddr, uint64_t *highaddr, 834 int elf_machine, AddressSpace *as) 835 { 836 bool elf_is64; 837 union { 838 Elf32_Ehdr h32; 839 Elf64_Ehdr h64; 840 } elf_header; 841 int data_swab = 0; 842 bool big_endian; 843 int64_t ret = -1; 844 Error *err = NULL; 845 846 847 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 848 if (err) { 849 error_free(err); 850 return ret; 851 } 852 853 if (elf_is64) { 854 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 855 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 856 : ARM_ENDIANNESS_LE; 857 } else { 858 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 859 if (big_endian) { 860 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 861 info->endianness = ARM_ENDIANNESS_BE8; 862 } else { 863 info->endianness = ARM_ENDIANNESS_BE32; 864 /* In BE32, the CPU has a different view of the per-byte 865 * address map than the rest of the system. BE32 ELF files 866 * are organised such that they can be programmed through 867 * the CPU's per-word byte-reversed view of the world. QEMU 868 * however loads ELF files independently of the CPU. So 869 * tell the ELF loader to byte reverse the data for us. 870 */ 871 data_swab = 2; 872 } 873 } else { 874 info->endianness = ARM_ENDIANNESS_LE; 875 } 876 } 877 878 ret = load_elf_as(info->kernel_filename, NULL, NULL, 879 pentry, lowaddr, highaddr, big_endian, elf_machine, 880 1, data_swab, as); 881 if (ret <= 0) { 882 /* The header loaded but the image didn't */ 883 exit(1); 884 } 885 886 return ret; 887 } 888 889 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 890 hwaddr *entry, AddressSpace *as) 891 { 892 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 893 uint8_t *buffer; 894 int size; 895 896 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 897 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 898 &buffer); 899 900 if (size < 0) { 901 gsize len; 902 903 /* Load as raw file otherwise */ 904 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 905 return -1; 906 } 907 size = len; 908 } 909 910 /* check the arm64 magic header value -- very old kernels may not have it */ 911 if (size > ARM64_MAGIC_OFFSET + 4 && 912 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 913 uint64_t hdrvals[2]; 914 915 /* The arm64 Image header has text_offset and image_size fields at 8 and 916 * 16 bytes into the Image header, respectively. The text_offset field 917 * is only valid if the image_size is non-zero. 918 */ 919 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 920 if (hdrvals[1] != 0) { 921 kernel_load_offset = le64_to_cpu(hdrvals[0]); 922 } 923 } 924 925 *entry = mem_base + kernel_load_offset; 926 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 927 928 g_free(buffer); 929 930 return size; 931 } 932 933 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 934 { 935 CPUState *cs; 936 int kernel_size; 937 int initrd_size; 938 int is_linux = 0; 939 uint64_t elf_entry, elf_low_addr, elf_high_addr; 940 int elf_machine; 941 hwaddr entry; 942 static const ARMInsnFixup *primary_loader; 943 AddressSpace *as = arm_boot_address_space(cpu, info); 944 945 /* CPU objects (unlike devices) are not automatically reset on system 946 * reset, so we must always register a handler to do so. If we're 947 * actually loading a kernel, the handler is also responsible for 948 * arranging that we start it correctly. 949 */ 950 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 951 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 952 } 953 954 /* The board code is not supposed to set secure_board_setup unless 955 * running its code in secure mode is actually possible, and KVM 956 * doesn't support secure. 957 */ 958 assert(!(info->secure_board_setup && kvm_enabled())); 959 960 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 961 info->dtb_limit = 0; 962 963 /* Load the kernel. */ 964 if (!info->kernel_filename || info->firmware_loaded) { 965 966 if (have_dtb(info)) { 967 /* If we have a device tree blob, but no kernel to supply it to (or 968 * the kernel is supposed to be loaded by the bootloader), copy the 969 * DTB to the base of RAM for the bootloader to pick up. 970 */ 971 info->dtb_start = info->loader_start; 972 } 973 974 if (info->kernel_filename) { 975 FWCfgState *fw_cfg; 976 bool try_decompressing_kernel; 977 978 fw_cfg = fw_cfg_find(); 979 try_decompressing_kernel = arm_feature(&cpu->env, 980 ARM_FEATURE_AARCH64); 981 982 /* Expose the kernel, the command line, and the initrd in fw_cfg. 983 * We don't process them here at all, it's all left to the 984 * firmware. 985 */ 986 load_image_to_fw_cfg(fw_cfg, 987 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 988 info->kernel_filename, 989 try_decompressing_kernel); 990 load_image_to_fw_cfg(fw_cfg, 991 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 992 info->initrd_filename, false); 993 994 if (info->kernel_cmdline) { 995 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 996 strlen(info->kernel_cmdline) + 1); 997 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 998 info->kernel_cmdline); 999 } 1000 } 1001 1002 /* We will start from address 0 (typically a boot ROM image) in the 1003 * same way as hardware. 1004 */ 1005 return; 1006 } 1007 1008 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1009 primary_loader = bootloader_aarch64; 1010 elf_machine = EM_AARCH64; 1011 } else { 1012 primary_loader = bootloader; 1013 if (!info->write_board_setup) { 1014 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 1015 } 1016 elf_machine = EM_ARM; 1017 } 1018 1019 if (!info->secondary_cpu_reset_hook) { 1020 info->secondary_cpu_reset_hook = default_reset_secondary; 1021 } 1022 if (!info->write_secondary_boot) { 1023 info->write_secondary_boot = default_write_secondary; 1024 } 1025 1026 if (info->nb_cpus == 0) 1027 info->nb_cpus = 1; 1028 1029 /* We want to put the initrd far enough into RAM that when the 1030 * kernel is uncompressed it will not clobber the initrd. However 1031 * on boards without much RAM we must ensure that we still leave 1032 * enough room for a decent sized initrd, and on boards with large 1033 * amounts of RAM we must avoid the initrd being so far up in RAM 1034 * that it is outside lowmem and inaccessible to the kernel. 1035 * So for boards with less than 256MB of RAM we put the initrd 1036 * halfway into RAM, and for boards with 256MB of RAM or more we put 1037 * the initrd at 128MB. 1038 */ 1039 info->initrd_start = info->loader_start + 1040 MIN(info->ram_size / 2, 128 * 1024 * 1024); 1041 1042 /* Assume that raw images are linux kernels, and ELF images are not. */ 1043 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, 1044 &elf_high_addr, elf_machine, as); 1045 if (kernel_size > 0 && have_dtb(info)) { 1046 /* If there is still some room left at the base of RAM, try and put 1047 * the DTB there like we do for images loaded with -bios or -pflash. 1048 */ 1049 if (elf_low_addr > info->loader_start 1050 || elf_high_addr < info->loader_start) { 1051 /* Set elf_low_addr as address limit for arm_load_dtb if it may be 1052 * pointing into RAM, otherwise pass '0' (no limit) 1053 */ 1054 if (elf_low_addr < info->loader_start) { 1055 elf_low_addr = 0; 1056 } 1057 info->dtb_start = info->loader_start; 1058 info->dtb_limit = elf_low_addr; 1059 } 1060 } 1061 entry = elf_entry; 1062 if (kernel_size < 0) { 1063 kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL, 1064 &is_linux, NULL, NULL, as); 1065 } 1066 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1067 kernel_size = load_aarch64_image(info->kernel_filename, 1068 info->loader_start, &entry, as); 1069 is_linux = 1; 1070 } else if (kernel_size < 0) { 1071 /* 32-bit ARM */ 1072 entry = info->loader_start + KERNEL_LOAD_ADDR; 1073 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1074 info->ram_size - KERNEL_LOAD_ADDR, 1075 as); 1076 is_linux = 1; 1077 } 1078 if (kernel_size < 0) { 1079 error_report("could not load kernel '%s'", info->kernel_filename); 1080 exit(1); 1081 } 1082 info->entry = entry; 1083 if (is_linux) { 1084 uint32_t fixupcontext[FIXUP_MAX]; 1085 1086 if (info->initrd_filename) { 1087 initrd_size = load_ramdisk_as(info->initrd_filename, 1088 info->initrd_start, 1089 info->ram_size - info->initrd_start, 1090 as); 1091 if (initrd_size < 0) { 1092 initrd_size = load_image_targphys_as(info->initrd_filename, 1093 info->initrd_start, 1094 info->ram_size - 1095 info->initrd_start, 1096 as); 1097 } 1098 if (initrd_size < 0) { 1099 error_report("could not load initrd '%s'", 1100 info->initrd_filename); 1101 exit(1); 1102 } 1103 } else { 1104 initrd_size = 0; 1105 } 1106 info->initrd_size = initrd_size; 1107 1108 fixupcontext[FIXUP_BOARDID] = info->board_id; 1109 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1110 1111 /* for device tree boot, we pass the DTB directly in r2. Otherwise 1112 * we point to the kernel args. 1113 */ 1114 if (have_dtb(info)) { 1115 hwaddr align; 1116 1117 if (elf_machine == EM_AARCH64) { 1118 /* 1119 * Some AArch64 kernels on early bootup map the fdt region as 1120 * 1121 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1122 * 1123 * Let's play safe and prealign it to 2MB to give us some space. 1124 */ 1125 align = 2 * 1024 * 1024; 1126 } else { 1127 /* 1128 * Some 32bit kernels will trash anything in the 4K page the 1129 * initrd ends in, so make sure the DTB isn't caught up in that. 1130 */ 1131 align = 4096; 1132 } 1133 1134 /* Place the DTB after the initrd in memory with alignment. */ 1135 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1136 align); 1137 fixupcontext[FIXUP_ARGPTR] = info->dtb_start; 1138 } else { 1139 fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR; 1140 if (info->ram_size >= (1ULL << 32)) { 1141 error_report("RAM size must be less than 4GB to boot" 1142 " Linux kernel using ATAGS (try passing a device tree" 1143 " using -dtb)"); 1144 exit(1); 1145 } 1146 } 1147 fixupcontext[FIXUP_ENTRYPOINT] = entry; 1148 1149 write_bootloader("bootloader", info->loader_start, 1150 primary_loader, fixupcontext, as); 1151 1152 if (info->nb_cpus > 1) { 1153 info->write_secondary_boot(cpu, info); 1154 } 1155 if (info->write_board_setup) { 1156 info->write_board_setup(cpu, info); 1157 } 1158 1159 /* Notify devices which need to fake up firmware initialization 1160 * that we're doing a direct kernel boot. 1161 */ 1162 object_child_foreach_recursive(object_get_root(), 1163 do_arm_linux_init, info); 1164 } 1165 info->is_linux = is_linux; 1166 1167 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1168 ARM_CPU(cs)->env.boot_info = info; 1169 } 1170 1171 if (!info->skip_dtb_autoload && have_dtb(info)) { 1172 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { 1173 exit(1); 1174 } 1175 } 1176 } 1177 1178 static const TypeInfo arm_linux_boot_if_info = { 1179 .name = TYPE_ARM_LINUX_BOOT_IF, 1180 .parent = TYPE_INTERFACE, 1181 .class_size = sizeof(ARMLinuxBootIfClass), 1182 }; 1183 1184 static void arm_linux_boot_register_types(void) 1185 { 1186 type_register_static(&arm_linux_boot_if_info); 1187 } 1188 1189 type_init(arm_linux_boot_register_types) 1190