1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/error-report.h" 12 #include "qapi/error.h" 13 #include <libfdt.h> 14 #include "hw/hw.h" 15 #include "hw/arm/arm.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "sysemu/kvm.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/numa.h" 20 #include "hw/boards.h" 21 #include "hw/loader.h" 22 #include "elf.h" 23 #include "sysemu/device_tree.h" 24 #include "qemu/config-file.h" 25 #include "qemu/option.h" 26 #include "exec/address-spaces.h" 27 #include "qemu/units.h" 28 29 /* Kernel boot protocol is specified in the kernel docs 30 * Documentation/arm/Booting and Documentation/arm64/booting.txt 31 * They have different preferred image load offsets from system RAM base. 32 */ 33 #define KERNEL_ARGS_ADDR 0x100 34 #define KERNEL_LOAD_ADDR 0x00010000 35 #define KERNEL64_LOAD_ADDR 0x00080000 36 37 #define ARM64_TEXT_OFFSET_OFFSET 8 38 #define ARM64_MAGIC_OFFSET 56 39 40 #define BOOTLOADER_MAX_SIZE (4 * KiB) 41 42 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 43 const struct arm_boot_info *info) 44 { 45 /* Return the address space to use for bootloader reads and writes. 46 * We prefer the secure address space if the CPU has it and we're 47 * going to boot the guest into it. 48 */ 49 int asidx; 50 CPUState *cs = CPU(cpu); 51 52 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 53 asidx = ARMASIdx_S; 54 } else { 55 asidx = ARMASIdx_NS; 56 } 57 58 return cpu_get_address_space(cs, asidx); 59 } 60 61 typedef enum { 62 FIXUP_NONE = 0, /* do nothing */ 63 FIXUP_TERMINATOR, /* end of insns */ 64 FIXUP_BOARDID, /* overwrite with board ID number */ 65 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 66 FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */ 67 FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */ 68 FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */ 69 FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */ 70 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 71 FIXUP_BOOTREG, /* overwrite with boot register address */ 72 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 73 FIXUP_MAX, 74 } FixupType; 75 76 typedef struct ARMInsnFixup { 77 uint32_t insn; 78 FixupType fixup; 79 } ARMInsnFixup; 80 81 static const ARMInsnFixup bootloader_aarch64[] = { 82 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 83 { 0xaa1f03e1 }, /* mov x1, xzr */ 84 { 0xaa1f03e2 }, /* mov x2, xzr */ 85 { 0xaa1f03e3 }, /* mov x3, xzr */ 86 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 87 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 88 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ 89 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ 90 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ 91 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ 92 { 0, FIXUP_TERMINATOR } 93 }; 94 95 /* A very small bootloader: call the board-setup code (if needed), 96 * set r0-r2, then jump to the kernel. 97 * If we're not calling boot setup code then we don't copy across 98 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 99 */ 100 101 static const ARMInsnFixup bootloader[] = { 102 { 0xe28fe004 }, /* add lr, pc, #4 */ 103 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 104 { 0, FIXUP_BOARD_SETUP }, 105 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 106 { 0xe3a00000 }, /* mov r0, #0 */ 107 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 108 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 109 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 110 { 0, FIXUP_BOARDID }, 111 { 0, FIXUP_ARGPTR_LO }, 112 { 0, FIXUP_ENTRYPOINT_LO }, 113 { 0, FIXUP_TERMINATOR } 114 }; 115 116 /* Handling for secondary CPU boot in a multicore system. 117 * Unlike the uniprocessor/primary CPU boot, this is platform 118 * dependent. The default code here is based on the secondary 119 * CPU boot protocol used on realview/vexpress boards, with 120 * some parameterisation to increase its flexibility. 121 * QEMU platform models for which this code is not appropriate 122 * should override write_secondary_boot and secondary_cpu_reset_hook 123 * instead. 124 * 125 * This code enables the interrupt controllers for the secondary 126 * CPUs and then puts all the secondary CPUs into a loop waiting 127 * for an interprocessor interrupt and polling a configurable 128 * location for the kernel secondary CPU entry point. 129 */ 130 #define DSB_INSN 0xf57ff04f 131 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 132 133 static const ARMInsnFixup smpboot[] = { 134 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 135 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 136 { 0xe3a01001 }, /* mov r1, #1 */ 137 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 138 { 0xe3a010ff }, /* mov r1, #0xff */ 139 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 140 { 0, FIXUP_DSB }, /* dsb */ 141 { 0xe320f003 }, /* wfi */ 142 { 0xe5901000 }, /* ldr r1, [r0] */ 143 { 0xe1110001 }, /* tst r1, r1 */ 144 { 0x0afffffb }, /* beq <wfi> */ 145 { 0xe12fff11 }, /* bx r1 */ 146 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 147 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 148 { 0, FIXUP_TERMINATOR } 149 }; 150 151 static void write_bootloader(const char *name, hwaddr addr, 152 const ARMInsnFixup *insns, uint32_t *fixupcontext, 153 AddressSpace *as) 154 { 155 /* Fix up the specified bootloader fragment and write it into 156 * guest memory using rom_add_blob_fixed(). fixupcontext is 157 * an array giving the values to write in for the fixup types 158 * which write a value into the code array. 159 */ 160 int i, len; 161 uint32_t *code; 162 163 len = 0; 164 while (insns[len].fixup != FIXUP_TERMINATOR) { 165 len++; 166 } 167 168 code = g_new0(uint32_t, len); 169 170 for (i = 0; i < len; i++) { 171 uint32_t insn = insns[i].insn; 172 FixupType fixup = insns[i].fixup; 173 174 switch (fixup) { 175 case FIXUP_NONE: 176 break; 177 case FIXUP_BOARDID: 178 case FIXUP_BOARD_SETUP: 179 case FIXUP_ARGPTR_LO: 180 case FIXUP_ARGPTR_HI: 181 case FIXUP_ENTRYPOINT_LO: 182 case FIXUP_ENTRYPOINT_HI: 183 case FIXUP_GIC_CPU_IF: 184 case FIXUP_BOOTREG: 185 case FIXUP_DSB: 186 insn = fixupcontext[fixup]; 187 break; 188 default: 189 abort(); 190 } 191 code[i] = tswap32(insn); 192 } 193 194 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 195 196 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 197 198 g_free(code); 199 } 200 201 static void default_write_secondary(ARMCPU *cpu, 202 const struct arm_boot_info *info) 203 { 204 uint32_t fixupcontext[FIXUP_MAX]; 205 AddressSpace *as = arm_boot_address_space(cpu, info); 206 207 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 208 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 209 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 210 fixupcontext[FIXUP_DSB] = DSB_INSN; 211 } else { 212 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 213 } 214 215 write_bootloader("smpboot", info->smp_loader_start, 216 smpboot, fixupcontext, as); 217 } 218 219 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 220 const struct arm_boot_info *info, 221 hwaddr mvbar_addr) 222 { 223 AddressSpace *as = arm_boot_address_space(cpu, info); 224 int n; 225 uint32_t mvbar_blob[] = { 226 /* mvbar_addr: secure monitor vectors 227 * Default unimplemented and unused vectors to spin. Makes it 228 * easier to debug (as opposed to the CPU running away). 229 */ 230 0xeafffffe, /* (spin) */ 231 0xeafffffe, /* (spin) */ 232 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 233 0xeafffffe, /* (spin) */ 234 0xeafffffe, /* (spin) */ 235 0xeafffffe, /* (spin) */ 236 0xeafffffe, /* (spin) */ 237 0xeafffffe, /* (spin) */ 238 }; 239 uint32_t board_setup_blob[] = { 240 /* board setup addr */ 241 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 242 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 243 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 244 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 245 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 246 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 247 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 248 0xe1a0f001, /* mov pc, r1 ;return */ 249 }; 250 251 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 252 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 253 254 /* check that these blobs don't overlap */ 255 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 256 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 257 258 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 259 mvbar_blob[n] = tswap32(mvbar_blob[n]); 260 } 261 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 262 mvbar_addr, as); 263 264 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 265 board_setup_blob[n] = tswap32(board_setup_blob[n]); 266 } 267 rom_add_blob_fixed_as("board-setup", board_setup_blob, 268 sizeof(board_setup_blob), info->board_setup_addr, as); 269 } 270 271 static void default_reset_secondary(ARMCPU *cpu, 272 const struct arm_boot_info *info) 273 { 274 AddressSpace *as = arm_boot_address_space(cpu, info); 275 CPUState *cs = CPU(cpu); 276 277 address_space_stl_notdirty(as, info->smp_bootreg_addr, 278 0, MEMTXATTRS_UNSPECIFIED, NULL); 279 cpu_set_pc(cs, info->smp_loader_start); 280 } 281 282 static inline bool have_dtb(const struct arm_boot_info *info) 283 { 284 return info->dtb_filename || info->get_dtb; 285 } 286 287 #define WRITE_WORD(p, value) do { \ 288 address_space_stl_notdirty(as, p, value, \ 289 MEMTXATTRS_UNSPECIFIED, NULL); \ 290 p += 4; \ 291 } while (0) 292 293 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 294 { 295 int initrd_size = info->initrd_size; 296 hwaddr base = info->loader_start; 297 hwaddr p; 298 299 p = base + KERNEL_ARGS_ADDR; 300 /* ATAG_CORE */ 301 WRITE_WORD(p, 5); 302 WRITE_WORD(p, 0x54410001); 303 WRITE_WORD(p, 1); 304 WRITE_WORD(p, 0x1000); 305 WRITE_WORD(p, 0); 306 /* ATAG_MEM */ 307 /* TODO: handle multiple chips on one ATAG list */ 308 WRITE_WORD(p, 4); 309 WRITE_WORD(p, 0x54410002); 310 WRITE_WORD(p, info->ram_size); 311 WRITE_WORD(p, info->loader_start); 312 if (initrd_size) { 313 /* ATAG_INITRD2 */ 314 WRITE_WORD(p, 4); 315 WRITE_WORD(p, 0x54420005); 316 WRITE_WORD(p, info->initrd_start); 317 WRITE_WORD(p, initrd_size); 318 } 319 if (info->kernel_cmdline && *info->kernel_cmdline) { 320 /* ATAG_CMDLINE */ 321 int cmdline_size; 322 323 cmdline_size = strlen(info->kernel_cmdline); 324 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 325 (const uint8_t *)info->kernel_cmdline, 326 cmdline_size + 1); 327 cmdline_size = (cmdline_size >> 2) + 1; 328 WRITE_WORD(p, cmdline_size + 2); 329 WRITE_WORD(p, 0x54410009); 330 p += cmdline_size * 4; 331 } 332 if (info->atag_board) { 333 /* ATAG_BOARD */ 334 int atag_board_len; 335 uint8_t atag_board_buf[0x1000]; 336 337 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 338 WRITE_WORD(p, (atag_board_len + 8) >> 2); 339 WRITE_WORD(p, 0x414f4d50); 340 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 341 atag_board_buf, atag_board_len); 342 p += atag_board_len; 343 } 344 /* ATAG_END */ 345 WRITE_WORD(p, 0); 346 WRITE_WORD(p, 0); 347 } 348 349 static void set_kernel_args_old(const struct arm_boot_info *info, 350 AddressSpace *as) 351 { 352 hwaddr p; 353 const char *s; 354 int initrd_size = info->initrd_size; 355 hwaddr base = info->loader_start; 356 357 /* see linux/include/asm-arm/setup.h */ 358 p = base + KERNEL_ARGS_ADDR; 359 /* page_size */ 360 WRITE_WORD(p, 4096); 361 /* nr_pages */ 362 WRITE_WORD(p, info->ram_size / 4096); 363 /* ramdisk_size */ 364 WRITE_WORD(p, 0); 365 #define FLAG_READONLY 1 366 #define FLAG_RDLOAD 4 367 #define FLAG_RDPROMPT 8 368 /* flags */ 369 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 370 /* rootdev */ 371 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 372 /* video_num_cols */ 373 WRITE_WORD(p, 0); 374 /* video_num_rows */ 375 WRITE_WORD(p, 0); 376 /* video_x */ 377 WRITE_WORD(p, 0); 378 /* video_y */ 379 WRITE_WORD(p, 0); 380 /* memc_control_reg */ 381 WRITE_WORD(p, 0); 382 /* unsigned char sounddefault */ 383 /* unsigned char adfsdrives */ 384 /* unsigned char bytes_per_char_h */ 385 /* unsigned char bytes_per_char_v */ 386 WRITE_WORD(p, 0); 387 /* pages_in_bank[4] */ 388 WRITE_WORD(p, 0); 389 WRITE_WORD(p, 0); 390 WRITE_WORD(p, 0); 391 WRITE_WORD(p, 0); 392 /* pages_in_vram */ 393 WRITE_WORD(p, 0); 394 /* initrd_start */ 395 if (initrd_size) { 396 WRITE_WORD(p, info->initrd_start); 397 } else { 398 WRITE_WORD(p, 0); 399 } 400 /* initrd_size */ 401 WRITE_WORD(p, initrd_size); 402 /* rd_start */ 403 WRITE_WORD(p, 0); 404 /* system_rev */ 405 WRITE_WORD(p, 0); 406 /* system_serial_low */ 407 WRITE_WORD(p, 0); 408 /* system_serial_high */ 409 WRITE_WORD(p, 0); 410 /* mem_fclk_21285 */ 411 WRITE_WORD(p, 0); 412 /* zero unused fields */ 413 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 414 WRITE_WORD(p, 0); 415 } 416 s = info->kernel_cmdline; 417 if (s) { 418 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 419 (const uint8_t *)s, strlen(s) + 1); 420 } else { 421 WRITE_WORD(p, 0); 422 } 423 } 424 425 static void fdt_add_psci_node(void *fdt) 426 { 427 uint32_t cpu_suspend_fn; 428 uint32_t cpu_off_fn; 429 uint32_t cpu_on_fn; 430 uint32_t migrate_fn; 431 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 432 const char *psci_method; 433 int64_t psci_conduit; 434 int rc; 435 436 psci_conduit = object_property_get_int(OBJECT(armcpu), 437 "psci-conduit", 438 &error_abort); 439 switch (psci_conduit) { 440 case QEMU_PSCI_CONDUIT_DISABLED: 441 return; 442 case QEMU_PSCI_CONDUIT_HVC: 443 psci_method = "hvc"; 444 break; 445 case QEMU_PSCI_CONDUIT_SMC: 446 psci_method = "smc"; 447 break; 448 default: 449 g_assert_not_reached(); 450 } 451 452 /* 453 * If /psci node is present in provided DTB, assume that no fixup 454 * is necessary and all PSCI configuration should be taken as-is 455 */ 456 rc = fdt_path_offset(fdt, "/psci"); 457 if (rc >= 0) { 458 return; 459 } 460 461 qemu_fdt_add_subnode(fdt, "/psci"); 462 if (armcpu->psci_version == 2) { 463 const char comp[] = "arm,psci-0.2\0arm,psci"; 464 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 465 466 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 467 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 468 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 469 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 470 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 471 } else { 472 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 473 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 474 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 475 } 476 } else { 477 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 478 479 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 480 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 481 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 482 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 483 } 484 485 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 486 * to the instruction that should be used to invoke PSCI functions. 487 * However, the device tree binding uses 'method' instead, so that is 488 * what we should use here. 489 */ 490 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 491 492 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 493 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 494 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 495 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 496 } 497 498 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 499 hwaddr addr_limit, AddressSpace *as) 500 { 501 void *fdt = NULL; 502 int size, rc, n = 0; 503 uint32_t acells, scells; 504 char *nodename; 505 unsigned int i; 506 hwaddr mem_base, mem_len; 507 char **node_path; 508 Error *err = NULL; 509 510 if (binfo->dtb_filename) { 511 char *filename; 512 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 513 if (!filename) { 514 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 515 goto fail; 516 } 517 518 fdt = load_device_tree(filename, &size); 519 if (!fdt) { 520 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 521 g_free(filename); 522 goto fail; 523 } 524 g_free(filename); 525 } else { 526 fdt = binfo->get_dtb(binfo, &size); 527 if (!fdt) { 528 fprintf(stderr, "Board was unable to create a dtb blob\n"); 529 goto fail; 530 } 531 } 532 533 if (addr_limit > addr && size > (addr_limit - addr)) { 534 /* Installing the device tree blob at addr would exceed addr_limit. 535 * Whether this constitutes failure is up to the caller to decide, 536 * so just return 0 as size, i.e., no error. 537 */ 538 g_free(fdt); 539 return 0; 540 } 541 542 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 543 NULL, &error_fatal); 544 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 545 NULL, &error_fatal); 546 if (acells == 0 || scells == 0) { 547 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 548 goto fail; 549 } 550 551 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { 552 /* This is user error so deserves a friendlier error message 553 * than the failure of setprop_sized_cells would provide 554 */ 555 fprintf(stderr, "qemu: dtb file not compatible with " 556 "RAM size > 4GB\n"); 557 goto fail; 558 } 559 560 /* nop all root nodes matching /memory or /memory@unit-address */ 561 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 562 if (err) { 563 error_report_err(err); 564 goto fail; 565 } 566 while (node_path[n]) { 567 if (g_str_has_prefix(node_path[n], "/memory")) { 568 qemu_fdt_nop_node(fdt, node_path[n]); 569 } 570 n++; 571 } 572 g_strfreev(node_path); 573 574 if (nb_numa_nodes > 0) { 575 mem_base = binfo->loader_start; 576 for (i = 0; i < nb_numa_nodes; i++) { 577 mem_len = numa_info[i].node_mem; 578 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 579 qemu_fdt_add_subnode(fdt, nodename); 580 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 581 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 582 acells, mem_base, 583 scells, mem_len); 584 if (rc < 0) { 585 fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename, 586 i); 587 goto fail; 588 } 589 590 qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i); 591 mem_base += mem_len; 592 g_free(nodename); 593 } 594 } else { 595 nodename = g_strdup_printf("/memory@%" PRIx64, binfo->loader_start); 596 qemu_fdt_add_subnode(fdt, nodename); 597 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 598 599 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 600 acells, binfo->loader_start, 601 scells, binfo->ram_size); 602 if (rc < 0) { 603 fprintf(stderr, "couldn't set %s reg\n", nodename); 604 goto fail; 605 } 606 g_free(nodename); 607 } 608 609 rc = fdt_path_offset(fdt, "/chosen"); 610 if (rc < 0) { 611 qemu_fdt_add_subnode(fdt, "/chosen"); 612 } 613 614 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { 615 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 616 binfo->kernel_cmdline); 617 if (rc < 0) { 618 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 619 goto fail; 620 } 621 } 622 623 if (binfo->initrd_size) { 624 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 625 binfo->initrd_start); 626 if (rc < 0) { 627 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 628 goto fail; 629 } 630 631 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 632 binfo->initrd_start + binfo->initrd_size); 633 if (rc < 0) { 634 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 635 goto fail; 636 } 637 } 638 639 fdt_add_psci_node(fdt); 640 641 if (binfo->modify_dtb) { 642 binfo->modify_dtb(binfo, fdt); 643 } 644 645 qemu_fdt_dumpdtb(fdt, size); 646 647 /* Put the DTB into the memory map as a ROM image: this will ensure 648 * the DTB is copied again upon reset, even if addr points into RAM. 649 */ 650 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 651 652 g_free(fdt); 653 654 return size; 655 656 fail: 657 g_free(fdt); 658 return -1; 659 } 660 661 static void do_cpu_reset(void *opaque) 662 { 663 ARMCPU *cpu = opaque; 664 CPUState *cs = CPU(cpu); 665 CPUARMState *env = &cpu->env; 666 const struct arm_boot_info *info = env->boot_info; 667 668 cpu_reset(cs); 669 if (info) { 670 if (!info->is_linux) { 671 int i; 672 /* Jump to the entry point. */ 673 uint64_t entry = info->entry; 674 675 switch (info->endianness) { 676 case ARM_ENDIANNESS_LE: 677 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 678 for (i = 1; i < 4; ++i) { 679 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 680 } 681 env->uncached_cpsr &= ~CPSR_E; 682 break; 683 case ARM_ENDIANNESS_BE8: 684 env->cp15.sctlr_el[1] |= SCTLR_E0E; 685 for (i = 1; i < 4; ++i) { 686 env->cp15.sctlr_el[i] |= SCTLR_EE; 687 } 688 env->uncached_cpsr |= CPSR_E; 689 break; 690 case ARM_ENDIANNESS_BE32: 691 env->cp15.sctlr_el[1] |= SCTLR_B; 692 break; 693 case ARM_ENDIANNESS_UNKNOWN: 694 break; /* Board's decision */ 695 default: 696 g_assert_not_reached(); 697 } 698 699 if (!env->aarch64) { 700 env->thumb = info->entry & 1; 701 entry &= 0xfffffffe; 702 } 703 cpu_set_pc(cs, entry); 704 } else { 705 /* If we are booting Linux then we need to check whether we are 706 * booting into secure or non-secure state and adjust the state 707 * accordingly. Out of reset, ARM is defined to be in secure state 708 * (SCR.NS = 0), we change that here if non-secure boot has been 709 * requested. 710 */ 711 if (arm_feature(env, ARM_FEATURE_EL3)) { 712 /* AArch64 is defined to come out of reset into EL3 if enabled. 713 * If we are booting Linux then we need to adjust our EL as 714 * Linux expects us to be in EL2 or EL1. AArch32 resets into 715 * SVC, which Linux expects, so no privilege/exception level to 716 * adjust. 717 */ 718 if (env->aarch64) { 719 env->cp15.scr_el3 |= SCR_RW; 720 if (arm_feature(env, ARM_FEATURE_EL2)) { 721 env->cp15.hcr_el2 |= HCR_RW; 722 env->pstate = PSTATE_MODE_EL2h; 723 } else { 724 env->pstate = PSTATE_MODE_EL1h; 725 } 726 /* AArch64 kernels never boot in secure mode */ 727 assert(!info->secure_boot); 728 /* This hook is only supported for AArch32 currently: 729 * bootloader_aarch64[] will not call the hook, and 730 * the code above has already dropped us into EL2 or EL1. 731 */ 732 assert(!info->secure_board_setup); 733 } 734 735 if (arm_feature(env, ARM_FEATURE_EL2)) { 736 /* If we have EL2 then Linux expects the HVC insn to work */ 737 env->cp15.scr_el3 |= SCR_HCE; 738 } 739 740 /* Set to non-secure if not a secure boot */ 741 if (!info->secure_boot && 742 (cs != first_cpu || !info->secure_board_setup)) { 743 /* Linux expects non-secure state */ 744 env->cp15.scr_el3 |= SCR_NS; 745 } 746 } 747 748 if (!env->aarch64 && !info->secure_boot && 749 arm_feature(env, ARM_FEATURE_EL2)) { 750 /* 751 * This is an AArch32 boot not to Secure state, and 752 * we have Hyp mode available, so boot the kernel into 753 * Hyp mode. This is not how the CPU comes out of reset, 754 * so we need to manually put it there. 755 */ 756 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw); 757 } 758 759 if (cs == first_cpu) { 760 AddressSpace *as = arm_boot_address_space(cpu, info); 761 762 cpu_set_pc(cs, info->loader_start); 763 764 if (!have_dtb(info)) { 765 if (old_param) { 766 set_kernel_args_old(info, as); 767 } else { 768 set_kernel_args(info, as); 769 } 770 } 771 } else { 772 info->secondary_cpu_reset_hook(cpu, info); 773 } 774 } 775 } 776 } 777 778 /** 779 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 780 * by key. 781 * @fw_cfg: The firmware config instance to store the data in. 782 * @size_key: The firmware config key to store the size of the loaded 783 * data under, with fw_cfg_add_i32(). 784 * @data_key: The firmware config key to store the loaded data under, 785 * with fw_cfg_add_bytes(). 786 * @image_name: The name of the image file to load. If it is NULL, the 787 * function returns without doing anything. 788 * @try_decompress: Whether the image should be decompressed (gunzipped) before 789 * adding it to fw_cfg. If decompression fails, the image is 790 * loaded as-is. 791 * 792 * In case of failure, the function prints an error message to stderr and the 793 * process exits with status 1. 794 */ 795 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 796 uint16_t data_key, const char *image_name, 797 bool try_decompress) 798 { 799 size_t size = -1; 800 uint8_t *data; 801 802 if (image_name == NULL) { 803 return; 804 } 805 806 if (try_decompress) { 807 size = load_image_gzipped_buffer(image_name, 808 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 809 } 810 811 if (size == (size_t)-1) { 812 gchar *contents; 813 gsize length; 814 815 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 816 error_report("failed to load \"%s\"", image_name); 817 exit(1); 818 } 819 size = length; 820 data = (uint8_t *)contents; 821 } 822 823 fw_cfg_add_i32(fw_cfg, size_key, size); 824 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 825 } 826 827 static int do_arm_linux_init(Object *obj, void *opaque) 828 { 829 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 830 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 831 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 832 struct arm_boot_info *info = opaque; 833 834 if (albifc->arm_linux_init) { 835 albifc->arm_linux_init(albif, info->secure_boot); 836 } 837 } 838 return 0; 839 } 840 841 static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 842 uint64_t *lowaddr, uint64_t *highaddr, 843 int elf_machine, AddressSpace *as) 844 { 845 bool elf_is64; 846 union { 847 Elf32_Ehdr h32; 848 Elf64_Ehdr h64; 849 } elf_header; 850 int data_swab = 0; 851 bool big_endian; 852 int64_t ret = -1; 853 Error *err = NULL; 854 855 856 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 857 if (err) { 858 error_free(err); 859 return ret; 860 } 861 862 if (elf_is64) { 863 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 864 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 865 : ARM_ENDIANNESS_LE; 866 } else { 867 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 868 if (big_endian) { 869 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 870 info->endianness = ARM_ENDIANNESS_BE8; 871 } else { 872 info->endianness = ARM_ENDIANNESS_BE32; 873 /* In BE32, the CPU has a different view of the per-byte 874 * address map than the rest of the system. BE32 ELF files 875 * are organised such that they can be programmed through 876 * the CPU's per-word byte-reversed view of the world. QEMU 877 * however loads ELF files independently of the CPU. So 878 * tell the ELF loader to byte reverse the data for us. 879 */ 880 data_swab = 2; 881 } 882 } else { 883 info->endianness = ARM_ENDIANNESS_LE; 884 } 885 } 886 887 ret = load_elf_as(info->kernel_filename, NULL, NULL, 888 pentry, lowaddr, highaddr, big_endian, elf_machine, 889 1, data_swab, as); 890 if (ret <= 0) { 891 /* The header loaded but the image didn't */ 892 exit(1); 893 } 894 895 return ret; 896 } 897 898 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 899 hwaddr *entry, AddressSpace *as) 900 { 901 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 902 uint8_t *buffer; 903 int size; 904 905 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 906 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 907 &buffer); 908 909 if (size < 0) { 910 gsize len; 911 912 /* Load as raw file otherwise */ 913 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 914 return -1; 915 } 916 size = len; 917 } 918 919 /* check the arm64 magic header value -- very old kernels may not have it */ 920 if (size > ARM64_MAGIC_OFFSET + 4 && 921 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 922 uint64_t hdrvals[2]; 923 924 /* The arm64 Image header has text_offset and image_size fields at 8 and 925 * 16 bytes into the Image header, respectively. The text_offset field 926 * is only valid if the image_size is non-zero. 927 */ 928 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 929 if (hdrvals[1] != 0) { 930 kernel_load_offset = le64_to_cpu(hdrvals[0]); 931 932 /* 933 * We write our startup "bootloader" at the very bottom of RAM, 934 * so that bit can't be used for the image. Luckily the Image 935 * format specification is that the image requests only an offset 936 * from a 2MB boundary, not an absolute load address. So if the 937 * image requests an offset that might mean it overlaps with the 938 * bootloader, we can just load it starting at 2MB+offset rather 939 * than 0MB + offset. 940 */ 941 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 942 kernel_load_offset += 2 * MiB; 943 } 944 } 945 } 946 947 *entry = mem_base + kernel_load_offset; 948 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 949 950 g_free(buffer); 951 952 return size; 953 } 954 955 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 956 { 957 CPUState *cs; 958 int kernel_size; 959 int initrd_size; 960 int is_linux = 0; 961 uint64_t elf_entry, elf_low_addr, elf_high_addr; 962 int elf_machine; 963 hwaddr entry; 964 static const ARMInsnFixup *primary_loader; 965 AddressSpace *as = arm_boot_address_space(cpu, info); 966 967 /* CPU objects (unlike devices) are not automatically reset on system 968 * reset, so we must always register a handler to do so. If we're 969 * actually loading a kernel, the handler is also responsible for 970 * arranging that we start it correctly. 971 */ 972 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 973 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 974 } 975 976 /* The board code is not supposed to set secure_board_setup unless 977 * running its code in secure mode is actually possible, and KVM 978 * doesn't support secure. 979 */ 980 assert(!(info->secure_board_setup && kvm_enabled())); 981 982 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 983 info->dtb_limit = 0; 984 985 /* Load the kernel. */ 986 if (!info->kernel_filename || info->firmware_loaded) { 987 988 if (have_dtb(info)) { 989 /* If we have a device tree blob, but no kernel to supply it to (or 990 * the kernel is supposed to be loaded by the bootloader), copy the 991 * DTB to the base of RAM for the bootloader to pick up. 992 */ 993 info->dtb_start = info->loader_start; 994 } 995 996 if (info->kernel_filename) { 997 FWCfgState *fw_cfg; 998 bool try_decompressing_kernel; 999 1000 fw_cfg = fw_cfg_find(); 1001 try_decompressing_kernel = arm_feature(&cpu->env, 1002 ARM_FEATURE_AARCH64); 1003 1004 /* Expose the kernel, the command line, and the initrd in fw_cfg. 1005 * We don't process them here at all, it's all left to the 1006 * firmware. 1007 */ 1008 load_image_to_fw_cfg(fw_cfg, 1009 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1010 info->kernel_filename, 1011 try_decompressing_kernel); 1012 load_image_to_fw_cfg(fw_cfg, 1013 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1014 info->initrd_filename, false); 1015 1016 if (info->kernel_cmdline) { 1017 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1018 strlen(info->kernel_cmdline) + 1); 1019 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1020 info->kernel_cmdline); 1021 } 1022 } 1023 1024 /* We will start from address 0 (typically a boot ROM image) in the 1025 * same way as hardware. 1026 */ 1027 return; 1028 } 1029 1030 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1031 primary_loader = bootloader_aarch64; 1032 elf_machine = EM_AARCH64; 1033 } else { 1034 primary_loader = bootloader; 1035 if (!info->write_board_setup) { 1036 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 1037 } 1038 elf_machine = EM_ARM; 1039 } 1040 1041 if (!info->secondary_cpu_reset_hook) { 1042 info->secondary_cpu_reset_hook = default_reset_secondary; 1043 } 1044 if (!info->write_secondary_boot) { 1045 info->write_secondary_boot = default_write_secondary; 1046 } 1047 1048 if (info->nb_cpus == 0) 1049 info->nb_cpus = 1; 1050 1051 /* We want to put the initrd far enough into RAM that when the 1052 * kernel is uncompressed it will not clobber the initrd. However 1053 * on boards without much RAM we must ensure that we still leave 1054 * enough room for a decent sized initrd, and on boards with large 1055 * amounts of RAM we must avoid the initrd being so far up in RAM 1056 * that it is outside lowmem and inaccessible to the kernel. 1057 * So for boards with less than 256MB of RAM we put the initrd 1058 * halfway into RAM, and for boards with 256MB of RAM or more we put 1059 * the initrd at 128MB. 1060 */ 1061 info->initrd_start = info->loader_start + 1062 MIN(info->ram_size / 2, 128 * 1024 * 1024); 1063 1064 /* Assume that raw images are linux kernels, and ELF images are not. */ 1065 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, 1066 &elf_high_addr, elf_machine, as); 1067 if (kernel_size > 0 && have_dtb(info)) { 1068 /* If there is still some room left at the base of RAM, try and put 1069 * the DTB there like we do for images loaded with -bios or -pflash. 1070 */ 1071 if (elf_low_addr > info->loader_start 1072 || elf_high_addr < info->loader_start) { 1073 /* Set elf_low_addr as address limit for arm_load_dtb if it may be 1074 * pointing into RAM, otherwise pass '0' (no limit) 1075 */ 1076 if (elf_low_addr < info->loader_start) { 1077 elf_low_addr = 0; 1078 } 1079 info->dtb_start = info->loader_start; 1080 info->dtb_limit = elf_low_addr; 1081 } 1082 } 1083 entry = elf_entry; 1084 if (kernel_size < 0) { 1085 kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL, 1086 &is_linux, NULL, NULL, as); 1087 } 1088 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1089 kernel_size = load_aarch64_image(info->kernel_filename, 1090 info->loader_start, &entry, as); 1091 is_linux = 1; 1092 } else if (kernel_size < 0) { 1093 /* 32-bit ARM */ 1094 entry = info->loader_start + KERNEL_LOAD_ADDR; 1095 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1096 info->ram_size - KERNEL_LOAD_ADDR, 1097 as); 1098 is_linux = 1; 1099 } 1100 if (kernel_size < 0) { 1101 error_report("could not load kernel '%s'", info->kernel_filename); 1102 exit(1); 1103 } 1104 info->entry = entry; 1105 if (is_linux) { 1106 uint32_t fixupcontext[FIXUP_MAX]; 1107 1108 if (info->initrd_filename) { 1109 initrd_size = load_ramdisk_as(info->initrd_filename, 1110 info->initrd_start, 1111 info->ram_size - info->initrd_start, 1112 as); 1113 if (initrd_size < 0) { 1114 initrd_size = load_image_targphys_as(info->initrd_filename, 1115 info->initrd_start, 1116 info->ram_size - 1117 info->initrd_start, 1118 as); 1119 } 1120 if (initrd_size < 0) { 1121 error_report("could not load initrd '%s'", 1122 info->initrd_filename); 1123 exit(1); 1124 } 1125 } else { 1126 initrd_size = 0; 1127 } 1128 info->initrd_size = initrd_size; 1129 1130 fixupcontext[FIXUP_BOARDID] = info->board_id; 1131 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1132 1133 /* for device tree boot, we pass the DTB directly in r2. Otherwise 1134 * we point to the kernel args. 1135 */ 1136 if (have_dtb(info)) { 1137 hwaddr align; 1138 1139 if (elf_machine == EM_AARCH64) { 1140 /* 1141 * Some AArch64 kernels on early bootup map the fdt region as 1142 * 1143 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1144 * 1145 * Let's play safe and prealign it to 2MB to give us some space. 1146 */ 1147 align = 2 * 1024 * 1024; 1148 } else { 1149 /* 1150 * Some 32bit kernels will trash anything in the 4K page the 1151 * initrd ends in, so make sure the DTB isn't caught up in that. 1152 */ 1153 align = 4096; 1154 } 1155 1156 /* Place the DTB after the initrd in memory with alignment. */ 1157 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1158 align); 1159 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; 1160 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; 1161 } else { 1162 fixupcontext[FIXUP_ARGPTR_LO] = 1163 info->loader_start + KERNEL_ARGS_ADDR; 1164 fixupcontext[FIXUP_ARGPTR_HI] = 1165 (info->loader_start + KERNEL_ARGS_ADDR) >> 32; 1166 if (info->ram_size >= (1ULL << 32)) { 1167 error_report("RAM size must be less than 4GB to boot" 1168 " Linux kernel using ATAGS (try passing a device tree" 1169 " using -dtb)"); 1170 exit(1); 1171 } 1172 } 1173 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; 1174 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; 1175 1176 write_bootloader("bootloader", info->loader_start, 1177 primary_loader, fixupcontext, as); 1178 1179 if (info->nb_cpus > 1) { 1180 info->write_secondary_boot(cpu, info); 1181 } 1182 if (info->write_board_setup) { 1183 info->write_board_setup(cpu, info); 1184 } 1185 1186 /* Notify devices which need to fake up firmware initialization 1187 * that we're doing a direct kernel boot. 1188 */ 1189 object_child_foreach_recursive(object_get_root(), 1190 do_arm_linux_init, info); 1191 } 1192 info->is_linux = is_linux; 1193 1194 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1195 ARM_CPU(cs)->env.boot_info = info; 1196 } 1197 1198 if (!info->skip_dtb_autoload && have_dtb(info)) { 1199 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { 1200 exit(1); 1201 } 1202 } 1203 } 1204 1205 static const TypeInfo arm_linux_boot_if_info = { 1206 .name = TYPE_ARM_LINUX_BOOT_IF, 1207 .parent = TYPE_INTERFACE, 1208 .class_size = sizeof(ARMLinuxBootIfClass), 1209 }; 1210 1211 static void arm_linux_boot_register_types(void) 1212 { 1213 type_register_static(&arm_linux_boot_if_info); 1214 } 1215 1216 type_init(arm_linux_boot_register_types) 1217