1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include <libfdt.h> 13 #include "hw/hw.h" 14 #include "hw/arm/arm.h" 15 #include "hw/arm/linux-boot-if.h" 16 #include "sysemu/kvm.h" 17 #include "sysemu/sysemu.h" 18 #include "sysemu/numa.h" 19 #include "hw/boards.h" 20 #include "hw/loader.h" 21 #include "elf.h" 22 #include "sysemu/device_tree.h" 23 #include "qemu/config-file.h" 24 #include "exec/address-spaces.h" 25 26 /* Kernel boot protocol is specified in the kernel docs 27 * Documentation/arm/Booting and Documentation/arm64/booting.txt 28 * They have different preferred image load offsets from system RAM base. 29 */ 30 #define KERNEL_ARGS_ADDR 0x100 31 #define KERNEL_LOAD_ADDR 0x00010000 32 #define KERNEL64_LOAD_ADDR 0x00080000 33 34 typedef enum { 35 FIXUP_NONE = 0, /* do nothing */ 36 FIXUP_TERMINATOR, /* end of insns */ 37 FIXUP_BOARDID, /* overwrite with board ID number */ 38 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 39 FIXUP_ARGPTR, /* overwrite with pointer to kernel args */ 40 FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */ 41 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 42 FIXUP_BOOTREG, /* overwrite with boot register address */ 43 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 44 FIXUP_MAX, 45 } FixupType; 46 47 typedef struct ARMInsnFixup { 48 uint32_t insn; 49 FixupType fixup; 50 } ARMInsnFixup; 51 52 static const ARMInsnFixup bootloader_aarch64[] = { 53 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 54 { 0xaa1f03e1 }, /* mov x1, xzr */ 55 { 0xaa1f03e2 }, /* mov x2, xzr */ 56 { 0xaa1f03e3 }, /* mov x3, xzr */ 57 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 58 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 59 { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */ 60 { 0 }, /* .word @DTB Higher 32-bits */ 61 { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */ 62 { 0 }, /* .word @Kernel Entry Higher 32-bits */ 63 { 0, FIXUP_TERMINATOR } 64 }; 65 66 /* A very small bootloader: call the board-setup code (if needed), 67 * set r0-r2, then jump to the kernel. 68 * If we're not calling boot setup code then we don't copy across 69 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 70 */ 71 72 static const ARMInsnFixup bootloader[] = { 73 { 0xe28fe004 }, /* add lr, pc, #4 */ 74 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 75 { 0, FIXUP_BOARD_SETUP }, 76 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 77 { 0xe3a00000 }, /* mov r0, #0 */ 78 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 79 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 80 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 81 { 0, FIXUP_BOARDID }, 82 { 0, FIXUP_ARGPTR }, 83 { 0, FIXUP_ENTRYPOINT }, 84 { 0, FIXUP_TERMINATOR } 85 }; 86 87 /* Handling for secondary CPU boot in a multicore system. 88 * Unlike the uniprocessor/primary CPU boot, this is platform 89 * dependent. The default code here is based on the secondary 90 * CPU boot protocol used on realview/vexpress boards, with 91 * some parameterisation to increase its flexibility. 92 * QEMU platform models for which this code is not appropriate 93 * should override write_secondary_boot and secondary_cpu_reset_hook 94 * instead. 95 * 96 * This code enables the interrupt controllers for the secondary 97 * CPUs and then puts all the secondary CPUs into a loop waiting 98 * for an interprocessor interrupt and polling a configurable 99 * location for the kernel secondary CPU entry point. 100 */ 101 #define DSB_INSN 0xf57ff04f 102 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 103 104 static const ARMInsnFixup smpboot[] = { 105 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 106 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 107 { 0xe3a01001 }, /* mov r1, #1 */ 108 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 109 { 0xe3a010ff }, /* mov r1, #0xff */ 110 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 111 { 0, FIXUP_DSB }, /* dsb */ 112 { 0xe320f003 }, /* wfi */ 113 { 0xe5901000 }, /* ldr r1, [r0] */ 114 { 0xe1110001 }, /* tst r1, r1 */ 115 { 0x0afffffb }, /* beq <wfi> */ 116 { 0xe12fff11 }, /* bx r1 */ 117 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 118 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 119 { 0, FIXUP_TERMINATOR } 120 }; 121 122 static void write_bootloader(const char *name, hwaddr addr, 123 const ARMInsnFixup *insns, uint32_t *fixupcontext) 124 { 125 /* Fix up the specified bootloader fragment and write it into 126 * guest memory using rom_add_blob_fixed(). fixupcontext is 127 * an array giving the values to write in for the fixup types 128 * which write a value into the code array. 129 */ 130 int i, len; 131 uint32_t *code; 132 133 len = 0; 134 while (insns[len].fixup != FIXUP_TERMINATOR) { 135 len++; 136 } 137 138 code = g_new0(uint32_t, len); 139 140 for (i = 0; i < len; i++) { 141 uint32_t insn = insns[i].insn; 142 FixupType fixup = insns[i].fixup; 143 144 switch (fixup) { 145 case FIXUP_NONE: 146 break; 147 case FIXUP_BOARDID: 148 case FIXUP_BOARD_SETUP: 149 case FIXUP_ARGPTR: 150 case FIXUP_ENTRYPOINT: 151 case FIXUP_GIC_CPU_IF: 152 case FIXUP_BOOTREG: 153 case FIXUP_DSB: 154 insn = fixupcontext[fixup]; 155 break; 156 default: 157 abort(); 158 } 159 code[i] = tswap32(insn); 160 } 161 162 rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr); 163 164 g_free(code); 165 } 166 167 static void default_write_secondary(ARMCPU *cpu, 168 const struct arm_boot_info *info) 169 { 170 uint32_t fixupcontext[FIXUP_MAX]; 171 172 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 173 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 174 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 175 fixupcontext[FIXUP_DSB] = DSB_INSN; 176 } else { 177 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 178 } 179 180 write_bootloader("smpboot", info->smp_loader_start, 181 smpboot, fixupcontext); 182 } 183 184 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 185 const struct arm_boot_info *info, 186 hwaddr mvbar_addr) 187 { 188 int n; 189 uint32_t mvbar_blob[] = { 190 /* mvbar_addr: secure monitor vectors 191 * Default unimplemented and unused vectors to spin. Makes it 192 * easier to debug (as opposed to the CPU running away). 193 */ 194 0xeafffffe, /* (spin) */ 195 0xeafffffe, /* (spin) */ 196 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 197 0xeafffffe, /* (spin) */ 198 0xeafffffe, /* (spin) */ 199 0xeafffffe, /* (spin) */ 200 0xeafffffe, /* (spin) */ 201 0xeafffffe, /* (spin) */ 202 }; 203 uint32_t board_setup_blob[] = { 204 /* board setup addr */ 205 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 206 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 207 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 208 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 209 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 210 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 211 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 212 0xe1a0f001, /* mov pc, r1 ;return */ 213 }; 214 215 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 216 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 217 218 /* check that these blobs don't overlap */ 219 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 220 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 221 222 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 223 mvbar_blob[n] = tswap32(mvbar_blob[n]); 224 } 225 rom_add_blob_fixed("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 226 mvbar_addr); 227 228 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 229 board_setup_blob[n] = tswap32(board_setup_blob[n]); 230 } 231 rom_add_blob_fixed("board-setup", board_setup_blob, 232 sizeof(board_setup_blob), info->board_setup_addr); 233 } 234 235 static void default_reset_secondary(ARMCPU *cpu, 236 const struct arm_boot_info *info) 237 { 238 CPUState *cs = CPU(cpu); 239 240 address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr, 241 0, MEMTXATTRS_UNSPECIFIED, NULL); 242 cpu_set_pc(cs, info->smp_loader_start); 243 } 244 245 static inline bool have_dtb(const struct arm_boot_info *info) 246 { 247 return info->dtb_filename || info->get_dtb; 248 } 249 250 #define WRITE_WORD(p, value) do { \ 251 address_space_stl_notdirty(&address_space_memory, p, value, \ 252 MEMTXATTRS_UNSPECIFIED, NULL); \ 253 p += 4; \ 254 } while (0) 255 256 static void set_kernel_args(const struct arm_boot_info *info) 257 { 258 int initrd_size = info->initrd_size; 259 hwaddr base = info->loader_start; 260 hwaddr p; 261 262 p = base + KERNEL_ARGS_ADDR; 263 /* ATAG_CORE */ 264 WRITE_WORD(p, 5); 265 WRITE_WORD(p, 0x54410001); 266 WRITE_WORD(p, 1); 267 WRITE_WORD(p, 0x1000); 268 WRITE_WORD(p, 0); 269 /* ATAG_MEM */ 270 /* TODO: handle multiple chips on one ATAG list */ 271 WRITE_WORD(p, 4); 272 WRITE_WORD(p, 0x54410002); 273 WRITE_WORD(p, info->ram_size); 274 WRITE_WORD(p, info->loader_start); 275 if (initrd_size) { 276 /* ATAG_INITRD2 */ 277 WRITE_WORD(p, 4); 278 WRITE_WORD(p, 0x54420005); 279 WRITE_WORD(p, info->initrd_start); 280 WRITE_WORD(p, initrd_size); 281 } 282 if (info->kernel_cmdline && *info->kernel_cmdline) { 283 /* ATAG_CMDLINE */ 284 int cmdline_size; 285 286 cmdline_size = strlen(info->kernel_cmdline); 287 cpu_physical_memory_write(p + 8, info->kernel_cmdline, 288 cmdline_size + 1); 289 cmdline_size = (cmdline_size >> 2) + 1; 290 WRITE_WORD(p, cmdline_size + 2); 291 WRITE_WORD(p, 0x54410009); 292 p += cmdline_size * 4; 293 } 294 if (info->atag_board) { 295 /* ATAG_BOARD */ 296 int atag_board_len; 297 uint8_t atag_board_buf[0x1000]; 298 299 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 300 WRITE_WORD(p, (atag_board_len + 8) >> 2); 301 WRITE_WORD(p, 0x414f4d50); 302 cpu_physical_memory_write(p, atag_board_buf, atag_board_len); 303 p += atag_board_len; 304 } 305 /* ATAG_END */ 306 WRITE_WORD(p, 0); 307 WRITE_WORD(p, 0); 308 } 309 310 static void set_kernel_args_old(const struct arm_boot_info *info) 311 { 312 hwaddr p; 313 const char *s; 314 int initrd_size = info->initrd_size; 315 hwaddr base = info->loader_start; 316 317 /* see linux/include/asm-arm/setup.h */ 318 p = base + KERNEL_ARGS_ADDR; 319 /* page_size */ 320 WRITE_WORD(p, 4096); 321 /* nr_pages */ 322 WRITE_WORD(p, info->ram_size / 4096); 323 /* ramdisk_size */ 324 WRITE_WORD(p, 0); 325 #define FLAG_READONLY 1 326 #define FLAG_RDLOAD 4 327 #define FLAG_RDPROMPT 8 328 /* flags */ 329 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 330 /* rootdev */ 331 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 332 /* video_num_cols */ 333 WRITE_WORD(p, 0); 334 /* video_num_rows */ 335 WRITE_WORD(p, 0); 336 /* video_x */ 337 WRITE_WORD(p, 0); 338 /* video_y */ 339 WRITE_WORD(p, 0); 340 /* memc_control_reg */ 341 WRITE_WORD(p, 0); 342 /* unsigned char sounddefault */ 343 /* unsigned char adfsdrives */ 344 /* unsigned char bytes_per_char_h */ 345 /* unsigned char bytes_per_char_v */ 346 WRITE_WORD(p, 0); 347 /* pages_in_bank[4] */ 348 WRITE_WORD(p, 0); 349 WRITE_WORD(p, 0); 350 WRITE_WORD(p, 0); 351 WRITE_WORD(p, 0); 352 /* pages_in_vram */ 353 WRITE_WORD(p, 0); 354 /* initrd_start */ 355 if (initrd_size) { 356 WRITE_WORD(p, info->initrd_start); 357 } else { 358 WRITE_WORD(p, 0); 359 } 360 /* initrd_size */ 361 WRITE_WORD(p, initrd_size); 362 /* rd_start */ 363 WRITE_WORD(p, 0); 364 /* system_rev */ 365 WRITE_WORD(p, 0); 366 /* system_serial_low */ 367 WRITE_WORD(p, 0); 368 /* system_serial_high */ 369 WRITE_WORD(p, 0); 370 /* mem_fclk_21285 */ 371 WRITE_WORD(p, 0); 372 /* zero unused fields */ 373 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 374 WRITE_WORD(p, 0); 375 } 376 s = info->kernel_cmdline; 377 if (s) { 378 cpu_physical_memory_write(p, s, strlen(s) + 1); 379 } else { 380 WRITE_WORD(p, 0); 381 } 382 } 383 384 /** 385 * load_dtb() - load a device tree binary image into memory 386 * @addr: the address to load the image at 387 * @binfo: struct describing the boot environment 388 * @addr_limit: upper limit of the available memory area at @addr 389 * 390 * Load a device tree supplied by the machine or by the user with the 391 * '-dtb' command line option, and put it at offset @addr in target 392 * memory. 393 * 394 * If @addr_limit contains a meaningful value (i.e., it is strictly greater 395 * than @addr), the device tree is only loaded if its size does not exceed 396 * the limit. 397 * 398 * Returns: the size of the device tree image on success, 399 * 0 if the image size exceeds the limit, 400 * -1 on errors. 401 * 402 * Note: Must not be called unless have_dtb(binfo) is true. 403 */ 404 static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 405 hwaddr addr_limit) 406 { 407 void *fdt = NULL; 408 int size, rc; 409 uint32_t acells, scells; 410 char *nodename; 411 unsigned int i; 412 hwaddr mem_base, mem_len; 413 414 if (binfo->dtb_filename) { 415 char *filename; 416 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 417 if (!filename) { 418 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 419 goto fail; 420 } 421 422 fdt = load_device_tree(filename, &size); 423 if (!fdt) { 424 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 425 g_free(filename); 426 goto fail; 427 } 428 g_free(filename); 429 } else { 430 fdt = binfo->get_dtb(binfo, &size); 431 if (!fdt) { 432 fprintf(stderr, "Board was unable to create a dtb blob\n"); 433 goto fail; 434 } 435 } 436 437 if (addr_limit > addr && size > (addr_limit - addr)) { 438 /* Installing the device tree blob at addr would exceed addr_limit. 439 * Whether this constitutes failure is up to the caller to decide, 440 * so just return 0 as size, i.e., no error. 441 */ 442 g_free(fdt); 443 return 0; 444 } 445 446 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 447 NULL, &error_fatal); 448 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 449 NULL, &error_fatal); 450 if (acells == 0 || scells == 0) { 451 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 452 goto fail; 453 } 454 455 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { 456 /* This is user error so deserves a friendlier error message 457 * than the failure of setprop_sized_cells would provide 458 */ 459 fprintf(stderr, "qemu: dtb file not compatible with " 460 "RAM size > 4GB\n"); 461 goto fail; 462 } 463 464 if (nb_numa_nodes > 0) { 465 /* 466 * Turn the /memory node created before into a NOP node, then create 467 * /memory@addr nodes for all numa nodes respectively. 468 */ 469 qemu_fdt_nop_node(fdt, "/memory"); 470 mem_base = binfo->loader_start; 471 for (i = 0; i < nb_numa_nodes; i++) { 472 mem_len = numa_info[i].node_mem; 473 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 474 qemu_fdt_add_subnode(fdt, nodename); 475 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 476 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 477 acells, mem_base, 478 scells, mem_len); 479 if (rc < 0) { 480 fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename, 481 i); 482 goto fail; 483 } 484 485 qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i); 486 mem_base += mem_len; 487 g_free(nodename); 488 } 489 } else { 490 Error *err = NULL; 491 492 rc = fdt_path_offset(fdt, "/memory"); 493 if (rc < 0) { 494 qemu_fdt_add_subnode(fdt, "/memory"); 495 } 496 497 if (!qemu_fdt_getprop(fdt, "/memory", "device_type", NULL, &err)) { 498 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 499 } 500 501 rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg", 502 acells, binfo->loader_start, 503 scells, binfo->ram_size); 504 if (rc < 0) { 505 fprintf(stderr, "couldn't set /memory/reg\n"); 506 goto fail; 507 } 508 } 509 510 rc = fdt_path_offset(fdt, "/chosen"); 511 if (rc < 0) { 512 qemu_fdt_add_subnode(fdt, "/chosen"); 513 } 514 515 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { 516 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 517 binfo->kernel_cmdline); 518 if (rc < 0) { 519 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 520 goto fail; 521 } 522 } 523 524 if (binfo->initrd_size) { 525 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 526 binfo->initrd_start); 527 if (rc < 0) { 528 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 529 goto fail; 530 } 531 532 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 533 binfo->initrd_start + binfo->initrd_size); 534 if (rc < 0) { 535 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 536 goto fail; 537 } 538 } 539 540 if (binfo->modify_dtb) { 541 binfo->modify_dtb(binfo, fdt); 542 } 543 544 qemu_fdt_dumpdtb(fdt, size); 545 546 /* Put the DTB into the memory map as a ROM image: this will ensure 547 * the DTB is copied again upon reset, even if addr points into RAM. 548 */ 549 rom_add_blob_fixed("dtb", fdt, size, addr); 550 551 g_free(fdt); 552 553 return size; 554 555 fail: 556 g_free(fdt); 557 return -1; 558 } 559 560 static void do_cpu_reset(void *opaque) 561 { 562 ARMCPU *cpu = opaque; 563 CPUState *cs = CPU(cpu); 564 CPUARMState *env = &cpu->env; 565 const struct arm_boot_info *info = env->boot_info; 566 567 cpu_reset(cs); 568 if (info) { 569 if (!info->is_linux) { 570 int i; 571 /* Jump to the entry point. */ 572 uint64_t entry = info->entry; 573 574 switch (info->endianness) { 575 case ARM_ENDIANNESS_LE: 576 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 577 for (i = 1; i < 4; ++i) { 578 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 579 } 580 env->uncached_cpsr &= ~CPSR_E; 581 break; 582 case ARM_ENDIANNESS_BE8: 583 env->cp15.sctlr_el[1] |= SCTLR_E0E; 584 for (i = 1; i < 4; ++i) { 585 env->cp15.sctlr_el[i] |= SCTLR_EE; 586 } 587 env->uncached_cpsr |= CPSR_E; 588 break; 589 case ARM_ENDIANNESS_BE32: 590 env->cp15.sctlr_el[1] |= SCTLR_B; 591 break; 592 case ARM_ENDIANNESS_UNKNOWN: 593 break; /* Board's decision */ 594 default: 595 g_assert_not_reached(); 596 } 597 598 if (!env->aarch64) { 599 env->thumb = info->entry & 1; 600 entry &= 0xfffffffe; 601 } 602 cpu_set_pc(cs, entry); 603 } else { 604 /* If we are booting Linux then we need to check whether we are 605 * booting into secure or non-secure state and adjust the state 606 * accordingly. Out of reset, ARM is defined to be in secure state 607 * (SCR.NS = 0), we change that here if non-secure boot has been 608 * requested. 609 */ 610 if (arm_feature(env, ARM_FEATURE_EL3)) { 611 /* AArch64 is defined to come out of reset into EL3 if enabled. 612 * If we are booting Linux then we need to adjust our EL as 613 * Linux expects us to be in EL2 or EL1. AArch32 resets into 614 * SVC, which Linux expects, so no privilege/exception level to 615 * adjust. 616 */ 617 if (env->aarch64) { 618 env->cp15.scr_el3 |= SCR_RW; 619 if (arm_feature(env, ARM_FEATURE_EL2)) { 620 env->cp15.hcr_el2 |= HCR_RW; 621 env->pstate = PSTATE_MODE_EL2h; 622 } else { 623 env->pstate = PSTATE_MODE_EL1h; 624 } 625 } 626 627 /* Set to non-secure if not a secure boot */ 628 if (!info->secure_boot && 629 (cs != first_cpu || !info->secure_board_setup)) { 630 /* Linux expects non-secure state */ 631 env->cp15.scr_el3 |= SCR_NS; 632 } 633 } 634 635 if (cs == first_cpu) { 636 cpu_set_pc(cs, info->loader_start); 637 638 if (!have_dtb(info)) { 639 if (old_param) { 640 set_kernel_args_old(info); 641 } else { 642 set_kernel_args(info); 643 } 644 } 645 } else { 646 info->secondary_cpu_reset_hook(cpu, info); 647 } 648 } 649 } 650 } 651 652 /** 653 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 654 * by key. 655 * @fw_cfg: The firmware config instance to store the data in. 656 * @size_key: The firmware config key to store the size of the loaded 657 * data under, with fw_cfg_add_i32(). 658 * @data_key: The firmware config key to store the loaded data under, 659 * with fw_cfg_add_bytes(). 660 * @image_name: The name of the image file to load. If it is NULL, the 661 * function returns without doing anything. 662 * @try_decompress: Whether the image should be decompressed (gunzipped) before 663 * adding it to fw_cfg. If decompression fails, the image is 664 * loaded as-is. 665 * 666 * In case of failure, the function prints an error message to stderr and the 667 * process exits with status 1. 668 */ 669 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 670 uint16_t data_key, const char *image_name, 671 bool try_decompress) 672 { 673 size_t size = -1; 674 uint8_t *data; 675 676 if (image_name == NULL) { 677 return; 678 } 679 680 if (try_decompress) { 681 size = load_image_gzipped_buffer(image_name, 682 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 683 } 684 685 if (size == (size_t)-1) { 686 gchar *contents; 687 gsize length; 688 689 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 690 fprintf(stderr, "failed to load \"%s\"\n", image_name); 691 exit(1); 692 } 693 size = length; 694 data = (uint8_t *)contents; 695 } 696 697 fw_cfg_add_i32(fw_cfg, size_key, size); 698 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 699 } 700 701 static int do_arm_linux_init(Object *obj, void *opaque) 702 { 703 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 704 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 705 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 706 struct arm_boot_info *info = opaque; 707 708 if (albifc->arm_linux_init) { 709 albifc->arm_linux_init(albif, info->secure_boot); 710 } 711 } 712 return 0; 713 } 714 715 static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 716 uint64_t *lowaddr, uint64_t *highaddr, 717 int elf_machine) 718 { 719 bool elf_is64; 720 union { 721 Elf32_Ehdr h32; 722 Elf64_Ehdr h64; 723 } elf_header; 724 int data_swab = 0; 725 bool big_endian; 726 uint64_t ret = -1; 727 Error *err = NULL; 728 729 730 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 731 if (err) { 732 return ret; 733 } 734 735 if (elf_is64) { 736 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 737 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 738 : ARM_ENDIANNESS_LE; 739 } else { 740 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 741 if (big_endian) { 742 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 743 info->endianness = ARM_ENDIANNESS_BE8; 744 } else { 745 info->endianness = ARM_ENDIANNESS_BE32; 746 /* In BE32, the CPU has a different view of the per-byte 747 * address map than the rest of the system. BE32 ELF files 748 * are organised such that they can be programmed through 749 * the CPU's per-word byte-reversed view of the world. QEMU 750 * however loads ELF files independently of the CPU. So 751 * tell the ELF loader to byte reverse the data for us. 752 */ 753 data_swab = 2; 754 } 755 } else { 756 info->endianness = ARM_ENDIANNESS_LE; 757 } 758 } 759 760 ret = load_elf(info->kernel_filename, NULL, NULL, 761 pentry, lowaddr, highaddr, big_endian, elf_machine, 762 1, data_swab); 763 if (ret <= 0) { 764 /* The header loaded but the image didn't */ 765 exit(1); 766 } 767 768 return ret; 769 } 770 771 static void arm_load_kernel_notify(Notifier *notifier, void *data) 772 { 773 CPUState *cs; 774 int kernel_size; 775 int initrd_size; 776 int is_linux = 0; 777 uint64_t elf_entry, elf_low_addr, elf_high_addr; 778 int elf_machine; 779 hwaddr entry, kernel_load_offset; 780 static const ARMInsnFixup *primary_loader; 781 ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier, 782 notifier, notifier); 783 ARMCPU *cpu = n->cpu; 784 struct arm_boot_info *info = 785 container_of(n, struct arm_boot_info, load_kernel_notifier); 786 787 /* The board code is not supposed to set secure_board_setup unless 788 * running its code in secure mode is actually possible, and KVM 789 * doesn't support secure. 790 */ 791 assert(!(info->secure_board_setup && kvm_enabled())); 792 793 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 794 795 /* Load the kernel. */ 796 if (!info->kernel_filename || info->firmware_loaded) { 797 798 if (have_dtb(info)) { 799 /* If we have a device tree blob, but no kernel to supply it to (or 800 * the kernel is supposed to be loaded by the bootloader), copy the 801 * DTB to the base of RAM for the bootloader to pick up. 802 */ 803 if (load_dtb(info->loader_start, info, 0) < 0) { 804 exit(1); 805 } 806 } 807 808 if (info->kernel_filename) { 809 FWCfgState *fw_cfg; 810 bool try_decompressing_kernel; 811 812 fw_cfg = fw_cfg_find(); 813 try_decompressing_kernel = arm_feature(&cpu->env, 814 ARM_FEATURE_AARCH64); 815 816 /* Expose the kernel, the command line, and the initrd in fw_cfg. 817 * We don't process them here at all, it's all left to the 818 * firmware. 819 */ 820 load_image_to_fw_cfg(fw_cfg, 821 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 822 info->kernel_filename, 823 try_decompressing_kernel); 824 load_image_to_fw_cfg(fw_cfg, 825 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 826 info->initrd_filename, false); 827 828 if (info->kernel_cmdline) { 829 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 830 strlen(info->kernel_cmdline) + 1); 831 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 832 info->kernel_cmdline); 833 } 834 } 835 836 /* We will start from address 0 (typically a boot ROM image) in the 837 * same way as hardware. 838 */ 839 return; 840 } 841 842 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 843 primary_loader = bootloader_aarch64; 844 kernel_load_offset = KERNEL64_LOAD_ADDR; 845 elf_machine = EM_AARCH64; 846 } else { 847 primary_loader = bootloader; 848 if (!info->write_board_setup) { 849 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 850 } 851 kernel_load_offset = KERNEL_LOAD_ADDR; 852 elf_machine = EM_ARM; 853 } 854 855 if (!info->secondary_cpu_reset_hook) { 856 info->secondary_cpu_reset_hook = default_reset_secondary; 857 } 858 if (!info->write_secondary_boot) { 859 info->write_secondary_boot = default_write_secondary; 860 } 861 862 if (info->nb_cpus == 0) 863 info->nb_cpus = 1; 864 865 /* We want to put the initrd far enough into RAM that when the 866 * kernel is uncompressed it will not clobber the initrd. However 867 * on boards without much RAM we must ensure that we still leave 868 * enough room for a decent sized initrd, and on boards with large 869 * amounts of RAM we must avoid the initrd being so far up in RAM 870 * that it is outside lowmem and inaccessible to the kernel. 871 * So for boards with less than 256MB of RAM we put the initrd 872 * halfway into RAM, and for boards with 256MB of RAM or more we put 873 * the initrd at 128MB. 874 */ 875 info->initrd_start = info->loader_start + 876 MIN(info->ram_size / 2, 128 * 1024 * 1024); 877 878 /* Assume that raw images are linux kernels, and ELF images are not. */ 879 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, 880 &elf_high_addr, elf_machine); 881 if (kernel_size > 0 && have_dtb(info)) { 882 /* If there is still some room left at the base of RAM, try and put 883 * the DTB there like we do for images loaded with -bios or -pflash. 884 */ 885 if (elf_low_addr > info->loader_start 886 || elf_high_addr < info->loader_start) { 887 /* Pass elf_low_addr as address limit to load_dtb if it may be 888 * pointing into RAM, otherwise pass '0' (no limit) 889 */ 890 if (elf_low_addr < info->loader_start) { 891 elf_low_addr = 0; 892 } 893 if (load_dtb(info->loader_start, info, elf_low_addr) < 0) { 894 exit(1); 895 } 896 } 897 } 898 entry = elf_entry; 899 if (kernel_size < 0) { 900 kernel_size = load_uimage(info->kernel_filename, &entry, NULL, 901 &is_linux, NULL, NULL); 902 } 903 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 904 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 905 entry = info->loader_start + kernel_load_offset; 906 kernel_size = load_image_gzipped(info->kernel_filename, entry, 907 info->ram_size - kernel_load_offset); 908 is_linux = 1; 909 } 910 if (kernel_size < 0) { 911 entry = info->loader_start + kernel_load_offset; 912 kernel_size = load_image_targphys(info->kernel_filename, entry, 913 info->ram_size - kernel_load_offset); 914 is_linux = 1; 915 } 916 if (kernel_size < 0) { 917 fprintf(stderr, "qemu: could not load kernel '%s'\n", 918 info->kernel_filename); 919 exit(1); 920 } 921 info->entry = entry; 922 if (is_linux) { 923 uint32_t fixupcontext[FIXUP_MAX]; 924 925 if (info->initrd_filename) { 926 initrd_size = load_ramdisk(info->initrd_filename, 927 info->initrd_start, 928 info->ram_size - 929 info->initrd_start); 930 if (initrd_size < 0) { 931 initrd_size = load_image_targphys(info->initrd_filename, 932 info->initrd_start, 933 info->ram_size - 934 info->initrd_start); 935 } 936 if (initrd_size < 0) { 937 fprintf(stderr, "qemu: could not load initrd '%s'\n", 938 info->initrd_filename); 939 exit(1); 940 } 941 } else { 942 initrd_size = 0; 943 } 944 info->initrd_size = initrd_size; 945 946 fixupcontext[FIXUP_BOARDID] = info->board_id; 947 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 948 949 /* for device tree boot, we pass the DTB directly in r2. Otherwise 950 * we point to the kernel args. 951 */ 952 if (have_dtb(info)) { 953 hwaddr align; 954 hwaddr dtb_start; 955 956 if (elf_machine == EM_AARCH64) { 957 /* 958 * Some AArch64 kernels on early bootup map the fdt region as 959 * 960 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 961 * 962 * Let's play safe and prealign it to 2MB to give us some space. 963 */ 964 align = 2 * 1024 * 1024; 965 } else { 966 /* 967 * Some 32bit kernels will trash anything in the 4K page the 968 * initrd ends in, so make sure the DTB isn't caught up in that. 969 */ 970 align = 4096; 971 } 972 973 /* Place the DTB after the initrd in memory with alignment. */ 974 dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); 975 if (load_dtb(dtb_start, info, 0) < 0) { 976 exit(1); 977 } 978 fixupcontext[FIXUP_ARGPTR] = dtb_start; 979 } else { 980 fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR; 981 if (info->ram_size >= (1ULL << 32)) { 982 fprintf(stderr, "qemu: RAM size must be less than 4GB to boot" 983 " Linux kernel using ATAGS (try passing a device tree" 984 " using -dtb)\n"); 985 exit(1); 986 } 987 } 988 fixupcontext[FIXUP_ENTRYPOINT] = entry; 989 990 write_bootloader("bootloader", info->loader_start, 991 primary_loader, fixupcontext); 992 993 if (info->nb_cpus > 1) { 994 info->write_secondary_boot(cpu, info); 995 } 996 if (info->write_board_setup) { 997 info->write_board_setup(cpu, info); 998 } 999 1000 /* Notify devices which need to fake up firmware initialization 1001 * that we're doing a direct kernel boot. 1002 */ 1003 object_child_foreach_recursive(object_get_root(), 1004 do_arm_linux_init, info); 1005 } 1006 info->is_linux = is_linux; 1007 1008 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { 1009 ARM_CPU(cs)->env.boot_info = info; 1010 } 1011 } 1012 1013 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 1014 { 1015 CPUState *cs; 1016 1017 info->load_kernel_notifier.cpu = cpu; 1018 info->load_kernel_notifier.notifier.notify = arm_load_kernel_notify; 1019 qemu_add_machine_init_done_notifier(&info->load_kernel_notifier.notifier); 1020 1021 /* CPU objects (unlike devices) are not automatically reset on system 1022 * reset, so we must always register a handler to do so. If we're 1023 * actually loading a kernel, the handler is also responsible for 1024 * arranging that we start it correctly. 1025 */ 1026 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { 1027 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1028 } 1029 } 1030 1031 static const TypeInfo arm_linux_boot_if_info = { 1032 .name = TYPE_ARM_LINUX_BOOT_IF, 1033 .parent = TYPE_INTERFACE, 1034 .class_size = sizeof(ARMLinuxBootIfClass), 1035 }; 1036 1037 static void arm_linux_boot_register_types(void) 1038 { 1039 type_register_static(&arm_linux_boot_if_info); 1040 } 1041 1042 type_init(arm_linux_boot_register_types) 1043