1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include <libfdt.h> 13 #include "hw/hw.h" 14 #include "hw/arm/arm.h" 15 #include "hw/arm/linux-boot-if.h" 16 #include "sysemu/kvm.h" 17 #include "sysemu/sysemu.h" 18 #include "sysemu/numa.h" 19 #include "hw/boards.h" 20 #include "hw/loader.h" 21 #include "elf.h" 22 #include "sysemu/device_tree.h" 23 #include "qemu/config-file.h" 24 #include "exec/address-spaces.h" 25 26 /* Kernel boot protocol is specified in the kernel docs 27 * Documentation/arm/Booting and Documentation/arm64/booting.txt 28 * They have different preferred image load offsets from system RAM base. 29 */ 30 #define KERNEL_ARGS_ADDR 0x100 31 #define KERNEL_LOAD_ADDR 0x00010000 32 #define KERNEL64_LOAD_ADDR 0x00080000 33 34 #define ARM64_TEXT_OFFSET_OFFSET 8 35 #define ARM64_MAGIC_OFFSET 56 36 37 typedef enum { 38 FIXUP_NONE = 0, /* do nothing */ 39 FIXUP_TERMINATOR, /* end of insns */ 40 FIXUP_BOARDID, /* overwrite with board ID number */ 41 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 42 FIXUP_ARGPTR, /* overwrite with pointer to kernel args */ 43 FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */ 44 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 45 FIXUP_BOOTREG, /* overwrite with boot register address */ 46 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 47 FIXUP_MAX, 48 } FixupType; 49 50 typedef struct ARMInsnFixup { 51 uint32_t insn; 52 FixupType fixup; 53 } ARMInsnFixup; 54 55 static const ARMInsnFixup bootloader_aarch64[] = { 56 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 57 { 0xaa1f03e1 }, /* mov x1, xzr */ 58 { 0xaa1f03e2 }, /* mov x2, xzr */ 59 { 0xaa1f03e3 }, /* mov x3, xzr */ 60 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 61 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 62 { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */ 63 { 0 }, /* .word @DTB Higher 32-bits */ 64 { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */ 65 { 0 }, /* .word @Kernel Entry Higher 32-bits */ 66 { 0, FIXUP_TERMINATOR } 67 }; 68 69 /* A very small bootloader: call the board-setup code (if needed), 70 * set r0-r2, then jump to the kernel. 71 * If we're not calling boot setup code then we don't copy across 72 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 73 */ 74 75 static const ARMInsnFixup bootloader[] = { 76 { 0xe28fe004 }, /* add lr, pc, #4 */ 77 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 78 { 0, FIXUP_BOARD_SETUP }, 79 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 80 { 0xe3a00000 }, /* mov r0, #0 */ 81 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 82 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 83 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 84 { 0, FIXUP_BOARDID }, 85 { 0, FIXUP_ARGPTR }, 86 { 0, FIXUP_ENTRYPOINT }, 87 { 0, FIXUP_TERMINATOR } 88 }; 89 90 /* Handling for secondary CPU boot in a multicore system. 91 * Unlike the uniprocessor/primary CPU boot, this is platform 92 * dependent. The default code here is based on the secondary 93 * CPU boot protocol used on realview/vexpress boards, with 94 * some parameterisation to increase its flexibility. 95 * QEMU platform models for which this code is not appropriate 96 * should override write_secondary_boot and secondary_cpu_reset_hook 97 * instead. 98 * 99 * This code enables the interrupt controllers for the secondary 100 * CPUs and then puts all the secondary CPUs into a loop waiting 101 * for an interprocessor interrupt and polling a configurable 102 * location for the kernel secondary CPU entry point. 103 */ 104 #define DSB_INSN 0xf57ff04f 105 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 106 107 static const ARMInsnFixup smpboot[] = { 108 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 109 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 110 { 0xe3a01001 }, /* mov r1, #1 */ 111 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 112 { 0xe3a010ff }, /* mov r1, #0xff */ 113 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 114 { 0, FIXUP_DSB }, /* dsb */ 115 { 0xe320f003 }, /* wfi */ 116 { 0xe5901000 }, /* ldr r1, [r0] */ 117 { 0xe1110001 }, /* tst r1, r1 */ 118 { 0x0afffffb }, /* beq <wfi> */ 119 { 0xe12fff11 }, /* bx r1 */ 120 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 121 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 122 { 0, FIXUP_TERMINATOR } 123 }; 124 125 static void write_bootloader(const char *name, hwaddr addr, 126 const ARMInsnFixup *insns, uint32_t *fixupcontext) 127 { 128 /* Fix up the specified bootloader fragment and write it into 129 * guest memory using rom_add_blob_fixed(). fixupcontext is 130 * an array giving the values to write in for the fixup types 131 * which write a value into the code array. 132 */ 133 int i, len; 134 uint32_t *code; 135 136 len = 0; 137 while (insns[len].fixup != FIXUP_TERMINATOR) { 138 len++; 139 } 140 141 code = g_new0(uint32_t, len); 142 143 for (i = 0; i < len; i++) { 144 uint32_t insn = insns[i].insn; 145 FixupType fixup = insns[i].fixup; 146 147 switch (fixup) { 148 case FIXUP_NONE: 149 break; 150 case FIXUP_BOARDID: 151 case FIXUP_BOARD_SETUP: 152 case FIXUP_ARGPTR: 153 case FIXUP_ENTRYPOINT: 154 case FIXUP_GIC_CPU_IF: 155 case FIXUP_BOOTREG: 156 case FIXUP_DSB: 157 insn = fixupcontext[fixup]; 158 break; 159 default: 160 abort(); 161 } 162 code[i] = tswap32(insn); 163 } 164 165 rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr); 166 167 g_free(code); 168 } 169 170 static void default_write_secondary(ARMCPU *cpu, 171 const struct arm_boot_info *info) 172 { 173 uint32_t fixupcontext[FIXUP_MAX]; 174 175 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 176 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 177 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 178 fixupcontext[FIXUP_DSB] = DSB_INSN; 179 } else { 180 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 181 } 182 183 write_bootloader("smpboot", info->smp_loader_start, 184 smpboot, fixupcontext); 185 } 186 187 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 188 const struct arm_boot_info *info, 189 hwaddr mvbar_addr) 190 { 191 int n; 192 uint32_t mvbar_blob[] = { 193 /* mvbar_addr: secure monitor vectors 194 * Default unimplemented and unused vectors to spin. Makes it 195 * easier to debug (as opposed to the CPU running away). 196 */ 197 0xeafffffe, /* (spin) */ 198 0xeafffffe, /* (spin) */ 199 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 200 0xeafffffe, /* (spin) */ 201 0xeafffffe, /* (spin) */ 202 0xeafffffe, /* (spin) */ 203 0xeafffffe, /* (spin) */ 204 0xeafffffe, /* (spin) */ 205 }; 206 uint32_t board_setup_blob[] = { 207 /* board setup addr */ 208 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 209 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 210 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 211 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 212 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 213 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 214 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 215 0xe1a0f001, /* mov pc, r1 ;return */ 216 }; 217 218 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 219 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 220 221 /* check that these blobs don't overlap */ 222 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 223 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 224 225 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 226 mvbar_blob[n] = tswap32(mvbar_blob[n]); 227 } 228 rom_add_blob_fixed("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 229 mvbar_addr); 230 231 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 232 board_setup_blob[n] = tswap32(board_setup_blob[n]); 233 } 234 rom_add_blob_fixed("board-setup", board_setup_blob, 235 sizeof(board_setup_blob), info->board_setup_addr); 236 } 237 238 static void default_reset_secondary(ARMCPU *cpu, 239 const struct arm_boot_info *info) 240 { 241 CPUState *cs = CPU(cpu); 242 243 address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr, 244 0, MEMTXATTRS_UNSPECIFIED, NULL); 245 cpu_set_pc(cs, info->smp_loader_start); 246 } 247 248 static inline bool have_dtb(const struct arm_boot_info *info) 249 { 250 return info->dtb_filename || info->get_dtb; 251 } 252 253 #define WRITE_WORD(p, value) do { \ 254 address_space_stl_notdirty(&address_space_memory, p, value, \ 255 MEMTXATTRS_UNSPECIFIED, NULL); \ 256 p += 4; \ 257 } while (0) 258 259 static void set_kernel_args(const struct arm_boot_info *info) 260 { 261 int initrd_size = info->initrd_size; 262 hwaddr base = info->loader_start; 263 hwaddr p; 264 265 p = base + KERNEL_ARGS_ADDR; 266 /* ATAG_CORE */ 267 WRITE_WORD(p, 5); 268 WRITE_WORD(p, 0x54410001); 269 WRITE_WORD(p, 1); 270 WRITE_WORD(p, 0x1000); 271 WRITE_WORD(p, 0); 272 /* ATAG_MEM */ 273 /* TODO: handle multiple chips on one ATAG list */ 274 WRITE_WORD(p, 4); 275 WRITE_WORD(p, 0x54410002); 276 WRITE_WORD(p, info->ram_size); 277 WRITE_WORD(p, info->loader_start); 278 if (initrd_size) { 279 /* ATAG_INITRD2 */ 280 WRITE_WORD(p, 4); 281 WRITE_WORD(p, 0x54420005); 282 WRITE_WORD(p, info->initrd_start); 283 WRITE_WORD(p, initrd_size); 284 } 285 if (info->kernel_cmdline && *info->kernel_cmdline) { 286 /* ATAG_CMDLINE */ 287 int cmdline_size; 288 289 cmdline_size = strlen(info->kernel_cmdline); 290 cpu_physical_memory_write(p + 8, info->kernel_cmdline, 291 cmdline_size + 1); 292 cmdline_size = (cmdline_size >> 2) + 1; 293 WRITE_WORD(p, cmdline_size + 2); 294 WRITE_WORD(p, 0x54410009); 295 p += cmdline_size * 4; 296 } 297 if (info->atag_board) { 298 /* ATAG_BOARD */ 299 int atag_board_len; 300 uint8_t atag_board_buf[0x1000]; 301 302 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 303 WRITE_WORD(p, (atag_board_len + 8) >> 2); 304 WRITE_WORD(p, 0x414f4d50); 305 cpu_physical_memory_write(p, atag_board_buf, atag_board_len); 306 p += atag_board_len; 307 } 308 /* ATAG_END */ 309 WRITE_WORD(p, 0); 310 WRITE_WORD(p, 0); 311 } 312 313 static void set_kernel_args_old(const struct arm_boot_info *info) 314 { 315 hwaddr p; 316 const char *s; 317 int initrd_size = info->initrd_size; 318 hwaddr base = info->loader_start; 319 320 /* see linux/include/asm-arm/setup.h */ 321 p = base + KERNEL_ARGS_ADDR; 322 /* page_size */ 323 WRITE_WORD(p, 4096); 324 /* nr_pages */ 325 WRITE_WORD(p, info->ram_size / 4096); 326 /* ramdisk_size */ 327 WRITE_WORD(p, 0); 328 #define FLAG_READONLY 1 329 #define FLAG_RDLOAD 4 330 #define FLAG_RDPROMPT 8 331 /* flags */ 332 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 333 /* rootdev */ 334 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 335 /* video_num_cols */ 336 WRITE_WORD(p, 0); 337 /* video_num_rows */ 338 WRITE_WORD(p, 0); 339 /* video_x */ 340 WRITE_WORD(p, 0); 341 /* video_y */ 342 WRITE_WORD(p, 0); 343 /* memc_control_reg */ 344 WRITE_WORD(p, 0); 345 /* unsigned char sounddefault */ 346 /* unsigned char adfsdrives */ 347 /* unsigned char bytes_per_char_h */ 348 /* unsigned char bytes_per_char_v */ 349 WRITE_WORD(p, 0); 350 /* pages_in_bank[4] */ 351 WRITE_WORD(p, 0); 352 WRITE_WORD(p, 0); 353 WRITE_WORD(p, 0); 354 WRITE_WORD(p, 0); 355 /* pages_in_vram */ 356 WRITE_WORD(p, 0); 357 /* initrd_start */ 358 if (initrd_size) { 359 WRITE_WORD(p, info->initrd_start); 360 } else { 361 WRITE_WORD(p, 0); 362 } 363 /* initrd_size */ 364 WRITE_WORD(p, initrd_size); 365 /* rd_start */ 366 WRITE_WORD(p, 0); 367 /* system_rev */ 368 WRITE_WORD(p, 0); 369 /* system_serial_low */ 370 WRITE_WORD(p, 0); 371 /* system_serial_high */ 372 WRITE_WORD(p, 0); 373 /* mem_fclk_21285 */ 374 WRITE_WORD(p, 0); 375 /* zero unused fields */ 376 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 377 WRITE_WORD(p, 0); 378 } 379 s = info->kernel_cmdline; 380 if (s) { 381 cpu_physical_memory_write(p, s, strlen(s) + 1); 382 } else { 383 WRITE_WORD(p, 0); 384 } 385 } 386 387 /** 388 * load_dtb() - load a device tree binary image into memory 389 * @addr: the address to load the image at 390 * @binfo: struct describing the boot environment 391 * @addr_limit: upper limit of the available memory area at @addr 392 * 393 * Load a device tree supplied by the machine or by the user with the 394 * '-dtb' command line option, and put it at offset @addr in target 395 * memory. 396 * 397 * If @addr_limit contains a meaningful value (i.e., it is strictly greater 398 * than @addr), the device tree is only loaded if its size does not exceed 399 * the limit. 400 * 401 * Returns: the size of the device tree image on success, 402 * 0 if the image size exceeds the limit, 403 * -1 on errors. 404 * 405 * Note: Must not be called unless have_dtb(binfo) is true. 406 */ 407 static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 408 hwaddr addr_limit) 409 { 410 void *fdt = NULL; 411 int size, rc; 412 uint32_t acells, scells; 413 char *nodename; 414 unsigned int i; 415 hwaddr mem_base, mem_len; 416 417 if (binfo->dtb_filename) { 418 char *filename; 419 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 420 if (!filename) { 421 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 422 goto fail; 423 } 424 425 fdt = load_device_tree(filename, &size); 426 if (!fdt) { 427 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 428 g_free(filename); 429 goto fail; 430 } 431 g_free(filename); 432 } else { 433 fdt = binfo->get_dtb(binfo, &size); 434 if (!fdt) { 435 fprintf(stderr, "Board was unable to create a dtb blob\n"); 436 goto fail; 437 } 438 } 439 440 if (addr_limit > addr && size > (addr_limit - addr)) { 441 /* Installing the device tree blob at addr would exceed addr_limit. 442 * Whether this constitutes failure is up to the caller to decide, 443 * so just return 0 as size, i.e., no error. 444 */ 445 g_free(fdt); 446 return 0; 447 } 448 449 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 450 NULL, &error_fatal); 451 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 452 NULL, &error_fatal); 453 if (acells == 0 || scells == 0) { 454 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 455 goto fail; 456 } 457 458 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { 459 /* This is user error so deserves a friendlier error message 460 * than the failure of setprop_sized_cells would provide 461 */ 462 fprintf(stderr, "qemu: dtb file not compatible with " 463 "RAM size > 4GB\n"); 464 goto fail; 465 } 466 467 if (nb_numa_nodes > 0) { 468 /* 469 * Turn the /memory node created before into a NOP node, then create 470 * /memory@addr nodes for all numa nodes respectively. 471 */ 472 qemu_fdt_nop_node(fdt, "/memory"); 473 mem_base = binfo->loader_start; 474 for (i = 0; i < nb_numa_nodes; i++) { 475 mem_len = numa_info[i].node_mem; 476 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 477 qemu_fdt_add_subnode(fdt, nodename); 478 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 479 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 480 acells, mem_base, 481 scells, mem_len); 482 if (rc < 0) { 483 fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename, 484 i); 485 goto fail; 486 } 487 488 qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i); 489 mem_base += mem_len; 490 g_free(nodename); 491 } 492 } else { 493 Error *err = NULL; 494 495 rc = fdt_path_offset(fdt, "/memory"); 496 if (rc < 0) { 497 qemu_fdt_add_subnode(fdt, "/memory"); 498 } 499 500 if (!qemu_fdt_getprop(fdt, "/memory", "device_type", NULL, &err)) { 501 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 502 } 503 504 rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg", 505 acells, binfo->loader_start, 506 scells, binfo->ram_size); 507 if (rc < 0) { 508 fprintf(stderr, "couldn't set /memory/reg\n"); 509 goto fail; 510 } 511 } 512 513 rc = fdt_path_offset(fdt, "/chosen"); 514 if (rc < 0) { 515 qemu_fdt_add_subnode(fdt, "/chosen"); 516 } 517 518 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { 519 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 520 binfo->kernel_cmdline); 521 if (rc < 0) { 522 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 523 goto fail; 524 } 525 } 526 527 if (binfo->initrd_size) { 528 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 529 binfo->initrd_start); 530 if (rc < 0) { 531 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 532 goto fail; 533 } 534 535 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 536 binfo->initrd_start + binfo->initrd_size); 537 if (rc < 0) { 538 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 539 goto fail; 540 } 541 } 542 543 if (binfo->modify_dtb) { 544 binfo->modify_dtb(binfo, fdt); 545 } 546 547 qemu_fdt_dumpdtb(fdt, size); 548 549 /* Put the DTB into the memory map as a ROM image: this will ensure 550 * the DTB is copied again upon reset, even if addr points into RAM. 551 */ 552 rom_add_blob_fixed("dtb", fdt, size, addr); 553 554 g_free(fdt); 555 556 return size; 557 558 fail: 559 g_free(fdt); 560 return -1; 561 } 562 563 static void do_cpu_reset(void *opaque) 564 { 565 ARMCPU *cpu = opaque; 566 CPUState *cs = CPU(cpu); 567 CPUARMState *env = &cpu->env; 568 const struct arm_boot_info *info = env->boot_info; 569 570 cpu_reset(cs); 571 if (info) { 572 if (!info->is_linux) { 573 int i; 574 /* Jump to the entry point. */ 575 uint64_t entry = info->entry; 576 577 switch (info->endianness) { 578 case ARM_ENDIANNESS_LE: 579 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 580 for (i = 1; i < 4; ++i) { 581 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 582 } 583 env->uncached_cpsr &= ~CPSR_E; 584 break; 585 case ARM_ENDIANNESS_BE8: 586 env->cp15.sctlr_el[1] |= SCTLR_E0E; 587 for (i = 1; i < 4; ++i) { 588 env->cp15.sctlr_el[i] |= SCTLR_EE; 589 } 590 env->uncached_cpsr |= CPSR_E; 591 break; 592 case ARM_ENDIANNESS_BE32: 593 env->cp15.sctlr_el[1] |= SCTLR_B; 594 break; 595 case ARM_ENDIANNESS_UNKNOWN: 596 break; /* Board's decision */ 597 default: 598 g_assert_not_reached(); 599 } 600 601 if (!env->aarch64) { 602 env->thumb = info->entry & 1; 603 entry &= 0xfffffffe; 604 } 605 cpu_set_pc(cs, entry); 606 } else { 607 /* If we are booting Linux then we need to check whether we are 608 * booting into secure or non-secure state and adjust the state 609 * accordingly. Out of reset, ARM is defined to be in secure state 610 * (SCR.NS = 0), we change that here if non-secure boot has been 611 * requested. 612 */ 613 if (arm_feature(env, ARM_FEATURE_EL3)) { 614 /* AArch64 is defined to come out of reset into EL3 if enabled. 615 * If we are booting Linux then we need to adjust our EL as 616 * Linux expects us to be in EL2 or EL1. AArch32 resets into 617 * SVC, which Linux expects, so no privilege/exception level to 618 * adjust. 619 */ 620 if (env->aarch64) { 621 env->cp15.scr_el3 |= SCR_RW; 622 if (arm_feature(env, ARM_FEATURE_EL2)) { 623 env->cp15.hcr_el2 |= HCR_RW; 624 env->pstate = PSTATE_MODE_EL2h; 625 } else { 626 env->pstate = PSTATE_MODE_EL1h; 627 } 628 } 629 630 /* Set to non-secure if not a secure boot */ 631 if (!info->secure_boot && 632 (cs != first_cpu || !info->secure_board_setup)) { 633 /* Linux expects non-secure state */ 634 env->cp15.scr_el3 |= SCR_NS; 635 } 636 } 637 638 if (cs == first_cpu) { 639 cpu_set_pc(cs, info->loader_start); 640 641 if (!have_dtb(info)) { 642 if (old_param) { 643 set_kernel_args_old(info); 644 } else { 645 set_kernel_args(info); 646 } 647 } 648 } else { 649 info->secondary_cpu_reset_hook(cpu, info); 650 } 651 } 652 } 653 } 654 655 /** 656 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 657 * by key. 658 * @fw_cfg: The firmware config instance to store the data in. 659 * @size_key: The firmware config key to store the size of the loaded 660 * data under, with fw_cfg_add_i32(). 661 * @data_key: The firmware config key to store the loaded data under, 662 * with fw_cfg_add_bytes(). 663 * @image_name: The name of the image file to load. If it is NULL, the 664 * function returns without doing anything. 665 * @try_decompress: Whether the image should be decompressed (gunzipped) before 666 * adding it to fw_cfg. If decompression fails, the image is 667 * loaded as-is. 668 * 669 * In case of failure, the function prints an error message to stderr and the 670 * process exits with status 1. 671 */ 672 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 673 uint16_t data_key, const char *image_name, 674 bool try_decompress) 675 { 676 size_t size = -1; 677 uint8_t *data; 678 679 if (image_name == NULL) { 680 return; 681 } 682 683 if (try_decompress) { 684 size = load_image_gzipped_buffer(image_name, 685 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 686 } 687 688 if (size == (size_t)-1) { 689 gchar *contents; 690 gsize length; 691 692 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 693 fprintf(stderr, "failed to load \"%s\"\n", image_name); 694 exit(1); 695 } 696 size = length; 697 data = (uint8_t *)contents; 698 } 699 700 fw_cfg_add_i32(fw_cfg, size_key, size); 701 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 702 } 703 704 static int do_arm_linux_init(Object *obj, void *opaque) 705 { 706 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 707 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 708 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 709 struct arm_boot_info *info = opaque; 710 711 if (albifc->arm_linux_init) { 712 albifc->arm_linux_init(albif, info->secure_boot); 713 } 714 } 715 return 0; 716 } 717 718 static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 719 uint64_t *lowaddr, uint64_t *highaddr, 720 int elf_machine) 721 { 722 bool elf_is64; 723 union { 724 Elf32_Ehdr h32; 725 Elf64_Ehdr h64; 726 } elf_header; 727 int data_swab = 0; 728 bool big_endian; 729 uint64_t ret = -1; 730 Error *err = NULL; 731 732 733 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 734 if (err) { 735 return ret; 736 } 737 738 if (elf_is64) { 739 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 740 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 741 : ARM_ENDIANNESS_LE; 742 } else { 743 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 744 if (big_endian) { 745 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 746 info->endianness = ARM_ENDIANNESS_BE8; 747 } else { 748 info->endianness = ARM_ENDIANNESS_BE32; 749 /* In BE32, the CPU has a different view of the per-byte 750 * address map than the rest of the system. BE32 ELF files 751 * are organised such that they can be programmed through 752 * the CPU's per-word byte-reversed view of the world. QEMU 753 * however loads ELF files independently of the CPU. So 754 * tell the ELF loader to byte reverse the data for us. 755 */ 756 data_swab = 2; 757 } 758 } else { 759 info->endianness = ARM_ENDIANNESS_LE; 760 } 761 } 762 763 ret = load_elf(info->kernel_filename, NULL, NULL, 764 pentry, lowaddr, highaddr, big_endian, elf_machine, 765 1, data_swab); 766 if (ret <= 0) { 767 /* The header loaded but the image didn't */ 768 exit(1); 769 } 770 771 return ret; 772 } 773 774 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 775 hwaddr *entry) 776 { 777 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 778 uint8_t *buffer; 779 int size; 780 781 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 782 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 783 &buffer); 784 785 if (size < 0) { 786 gsize len; 787 788 /* Load as raw file otherwise */ 789 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 790 return -1; 791 } 792 size = len; 793 } 794 795 /* check the arm64 magic header value -- very old kernels may not have it */ 796 if (memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 797 uint64_t hdrvals[2]; 798 799 /* The arm64 Image header has text_offset and image_size fields at 8 and 800 * 16 bytes into the Image header, respectively. The text_offset field 801 * is only valid if the image_size is non-zero. 802 */ 803 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 804 if (hdrvals[1] != 0) { 805 kernel_load_offset = le64_to_cpu(hdrvals[0]); 806 } 807 } 808 809 *entry = mem_base + kernel_load_offset; 810 rom_add_blob_fixed(filename, buffer, size, *entry); 811 812 g_free(buffer); 813 814 return size; 815 } 816 817 static void arm_load_kernel_notify(Notifier *notifier, void *data) 818 { 819 CPUState *cs; 820 int kernel_size; 821 int initrd_size; 822 int is_linux = 0; 823 uint64_t elf_entry, elf_low_addr, elf_high_addr; 824 int elf_machine; 825 hwaddr entry; 826 static const ARMInsnFixup *primary_loader; 827 ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier, 828 notifier, notifier); 829 ARMCPU *cpu = n->cpu; 830 struct arm_boot_info *info = 831 container_of(n, struct arm_boot_info, load_kernel_notifier); 832 833 /* The board code is not supposed to set secure_board_setup unless 834 * running its code in secure mode is actually possible, and KVM 835 * doesn't support secure. 836 */ 837 assert(!(info->secure_board_setup && kvm_enabled())); 838 839 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 840 841 /* Load the kernel. */ 842 if (!info->kernel_filename || info->firmware_loaded) { 843 844 if (have_dtb(info)) { 845 /* If we have a device tree blob, but no kernel to supply it to (or 846 * the kernel is supposed to be loaded by the bootloader), copy the 847 * DTB to the base of RAM for the bootloader to pick up. 848 */ 849 if (load_dtb(info->loader_start, info, 0) < 0) { 850 exit(1); 851 } 852 } 853 854 if (info->kernel_filename) { 855 FWCfgState *fw_cfg; 856 bool try_decompressing_kernel; 857 858 fw_cfg = fw_cfg_find(); 859 try_decompressing_kernel = arm_feature(&cpu->env, 860 ARM_FEATURE_AARCH64); 861 862 /* Expose the kernel, the command line, and the initrd in fw_cfg. 863 * We don't process them here at all, it's all left to the 864 * firmware. 865 */ 866 load_image_to_fw_cfg(fw_cfg, 867 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 868 info->kernel_filename, 869 try_decompressing_kernel); 870 load_image_to_fw_cfg(fw_cfg, 871 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 872 info->initrd_filename, false); 873 874 if (info->kernel_cmdline) { 875 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 876 strlen(info->kernel_cmdline) + 1); 877 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 878 info->kernel_cmdline); 879 } 880 } 881 882 /* We will start from address 0 (typically a boot ROM image) in the 883 * same way as hardware. 884 */ 885 return; 886 } 887 888 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 889 primary_loader = bootloader_aarch64; 890 elf_machine = EM_AARCH64; 891 } else { 892 primary_loader = bootloader; 893 if (!info->write_board_setup) { 894 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 895 } 896 elf_machine = EM_ARM; 897 } 898 899 if (!info->secondary_cpu_reset_hook) { 900 info->secondary_cpu_reset_hook = default_reset_secondary; 901 } 902 if (!info->write_secondary_boot) { 903 info->write_secondary_boot = default_write_secondary; 904 } 905 906 if (info->nb_cpus == 0) 907 info->nb_cpus = 1; 908 909 /* We want to put the initrd far enough into RAM that when the 910 * kernel is uncompressed it will not clobber the initrd. However 911 * on boards without much RAM we must ensure that we still leave 912 * enough room for a decent sized initrd, and on boards with large 913 * amounts of RAM we must avoid the initrd being so far up in RAM 914 * that it is outside lowmem and inaccessible to the kernel. 915 * So for boards with less than 256MB of RAM we put the initrd 916 * halfway into RAM, and for boards with 256MB of RAM or more we put 917 * the initrd at 128MB. 918 */ 919 info->initrd_start = info->loader_start + 920 MIN(info->ram_size / 2, 128 * 1024 * 1024); 921 922 /* Assume that raw images are linux kernels, and ELF images are not. */ 923 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, 924 &elf_high_addr, elf_machine); 925 if (kernel_size > 0 && have_dtb(info)) { 926 /* If there is still some room left at the base of RAM, try and put 927 * the DTB there like we do for images loaded with -bios or -pflash. 928 */ 929 if (elf_low_addr > info->loader_start 930 || elf_high_addr < info->loader_start) { 931 /* Pass elf_low_addr as address limit to load_dtb if it may be 932 * pointing into RAM, otherwise pass '0' (no limit) 933 */ 934 if (elf_low_addr < info->loader_start) { 935 elf_low_addr = 0; 936 } 937 if (load_dtb(info->loader_start, info, elf_low_addr) < 0) { 938 exit(1); 939 } 940 } 941 } 942 entry = elf_entry; 943 if (kernel_size < 0) { 944 kernel_size = load_uimage(info->kernel_filename, &entry, NULL, 945 &is_linux, NULL, NULL); 946 } 947 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 948 kernel_size = load_aarch64_image(info->kernel_filename, 949 info->loader_start, &entry); 950 is_linux = 1; 951 } else if (kernel_size < 0) { 952 /* 32-bit ARM */ 953 entry = info->loader_start + KERNEL_LOAD_ADDR; 954 kernel_size = load_image_targphys(info->kernel_filename, entry, 955 info->ram_size - KERNEL_LOAD_ADDR); 956 is_linux = 1; 957 } 958 if (kernel_size < 0) { 959 fprintf(stderr, "qemu: could not load kernel '%s'\n", 960 info->kernel_filename); 961 exit(1); 962 } 963 info->entry = entry; 964 if (is_linux) { 965 uint32_t fixupcontext[FIXUP_MAX]; 966 967 if (info->initrd_filename) { 968 initrd_size = load_ramdisk(info->initrd_filename, 969 info->initrd_start, 970 info->ram_size - 971 info->initrd_start); 972 if (initrd_size < 0) { 973 initrd_size = load_image_targphys(info->initrd_filename, 974 info->initrd_start, 975 info->ram_size - 976 info->initrd_start); 977 } 978 if (initrd_size < 0) { 979 fprintf(stderr, "qemu: could not load initrd '%s'\n", 980 info->initrd_filename); 981 exit(1); 982 } 983 } else { 984 initrd_size = 0; 985 } 986 info->initrd_size = initrd_size; 987 988 fixupcontext[FIXUP_BOARDID] = info->board_id; 989 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 990 991 /* for device tree boot, we pass the DTB directly in r2. Otherwise 992 * we point to the kernel args. 993 */ 994 if (have_dtb(info)) { 995 hwaddr align; 996 hwaddr dtb_start; 997 998 if (elf_machine == EM_AARCH64) { 999 /* 1000 * Some AArch64 kernels on early bootup map the fdt region as 1001 * 1002 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1003 * 1004 * Let's play safe and prealign it to 2MB to give us some space. 1005 */ 1006 align = 2 * 1024 * 1024; 1007 } else { 1008 /* 1009 * Some 32bit kernels will trash anything in the 4K page the 1010 * initrd ends in, so make sure the DTB isn't caught up in that. 1011 */ 1012 align = 4096; 1013 } 1014 1015 /* Place the DTB after the initrd in memory with alignment. */ 1016 dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); 1017 if (load_dtb(dtb_start, info, 0) < 0) { 1018 exit(1); 1019 } 1020 fixupcontext[FIXUP_ARGPTR] = dtb_start; 1021 } else { 1022 fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR; 1023 if (info->ram_size >= (1ULL << 32)) { 1024 fprintf(stderr, "qemu: RAM size must be less than 4GB to boot" 1025 " Linux kernel using ATAGS (try passing a device tree" 1026 " using -dtb)\n"); 1027 exit(1); 1028 } 1029 } 1030 fixupcontext[FIXUP_ENTRYPOINT] = entry; 1031 1032 write_bootloader("bootloader", info->loader_start, 1033 primary_loader, fixupcontext); 1034 1035 if (info->nb_cpus > 1) { 1036 info->write_secondary_boot(cpu, info); 1037 } 1038 if (info->write_board_setup) { 1039 info->write_board_setup(cpu, info); 1040 } 1041 1042 /* Notify devices which need to fake up firmware initialization 1043 * that we're doing a direct kernel boot. 1044 */ 1045 object_child_foreach_recursive(object_get_root(), 1046 do_arm_linux_init, info); 1047 } 1048 info->is_linux = is_linux; 1049 1050 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { 1051 ARM_CPU(cs)->env.boot_info = info; 1052 } 1053 } 1054 1055 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 1056 { 1057 CPUState *cs; 1058 1059 info->load_kernel_notifier.cpu = cpu; 1060 info->load_kernel_notifier.notifier.notify = arm_load_kernel_notify; 1061 qemu_add_machine_init_done_notifier(&info->load_kernel_notifier.notifier); 1062 1063 /* CPU objects (unlike devices) are not automatically reset on system 1064 * reset, so we must always register a handler to do so. If we're 1065 * actually loading a kernel, the handler is also responsible for 1066 * arranging that we start it correctly. 1067 */ 1068 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { 1069 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1070 } 1071 } 1072 1073 static const TypeInfo arm_linux_boot_if_info = { 1074 .name = TYPE_ARM_LINUX_BOOT_IF, 1075 .parent = TYPE_INTERFACE, 1076 .class_size = sizeof(ARMLinuxBootIfClass), 1077 }; 1078 1079 static void arm_linux_boot_register_types(void) 1080 { 1081 type_register_static(&arm_linux_boot_if_info); 1082 } 1083 1084 type_init(arm_linux_boot_register_types) 1085