1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu-common.h" 12 #include "qemu/error-report.h" 13 #include "qapi/error.h" 14 #include <libfdt.h> 15 #include "hw/arm/boot.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "sysemu/kvm.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/numa.h" 20 #include "hw/boards.h" 21 #include "sysemu/reset.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "sysemu/device_tree.h" 25 #include "qemu/config-file.h" 26 #include "qemu/option.h" 27 #include "exec/address-spaces.h" 28 #include "qemu/units.h" 29 30 /* Kernel boot protocol is specified in the kernel docs 31 * Documentation/arm/Booting and Documentation/arm64/booting.txt 32 * They have different preferred image load offsets from system RAM base. 33 */ 34 #define KERNEL_ARGS_ADDR 0x100 35 #define KERNEL_NOLOAD_ADDR 0x02000000 36 #define KERNEL_LOAD_ADDR 0x00010000 37 #define KERNEL64_LOAD_ADDR 0x00080000 38 39 #define ARM64_TEXT_OFFSET_OFFSET 8 40 #define ARM64_MAGIC_OFFSET 56 41 42 #define BOOTLOADER_MAX_SIZE (4 * KiB) 43 44 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 45 const struct arm_boot_info *info) 46 { 47 /* Return the address space to use for bootloader reads and writes. 48 * We prefer the secure address space if the CPU has it and we're 49 * going to boot the guest into it. 50 */ 51 int asidx; 52 CPUState *cs = CPU(cpu); 53 54 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 55 asidx = ARMASIdx_S; 56 } else { 57 asidx = ARMASIdx_NS; 58 } 59 60 return cpu_get_address_space(cs, asidx); 61 } 62 63 typedef enum { 64 FIXUP_NONE = 0, /* do nothing */ 65 FIXUP_TERMINATOR, /* end of insns */ 66 FIXUP_BOARDID, /* overwrite with board ID number */ 67 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 68 FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */ 69 FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */ 70 FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */ 71 FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */ 72 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 73 FIXUP_BOOTREG, /* overwrite with boot register address */ 74 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 75 FIXUP_MAX, 76 } FixupType; 77 78 typedef struct ARMInsnFixup { 79 uint32_t insn; 80 FixupType fixup; 81 } ARMInsnFixup; 82 83 static const ARMInsnFixup bootloader_aarch64[] = { 84 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 85 { 0xaa1f03e1 }, /* mov x1, xzr */ 86 { 0xaa1f03e2 }, /* mov x2, xzr */ 87 { 0xaa1f03e3 }, /* mov x3, xzr */ 88 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 89 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 90 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ 91 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ 92 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ 93 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ 94 { 0, FIXUP_TERMINATOR } 95 }; 96 97 /* A very small bootloader: call the board-setup code (if needed), 98 * set r0-r2, then jump to the kernel. 99 * If we're not calling boot setup code then we don't copy across 100 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 101 */ 102 103 static const ARMInsnFixup bootloader[] = { 104 { 0xe28fe004 }, /* add lr, pc, #4 */ 105 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 106 { 0, FIXUP_BOARD_SETUP }, 107 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 108 { 0xe3a00000 }, /* mov r0, #0 */ 109 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 110 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 111 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 112 { 0, FIXUP_BOARDID }, 113 { 0, FIXUP_ARGPTR_LO }, 114 { 0, FIXUP_ENTRYPOINT_LO }, 115 { 0, FIXUP_TERMINATOR } 116 }; 117 118 /* Handling for secondary CPU boot in a multicore system. 119 * Unlike the uniprocessor/primary CPU boot, this is platform 120 * dependent. The default code here is based on the secondary 121 * CPU boot protocol used on realview/vexpress boards, with 122 * some parameterisation to increase its flexibility. 123 * QEMU platform models for which this code is not appropriate 124 * should override write_secondary_boot and secondary_cpu_reset_hook 125 * instead. 126 * 127 * This code enables the interrupt controllers for the secondary 128 * CPUs and then puts all the secondary CPUs into a loop waiting 129 * for an interprocessor interrupt and polling a configurable 130 * location for the kernel secondary CPU entry point. 131 */ 132 #define DSB_INSN 0xf57ff04f 133 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 134 135 static const ARMInsnFixup smpboot[] = { 136 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 137 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 138 { 0xe3a01001 }, /* mov r1, #1 */ 139 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 140 { 0xe3a010ff }, /* mov r1, #0xff */ 141 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 142 { 0, FIXUP_DSB }, /* dsb */ 143 { 0xe320f003 }, /* wfi */ 144 { 0xe5901000 }, /* ldr r1, [r0] */ 145 { 0xe1110001 }, /* tst r1, r1 */ 146 { 0x0afffffb }, /* beq <wfi> */ 147 { 0xe12fff11 }, /* bx r1 */ 148 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 149 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 150 { 0, FIXUP_TERMINATOR } 151 }; 152 153 static void write_bootloader(const char *name, hwaddr addr, 154 const ARMInsnFixup *insns, uint32_t *fixupcontext, 155 AddressSpace *as) 156 { 157 /* Fix up the specified bootloader fragment and write it into 158 * guest memory using rom_add_blob_fixed(). fixupcontext is 159 * an array giving the values to write in for the fixup types 160 * which write a value into the code array. 161 */ 162 int i, len; 163 uint32_t *code; 164 165 len = 0; 166 while (insns[len].fixup != FIXUP_TERMINATOR) { 167 len++; 168 } 169 170 code = g_new0(uint32_t, len); 171 172 for (i = 0; i < len; i++) { 173 uint32_t insn = insns[i].insn; 174 FixupType fixup = insns[i].fixup; 175 176 switch (fixup) { 177 case FIXUP_NONE: 178 break; 179 case FIXUP_BOARDID: 180 case FIXUP_BOARD_SETUP: 181 case FIXUP_ARGPTR_LO: 182 case FIXUP_ARGPTR_HI: 183 case FIXUP_ENTRYPOINT_LO: 184 case FIXUP_ENTRYPOINT_HI: 185 case FIXUP_GIC_CPU_IF: 186 case FIXUP_BOOTREG: 187 case FIXUP_DSB: 188 insn = fixupcontext[fixup]; 189 break; 190 default: 191 abort(); 192 } 193 code[i] = tswap32(insn); 194 } 195 196 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 197 198 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 199 200 g_free(code); 201 } 202 203 static void default_write_secondary(ARMCPU *cpu, 204 const struct arm_boot_info *info) 205 { 206 uint32_t fixupcontext[FIXUP_MAX]; 207 AddressSpace *as = arm_boot_address_space(cpu, info); 208 209 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 210 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 211 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 212 fixupcontext[FIXUP_DSB] = DSB_INSN; 213 } else { 214 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 215 } 216 217 write_bootloader("smpboot", info->smp_loader_start, 218 smpboot, fixupcontext, as); 219 } 220 221 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 222 const struct arm_boot_info *info, 223 hwaddr mvbar_addr) 224 { 225 AddressSpace *as = arm_boot_address_space(cpu, info); 226 int n; 227 uint32_t mvbar_blob[] = { 228 /* mvbar_addr: secure monitor vectors 229 * Default unimplemented and unused vectors to spin. Makes it 230 * easier to debug (as opposed to the CPU running away). 231 */ 232 0xeafffffe, /* (spin) */ 233 0xeafffffe, /* (spin) */ 234 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 235 0xeafffffe, /* (spin) */ 236 0xeafffffe, /* (spin) */ 237 0xeafffffe, /* (spin) */ 238 0xeafffffe, /* (spin) */ 239 0xeafffffe, /* (spin) */ 240 }; 241 uint32_t board_setup_blob[] = { 242 /* board setup addr */ 243 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ 244 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ 245 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ 246 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 247 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 248 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 249 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 250 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 251 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 252 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 253 0xe1a0f001, /* mov pc, r1 ;return */ 254 }; 255 256 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 257 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 258 259 /* check that these blobs don't overlap */ 260 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 261 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 262 263 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 264 mvbar_blob[n] = tswap32(mvbar_blob[n]); 265 } 266 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 267 mvbar_addr, as); 268 269 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 270 board_setup_blob[n] = tswap32(board_setup_blob[n]); 271 } 272 rom_add_blob_fixed_as("board-setup", board_setup_blob, 273 sizeof(board_setup_blob), info->board_setup_addr, as); 274 } 275 276 static void default_reset_secondary(ARMCPU *cpu, 277 const struct arm_boot_info *info) 278 { 279 AddressSpace *as = arm_boot_address_space(cpu, info); 280 CPUState *cs = CPU(cpu); 281 282 address_space_stl_notdirty(as, info->smp_bootreg_addr, 283 0, MEMTXATTRS_UNSPECIFIED, NULL); 284 cpu_set_pc(cs, info->smp_loader_start); 285 } 286 287 static inline bool have_dtb(const struct arm_boot_info *info) 288 { 289 return info->dtb_filename || info->get_dtb; 290 } 291 292 #define WRITE_WORD(p, value) do { \ 293 address_space_stl_notdirty(as, p, value, \ 294 MEMTXATTRS_UNSPECIFIED, NULL); \ 295 p += 4; \ 296 } while (0) 297 298 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 299 { 300 int initrd_size = info->initrd_size; 301 hwaddr base = info->loader_start; 302 hwaddr p; 303 304 p = base + KERNEL_ARGS_ADDR; 305 /* ATAG_CORE */ 306 WRITE_WORD(p, 5); 307 WRITE_WORD(p, 0x54410001); 308 WRITE_WORD(p, 1); 309 WRITE_WORD(p, 0x1000); 310 WRITE_WORD(p, 0); 311 /* ATAG_MEM */ 312 /* TODO: handle multiple chips on one ATAG list */ 313 WRITE_WORD(p, 4); 314 WRITE_WORD(p, 0x54410002); 315 WRITE_WORD(p, info->ram_size); 316 WRITE_WORD(p, info->loader_start); 317 if (initrd_size) { 318 /* ATAG_INITRD2 */ 319 WRITE_WORD(p, 4); 320 WRITE_WORD(p, 0x54420005); 321 WRITE_WORD(p, info->initrd_start); 322 WRITE_WORD(p, initrd_size); 323 } 324 if (info->kernel_cmdline && *info->kernel_cmdline) { 325 /* ATAG_CMDLINE */ 326 int cmdline_size; 327 328 cmdline_size = strlen(info->kernel_cmdline); 329 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 330 (const uint8_t *)info->kernel_cmdline, 331 cmdline_size + 1); 332 cmdline_size = (cmdline_size >> 2) + 1; 333 WRITE_WORD(p, cmdline_size + 2); 334 WRITE_WORD(p, 0x54410009); 335 p += cmdline_size * 4; 336 } 337 if (info->atag_board) { 338 /* ATAG_BOARD */ 339 int atag_board_len; 340 uint8_t atag_board_buf[0x1000]; 341 342 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 343 WRITE_WORD(p, (atag_board_len + 8) >> 2); 344 WRITE_WORD(p, 0x414f4d50); 345 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 346 atag_board_buf, atag_board_len); 347 p += atag_board_len; 348 } 349 /* ATAG_END */ 350 WRITE_WORD(p, 0); 351 WRITE_WORD(p, 0); 352 } 353 354 static void set_kernel_args_old(const struct arm_boot_info *info, 355 AddressSpace *as) 356 { 357 hwaddr p; 358 const char *s; 359 int initrd_size = info->initrd_size; 360 hwaddr base = info->loader_start; 361 362 /* see linux/include/asm-arm/setup.h */ 363 p = base + KERNEL_ARGS_ADDR; 364 /* page_size */ 365 WRITE_WORD(p, 4096); 366 /* nr_pages */ 367 WRITE_WORD(p, info->ram_size / 4096); 368 /* ramdisk_size */ 369 WRITE_WORD(p, 0); 370 #define FLAG_READONLY 1 371 #define FLAG_RDLOAD 4 372 #define FLAG_RDPROMPT 8 373 /* flags */ 374 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 375 /* rootdev */ 376 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 377 /* video_num_cols */ 378 WRITE_WORD(p, 0); 379 /* video_num_rows */ 380 WRITE_WORD(p, 0); 381 /* video_x */ 382 WRITE_WORD(p, 0); 383 /* video_y */ 384 WRITE_WORD(p, 0); 385 /* memc_control_reg */ 386 WRITE_WORD(p, 0); 387 /* unsigned char sounddefault */ 388 /* unsigned char adfsdrives */ 389 /* unsigned char bytes_per_char_h */ 390 /* unsigned char bytes_per_char_v */ 391 WRITE_WORD(p, 0); 392 /* pages_in_bank[4] */ 393 WRITE_WORD(p, 0); 394 WRITE_WORD(p, 0); 395 WRITE_WORD(p, 0); 396 WRITE_WORD(p, 0); 397 /* pages_in_vram */ 398 WRITE_WORD(p, 0); 399 /* initrd_start */ 400 if (initrd_size) { 401 WRITE_WORD(p, info->initrd_start); 402 } else { 403 WRITE_WORD(p, 0); 404 } 405 /* initrd_size */ 406 WRITE_WORD(p, initrd_size); 407 /* rd_start */ 408 WRITE_WORD(p, 0); 409 /* system_rev */ 410 WRITE_WORD(p, 0); 411 /* system_serial_low */ 412 WRITE_WORD(p, 0); 413 /* system_serial_high */ 414 WRITE_WORD(p, 0); 415 /* mem_fclk_21285 */ 416 WRITE_WORD(p, 0); 417 /* zero unused fields */ 418 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 419 WRITE_WORD(p, 0); 420 } 421 s = info->kernel_cmdline; 422 if (s) { 423 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 424 (const uint8_t *)s, strlen(s) + 1); 425 } else { 426 WRITE_WORD(p, 0); 427 } 428 } 429 430 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, 431 uint32_t scells, hwaddr mem_len, 432 int numa_node_id) 433 { 434 char *nodename; 435 int ret; 436 437 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 438 qemu_fdt_add_subnode(fdt, nodename); 439 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 440 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base, 441 scells, mem_len); 442 if (ret < 0) { 443 goto out; 444 } 445 446 /* only set the NUMA ID if it is specified */ 447 if (numa_node_id >= 0) { 448 ret = qemu_fdt_setprop_cell(fdt, nodename, 449 "numa-node-id", numa_node_id); 450 } 451 out: 452 g_free(nodename); 453 return ret; 454 } 455 456 static void fdt_add_psci_node(void *fdt) 457 { 458 uint32_t cpu_suspend_fn; 459 uint32_t cpu_off_fn; 460 uint32_t cpu_on_fn; 461 uint32_t migrate_fn; 462 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 463 const char *psci_method; 464 int64_t psci_conduit; 465 int rc; 466 467 psci_conduit = object_property_get_int(OBJECT(armcpu), 468 "psci-conduit", 469 &error_abort); 470 switch (psci_conduit) { 471 case QEMU_PSCI_CONDUIT_DISABLED: 472 return; 473 case QEMU_PSCI_CONDUIT_HVC: 474 psci_method = "hvc"; 475 break; 476 case QEMU_PSCI_CONDUIT_SMC: 477 psci_method = "smc"; 478 break; 479 default: 480 g_assert_not_reached(); 481 } 482 483 /* 484 * If /psci node is present in provided DTB, assume that no fixup 485 * is necessary and all PSCI configuration should be taken as-is 486 */ 487 rc = fdt_path_offset(fdt, "/psci"); 488 if (rc >= 0) { 489 return; 490 } 491 492 qemu_fdt_add_subnode(fdt, "/psci"); 493 if (armcpu->psci_version == 2) { 494 const char comp[] = "arm,psci-0.2\0arm,psci"; 495 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 496 497 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 498 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 499 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 500 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 501 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 502 } else { 503 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 504 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 505 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 506 } 507 } else { 508 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 509 510 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 511 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 512 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 513 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 514 } 515 516 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 517 * to the instruction that should be used to invoke PSCI functions. 518 * However, the device tree binding uses 'method' instead, so that is 519 * what we should use here. 520 */ 521 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 522 523 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 524 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 525 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 526 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 527 } 528 529 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 530 hwaddr addr_limit, AddressSpace *as, MachineState *ms) 531 { 532 void *fdt = NULL; 533 int size, rc, n = 0; 534 uint32_t acells, scells; 535 unsigned int i; 536 hwaddr mem_base, mem_len; 537 char **node_path; 538 Error *err = NULL; 539 540 if (binfo->dtb_filename) { 541 char *filename; 542 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 543 if (!filename) { 544 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 545 goto fail; 546 } 547 548 fdt = load_device_tree(filename, &size); 549 if (!fdt) { 550 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 551 g_free(filename); 552 goto fail; 553 } 554 g_free(filename); 555 } else { 556 fdt = binfo->get_dtb(binfo, &size); 557 if (!fdt) { 558 fprintf(stderr, "Board was unable to create a dtb blob\n"); 559 goto fail; 560 } 561 } 562 563 if (addr_limit > addr && size > (addr_limit - addr)) { 564 /* Installing the device tree blob at addr would exceed addr_limit. 565 * Whether this constitutes failure is up to the caller to decide, 566 * so just return 0 as size, i.e., no error. 567 */ 568 g_free(fdt); 569 return 0; 570 } 571 572 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 573 NULL, &error_fatal); 574 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 575 NULL, &error_fatal); 576 if (acells == 0 || scells == 0) { 577 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 578 goto fail; 579 } 580 581 if (scells < 2 && binfo->ram_size >= 4 * GiB) { 582 /* This is user error so deserves a friendlier error message 583 * than the failure of setprop_sized_cells would provide 584 */ 585 fprintf(stderr, "qemu: dtb file not compatible with " 586 "RAM size > 4GB\n"); 587 goto fail; 588 } 589 590 /* nop all root nodes matching /memory or /memory@unit-address */ 591 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 592 if (err) { 593 error_report_err(err); 594 goto fail; 595 } 596 while (node_path[n]) { 597 if (g_str_has_prefix(node_path[n], "/memory")) { 598 qemu_fdt_nop_node(fdt, node_path[n]); 599 } 600 n++; 601 } 602 g_strfreev(node_path); 603 604 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) { 605 mem_base = binfo->loader_start; 606 for (i = 0; i < ms->numa_state->num_nodes; i++) { 607 mem_len = ms->numa_state->nodes[i].node_mem; 608 rc = fdt_add_memory_node(fdt, acells, mem_base, 609 scells, mem_len, i); 610 if (rc < 0) { 611 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 612 mem_base); 613 goto fail; 614 } 615 616 mem_base += mem_len; 617 } 618 } else { 619 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start, 620 scells, binfo->ram_size, -1); 621 if (rc < 0) { 622 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 623 binfo->loader_start); 624 goto fail; 625 } 626 } 627 628 rc = fdt_path_offset(fdt, "/chosen"); 629 if (rc < 0) { 630 qemu_fdt_add_subnode(fdt, "/chosen"); 631 } 632 633 if (ms->kernel_cmdline && *ms->kernel_cmdline) { 634 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 635 ms->kernel_cmdline); 636 if (rc < 0) { 637 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 638 goto fail; 639 } 640 } 641 642 if (binfo->initrd_size) { 643 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 644 binfo->initrd_start); 645 if (rc < 0) { 646 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 647 goto fail; 648 } 649 650 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 651 binfo->initrd_start + binfo->initrd_size); 652 if (rc < 0) { 653 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 654 goto fail; 655 } 656 } 657 658 fdt_add_psci_node(fdt); 659 660 if (binfo->modify_dtb) { 661 binfo->modify_dtb(binfo, fdt); 662 } 663 664 qemu_fdt_dumpdtb(fdt, size); 665 666 /* Put the DTB into the memory map as a ROM image: this will ensure 667 * the DTB is copied again upon reset, even if addr points into RAM. 668 */ 669 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 670 671 g_free(fdt); 672 673 return size; 674 675 fail: 676 g_free(fdt); 677 return -1; 678 } 679 680 static void do_cpu_reset(void *opaque) 681 { 682 ARMCPU *cpu = opaque; 683 CPUState *cs = CPU(cpu); 684 CPUARMState *env = &cpu->env; 685 const struct arm_boot_info *info = env->boot_info; 686 687 cpu_reset(cs); 688 if (info) { 689 if (!info->is_linux) { 690 int i; 691 /* Jump to the entry point. */ 692 uint64_t entry = info->entry; 693 694 switch (info->endianness) { 695 case ARM_ENDIANNESS_LE: 696 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 697 for (i = 1; i < 4; ++i) { 698 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 699 } 700 env->uncached_cpsr &= ~CPSR_E; 701 break; 702 case ARM_ENDIANNESS_BE8: 703 env->cp15.sctlr_el[1] |= SCTLR_E0E; 704 for (i = 1; i < 4; ++i) { 705 env->cp15.sctlr_el[i] |= SCTLR_EE; 706 } 707 env->uncached_cpsr |= CPSR_E; 708 break; 709 case ARM_ENDIANNESS_BE32: 710 env->cp15.sctlr_el[1] |= SCTLR_B; 711 break; 712 case ARM_ENDIANNESS_UNKNOWN: 713 break; /* Board's decision */ 714 default: 715 g_assert_not_reached(); 716 } 717 718 cpu_set_pc(cs, entry); 719 } else { 720 /* If we are booting Linux then we need to check whether we are 721 * booting into secure or non-secure state and adjust the state 722 * accordingly. Out of reset, ARM is defined to be in secure state 723 * (SCR.NS = 0), we change that here if non-secure boot has been 724 * requested. 725 */ 726 if (arm_feature(env, ARM_FEATURE_EL3)) { 727 /* AArch64 is defined to come out of reset into EL3 if enabled. 728 * If we are booting Linux then we need to adjust our EL as 729 * Linux expects us to be in EL2 or EL1. AArch32 resets into 730 * SVC, which Linux expects, so no privilege/exception level to 731 * adjust. 732 */ 733 if (env->aarch64) { 734 env->cp15.scr_el3 |= SCR_RW; 735 if (arm_feature(env, ARM_FEATURE_EL2)) { 736 env->cp15.hcr_el2 |= HCR_RW; 737 env->pstate = PSTATE_MODE_EL2h; 738 } else { 739 env->pstate = PSTATE_MODE_EL1h; 740 } 741 /* AArch64 kernels never boot in secure mode */ 742 assert(!info->secure_boot); 743 /* This hook is only supported for AArch32 currently: 744 * bootloader_aarch64[] will not call the hook, and 745 * the code above has already dropped us into EL2 or EL1. 746 */ 747 assert(!info->secure_board_setup); 748 } 749 750 if (arm_feature(env, ARM_FEATURE_EL2)) { 751 /* If we have EL2 then Linux expects the HVC insn to work */ 752 env->cp15.scr_el3 |= SCR_HCE; 753 } 754 755 /* Set to non-secure if not a secure boot */ 756 if (!info->secure_boot && 757 (cs != first_cpu || !info->secure_board_setup)) { 758 /* Linux expects non-secure state */ 759 env->cp15.scr_el3 |= SCR_NS; 760 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 761 env->cp15.nsacr |= 3 << 10; 762 } 763 } 764 765 if (!env->aarch64 && !info->secure_boot && 766 arm_feature(env, ARM_FEATURE_EL2)) { 767 /* 768 * This is an AArch32 boot not to Secure state, and 769 * we have Hyp mode available, so boot the kernel into 770 * Hyp mode. This is not how the CPU comes out of reset, 771 * so we need to manually put it there. 772 */ 773 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw); 774 } 775 776 if (cs == first_cpu) { 777 AddressSpace *as = arm_boot_address_space(cpu, info); 778 779 cpu_set_pc(cs, info->loader_start); 780 781 if (!have_dtb(info)) { 782 if (old_param) { 783 set_kernel_args_old(info, as); 784 } else { 785 set_kernel_args(info, as); 786 } 787 } 788 } else { 789 info->secondary_cpu_reset_hook(cpu, info); 790 } 791 } 792 arm_rebuild_hflags(env); 793 } 794 } 795 796 /** 797 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 798 * by key. 799 * @fw_cfg: The firmware config instance to store the data in. 800 * @size_key: The firmware config key to store the size of the loaded 801 * data under, with fw_cfg_add_i32(). 802 * @data_key: The firmware config key to store the loaded data under, 803 * with fw_cfg_add_bytes(). 804 * @image_name: The name of the image file to load. If it is NULL, the 805 * function returns without doing anything. 806 * @try_decompress: Whether the image should be decompressed (gunzipped) before 807 * adding it to fw_cfg. If decompression fails, the image is 808 * loaded as-is. 809 * 810 * In case of failure, the function prints an error message to stderr and the 811 * process exits with status 1. 812 */ 813 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 814 uint16_t data_key, const char *image_name, 815 bool try_decompress) 816 { 817 size_t size = -1; 818 uint8_t *data; 819 820 if (image_name == NULL) { 821 return; 822 } 823 824 if (try_decompress) { 825 size = load_image_gzipped_buffer(image_name, 826 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 827 } 828 829 if (size == (size_t)-1) { 830 gchar *contents; 831 gsize length; 832 833 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 834 error_report("failed to load \"%s\"", image_name); 835 exit(1); 836 } 837 size = length; 838 data = (uint8_t *)contents; 839 } 840 841 fw_cfg_add_i32(fw_cfg, size_key, size); 842 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 843 } 844 845 static int do_arm_linux_init(Object *obj, void *opaque) 846 { 847 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 848 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 849 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 850 struct arm_boot_info *info = opaque; 851 852 if (albifc->arm_linux_init) { 853 albifc->arm_linux_init(albif, info->secure_boot); 854 } 855 } 856 return 0; 857 } 858 859 static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 860 uint64_t *lowaddr, uint64_t *highaddr, 861 int elf_machine, AddressSpace *as) 862 { 863 bool elf_is64; 864 union { 865 Elf32_Ehdr h32; 866 Elf64_Ehdr h64; 867 } elf_header; 868 int data_swab = 0; 869 bool big_endian; 870 int64_t ret = -1; 871 Error *err = NULL; 872 873 874 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 875 if (err) { 876 error_free(err); 877 return ret; 878 } 879 880 if (elf_is64) { 881 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 882 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 883 : ARM_ENDIANNESS_LE; 884 } else { 885 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 886 if (big_endian) { 887 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 888 info->endianness = ARM_ENDIANNESS_BE8; 889 } else { 890 info->endianness = ARM_ENDIANNESS_BE32; 891 /* In BE32, the CPU has a different view of the per-byte 892 * address map than the rest of the system. BE32 ELF files 893 * are organised such that they can be programmed through 894 * the CPU's per-word byte-reversed view of the world. QEMU 895 * however loads ELF files independently of the CPU. So 896 * tell the ELF loader to byte reverse the data for us. 897 */ 898 data_swab = 2; 899 } 900 } else { 901 info->endianness = ARM_ENDIANNESS_LE; 902 } 903 } 904 905 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL, 906 pentry, lowaddr, highaddr, big_endian, elf_machine, 907 1, data_swab, as); 908 if (ret <= 0) { 909 /* The header loaded but the image didn't */ 910 exit(1); 911 } 912 913 return ret; 914 } 915 916 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 917 hwaddr *entry, AddressSpace *as) 918 { 919 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 920 uint64_t kernel_size = 0; 921 uint8_t *buffer; 922 int size; 923 924 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 925 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 926 &buffer); 927 928 if (size < 0) { 929 gsize len; 930 931 /* Load as raw file otherwise */ 932 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 933 return -1; 934 } 935 size = len; 936 } 937 938 /* check the arm64 magic header value -- very old kernels may not have it */ 939 if (size > ARM64_MAGIC_OFFSET + 4 && 940 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 941 uint64_t hdrvals[2]; 942 943 /* The arm64 Image header has text_offset and image_size fields at 8 and 944 * 16 bytes into the Image header, respectively. The text_offset field 945 * is only valid if the image_size is non-zero. 946 */ 947 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 948 949 kernel_size = le64_to_cpu(hdrvals[1]); 950 951 if (kernel_size != 0) { 952 kernel_load_offset = le64_to_cpu(hdrvals[0]); 953 954 /* 955 * We write our startup "bootloader" at the very bottom of RAM, 956 * so that bit can't be used for the image. Luckily the Image 957 * format specification is that the image requests only an offset 958 * from a 2MB boundary, not an absolute load address. So if the 959 * image requests an offset that might mean it overlaps with the 960 * bootloader, we can just load it starting at 2MB+offset rather 961 * than 0MB + offset. 962 */ 963 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 964 kernel_load_offset += 2 * MiB; 965 } 966 } 967 } 968 969 /* 970 * Kernels before v3.17 don't populate the image_size field, and 971 * raw images have no header. For those our best guess at the size 972 * is the size of the Image file itself. 973 */ 974 if (kernel_size == 0) { 975 kernel_size = size; 976 } 977 978 *entry = mem_base + kernel_load_offset; 979 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 980 981 g_free(buffer); 982 983 return kernel_size; 984 } 985 986 static void arm_setup_direct_kernel_boot(ARMCPU *cpu, 987 struct arm_boot_info *info) 988 { 989 /* Set up for a direct boot of a kernel image file. */ 990 CPUState *cs; 991 AddressSpace *as = arm_boot_address_space(cpu, info); 992 int kernel_size; 993 int initrd_size; 994 int is_linux = 0; 995 uint64_t elf_entry; 996 /* Addresses of first byte used and first byte not used by the image */ 997 uint64_t image_low_addr = 0, image_high_addr = 0; 998 int elf_machine; 999 hwaddr entry; 1000 static const ARMInsnFixup *primary_loader; 1001 uint64_t ram_end = info->loader_start + info->ram_size; 1002 1003 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1004 primary_loader = bootloader_aarch64; 1005 elf_machine = EM_AARCH64; 1006 } else { 1007 primary_loader = bootloader; 1008 if (!info->write_board_setup) { 1009 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 1010 } 1011 elf_machine = EM_ARM; 1012 } 1013 1014 if (!info->secondary_cpu_reset_hook) { 1015 info->secondary_cpu_reset_hook = default_reset_secondary; 1016 } 1017 if (!info->write_secondary_boot) { 1018 info->write_secondary_boot = default_write_secondary; 1019 } 1020 1021 if (info->nb_cpus == 0) 1022 info->nb_cpus = 1; 1023 1024 /* Assume that raw images are linux kernels, and ELF images are not. */ 1025 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr, 1026 &image_high_addr, elf_machine, as); 1027 if (kernel_size > 0 && have_dtb(info)) { 1028 /* 1029 * If there is still some room left at the base of RAM, try and put 1030 * the DTB there like we do for images loaded with -bios or -pflash. 1031 */ 1032 if (image_low_addr > info->loader_start 1033 || image_high_addr < info->loader_start) { 1034 /* 1035 * Set image_low_addr as address limit for arm_load_dtb if it may be 1036 * pointing into RAM, otherwise pass '0' (no limit) 1037 */ 1038 if (image_low_addr < info->loader_start) { 1039 image_low_addr = 0; 1040 } 1041 info->dtb_start = info->loader_start; 1042 info->dtb_limit = image_low_addr; 1043 } 1044 } 1045 entry = elf_entry; 1046 if (kernel_size < 0) { 1047 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; 1048 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, 1049 &is_linux, NULL, NULL, as); 1050 if (kernel_size >= 0) { 1051 image_low_addr = loadaddr; 1052 image_high_addr = image_low_addr + kernel_size; 1053 } 1054 } 1055 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1056 kernel_size = load_aarch64_image(info->kernel_filename, 1057 info->loader_start, &entry, as); 1058 is_linux = 1; 1059 if (kernel_size >= 0) { 1060 image_low_addr = entry; 1061 image_high_addr = image_low_addr + kernel_size; 1062 } 1063 } else if (kernel_size < 0) { 1064 /* 32-bit ARM */ 1065 entry = info->loader_start + KERNEL_LOAD_ADDR; 1066 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1067 ram_end - KERNEL_LOAD_ADDR, as); 1068 is_linux = 1; 1069 if (kernel_size >= 0) { 1070 image_low_addr = entry; 1071 image_high_addr = image_low_addr + kernel_size; 1072 } 1073 } 1074 if (kernel_size < 0) { 1075 error_report("could not load kernel '%s'", info->kernel_filename); 1076 exit(1); 1077 } 1078 1079 if (kernel_size > info->ram_size) { 1080 error_report("kernel '%s' is too large to fit in RAM " 1081 "(kernel size %d, RAM size %" PRId64 ")", 1082 info->kernel_filename, kernel_size, info->ram_size); 1083 exit(1); 1084 } 1085 1086 info->entry = entry; 1087 1088 /* 1089 * We want to put the initrd far enough into RAM that when the 1090 * kernel is uncompressed it will not clobber the initrd. However 1091 * on boards without much RAM we must ensure that we still leave 1092 * enough room for a decent sized initrd, and on boards with large 1093 * amounts of RAM we must avoid the initrd being so far up in RAM 1094 * that it is outside lowmem and inaccessible to the kernel. 1095 * So for boards with less than 256MB of RAM we put the initrd 1096 * halfway into RAM, and for boards with 256MB of RAM or more we put 1097 * the initrd at 128MB. 1098 * We also refuse to put the initrd somewhere that will definitely 1099 * overlay the kernel we just loaded, though for kernel formats which 1100 * don't tell us their exact size (eg self-decompressing 32-bit kernels) 1101 * we might still make a bad choice here. 1102 */ 1103 info->initrd_start = info->loader_start + 1104 MIN(info->ram_size / 2, 128 * MiB); 1105 if (image_high_addr) { 1106 info->initrd_start = MAX(info->initrd_start, image_high_addr); 1107 } 1108 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); 1109 1110 if (is_linux) { 1111 uint32_t fixupcontext[FIXUP_MAX]; 1112 1113 if (info->initrd_filename) { 1114 1115 if (info->initrd_start >= ram_end) { 1116 error_report("not enough space after kernel to load initrd"); 1117 exit(1); 1118 } 1119 1120 initrd_size = load_ramdisk_as(info->initrd_filename, 1121 info->initrd_start, 1122 ram_end - info->initrd_start, as); 1123 if (initrd_size < 0) { 1124 initrd_size = load_image_targphys_as(info->initrd_filename, 1125 info->initrd_start, 1126 ram_end - 1127 info->initrd_start, 1128 as); 1129 } 1130 if (initrd_size < 0) { 1131 error_report("could not load initrd '%s'", 1132 info->initrd_filename); 1133 exit(1); 1134 } 1135 if (info->initrd_start + initrd_size > ram_end) { 1136 error_report("could not load initrd '%s': " 1137 "too big to fit into RAM after the kernel", 1138 info->initrd_filename); 1139 exit(1); 1140 } 1141 } else { 1142 initrd_size = 0; 1143 } 1144 info->initrd_size = initrd_size; 1145 1146 fixupcontext[FIXUP_BOARDID] = info->board_id; 1147 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1148 1149 /* 1150 * for device tree boot, we pass the DTB directly in r2. Otherwise 1151 * we point to the kernel args. 1152 */ 1153 if (have_dtb(info)) { 1154 hwaddr align; 1155 1156 if (elf_machine == EM_AARCH64) { 1157 /* 1158 * Some AArch64 kernels on early bootup map the fdt region as 1159 * 1160 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1161 * 1162 * Let's play safe and prealign it to 2MB to give us some space. 1163 */ 1164 align = 2 * MiB; 1165 } else { 1166 /* 1167 * Some 32bit kernels will trash anything in the 4K page the 1168 * initrd ends in, so make sure the DTB isn't caught up in that. 1169 */ 1170 align = 4 * KiB; 1171 } 1172 1173 /* Place the DTB after the initrd in memory with alignment. */ 1174 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1175 align); 1176 if (info->dtb_start >= ram_end) { 1177 error_report("Not enough space for DTB after kernel/initrd"); 1178 exit(1); 1179 } 1180 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; 1181 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; 1182 } else { 1183 fixupcontext[FIXUP_ARGPTR_LO] = 1184 info->loader_start + KERNEL_ARGS_ADDR; 1185 fixupcontext[FIXUP_ARGPTR_HI] = 1186 (info->loader_start + KERNEL_ARGS_ADDR) >> 32; 1187 if (info->ram_size >= 4 * GiB) { 1188 error_report("RAM size must be less than 4GB to boot" 1189 " Linux kernel using ATAGS (try passing a device tree" 1190 " using -dtb)"); 1191 exit(1); 1192 } 1193 } 1194 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; 1195 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; 1196 1197 write_bootloader("bootloader", info->loader_start, 1198 primary_loader, fixupcontext, as); 1199 1200 if (info->nb_cpus > 1) { 1201 info->write_secondary_boot(cpu, info); 1202 } 1203 if (info->write_board_setup) { 1204 info->write_board_setup(cpu, info); 1205 } 1206 1207 /* 1208 * Notify devices which need to fake up firmware initialization 1209 * that we're doing a direct kernel boot. 1210 */ 1211 object_child_foreach_recursive(object_get_root(), 1212 do_arm_linux_init, info); 1213 } 1214 info->is_linux = is_linux; 1215 1216 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1217 ARM_CPU(cs)->env.boot_info = info; 1218 } 1219 } 1220 1221 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) 1222 { 1223 /* Set up for booting firmware (which might load a kernel via fw_cfg) */ 1224 1225 if (have_dtb(info)) { 1226 /* 1227 * If we have a device tree blob, but no kernel to supply it to (or 1228 * the kernel is supposed to be loaded by the bootloader), copy the 1229 * DTB to the base of RAM for the bootloader to pick up. 1230 */ 1231 info->dtb_start = info->loader_start; 1232 } 1233 1234 if (info->kernel_filename) { 1235 FWCfgState *fw_cfg; 1236 bool try_decompressing_kernel; 1237 1238 fw_cfg = fw_cfg_find(); 1239 try_decompressing_kernel = arm_feature(&cpu->env, 1240 ARM_FEATURE_AARCH64); 1241 1242 /* 1243 * Expose the kernel, the command line, and the initrd in fw_cfg. 1244 * We don't process them here at all, it's all left to the 1245 * firmware. 1246 */ 1247 load_image_to_fw_cfg(fw_cfg, 1248 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1249 info->kernel_filename, 1250 try_decompressing_kernel); 1251 load_image_to_fw_cfg(fw_cfg, 1252 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1253 info->initrd_filename, false); 1254 1255 if (info->kernel_cmdline) { 1256 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1257 strlen(info->kernel_cmdline) + 1); 1258 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1259 info->kernel_cmdline); 1260 } 1261 } 1262 1263 /* 1264 * We will start from address 0 (typically a boot ROM image) in the 1265 * same way as hardware. Leave env->boot_info NULL, so that 1266 * do_cpu_reset() knows it does not need to alter the PC on reset. 1267 */ 1268 } 1269 1270 void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) 1271 { 1272 CPUState *cs; 1273 AddressSpace *as = arm_boot_address_space(cpu, info); 1274 1275 /* 1276 * CPU objects (unlike devices) are not automatically reset on system 1277 * reset, so we must always register a handler to do so. If we're 1278 * actually loading a kernel, the handler is also responsible for 1279 * arranging that we start it correctly. 1280 */ 1281 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1282 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1283 } 1284 1285 /* 1286 * The board code is not supposed to set secure_board_setup unless 1287 * running its code in secure mode is actually possible, and KVM 1288 * doesn't support secure. 1289 */ 1290 assert(!(info->secure_board_setup && kvm_enabled())); 1291 info->kernel_filename = ms->kernel_filename; 1292 info->kernel_cmdline = ms->kernel_cmdline; 1293 info->initrd_filename = ms->initrd_filename; 1294 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 1295 info->dtb_limit = 0; 1296 1297 /* Load the kernel. */ 1298 if (!info->kernel_filename || info->firmware_loaded) { 1299 arm_setup_firmware_boot(cpu, info); 1300 } else { 1301 arm_setup_direct_kernel_boot(cpu, info); 1302 } 1303 1304 if (!info->skip_dtb_autoload && have_dtb(info)) { 1305 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1306 exit(1); 1307 } 1308 } 1309 } 1310 1311 static const TypeInfo arm_linux_boot_if_info = { 1312 .name = TYPE_ARM_LINUX_BOOT_IF, 1313 .parent = TYPE_INTERFACE, 1314 .class_size = sizeof(ARMLinuxBootIfClass), 1315 }; 1316 1317 static void arm_linux_boot_register_types(void) 1318 { 1319 type_register_static(&arm_linux_boot_if_info); 1320 } 1321 1322 type_init(arm_linux_boot_register_types) 1323