1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/error-report.h" 12 #include "qapi/error.h" 13 #include <libfdt.h> 14 #include "hw/hw.h" 15 #include "hw/arm/arm.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "sysemu/kvm.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/numa.h" 20 #include "hw/boards.h" 21 #include "hw/loader.h" 22 #include "elf.h" 23 #include "sysemu/device_tree.h" 24 #include "qemu/config-file.h" 25 #include "qemu/option.h" 26 #include "exec/address-spaces.h" 27 #include "qemu/units.h" 28 29 /* Kernel boot protocol is specified in the kernel docs 30 * Documentation/arm/Booting and Documentation/arm64/booting.txt 31 * They have different preferred image load offsets from system RAM base. 32 */ 33 #define KERNEL_ARGS_ADDR 0x100 34 #define KERNEL_NOLOAD_ADDR 0x02000000 35 #define KERNEL_LOAD_ADDR 0x00010000 36 #define KERNEL64_LOAD_ADDR 0x00080000 37 38 #define ARM64_TEXT_OFFSET_OFFSET 8 39 #define ARM64_MAGIC_OFFSET 56 40 41 #define BOOTLOADER_MAX_SIZE (4 * KiB) 42 43 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 44 const struct arm_boot_info *info) 45 { 46 /* Return the address space to use for bootloader reads and writes. 47 * We prefer the secure address space if the CPU has it and we're 48 * going to boot the guest into it. 49 */ 50 int asidx; 51 CPUState *cs = CPU(cpu); 52 53 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 54 asidx = ARMASIdx_S; 55 } else { 56 asidx = ARMASIdx_NS; 57 } 58 59 return cpu_get_address_space(cs, asidx); 60 } 61 62 typedef enum { 63 FIXUP_NONE = 0, /* do nothing */ 64 FIXUP_TERMINATOR, /* end of insns */ 65 FIXUP_BOARDID, /* overwrite with board ID number */ 66 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 67 FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */ 68 FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */ 69 FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */ 70 FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */ 71 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 72 FIXUP_BOOTREG, /* overwrite with boot register address */ 73 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 74 FIXUP_MAX, 75 } FixupType; 76 77 typedef struct ARMInsnFixup { 78 uint32_t insn; 79 FixupType fixup; 80 } ARMInsnFixup; 81 82 static const ARMInsnFixup bootloader_aarch64[] = { 83 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 84 { 0xaa1f03e1 }, /* mov x1, xzr */ 85 { 0xaa1f03e2 }, /* mov x2, xzr */ 86 { 0xaa1f03e3 }, /* mov x3, xzr */ 87 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 88 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 89 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ 90 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ 91 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ 92 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ 93 { 0, FIXUP_TERMINATOR } 94 }; 95 96 /* A very small bootloader: call the board-setup code (if needed), 97 * set r0-r2, then jump to the kernel. 98 * If we're not calling boot setup code then we don't copy across 99 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 100 */ 101 102 static const ARMInsnFixup bootloader[] = { 103 { 0xe28fe004 }, /* add lr, pc, #4 */ 104 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 105 { 0, FIXUP_BOARD_SETUP }, 106 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 107 { 0xe3a00000 }, /* mov r0, #0 */ 108 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 109 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 110 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 111 { 0, FIXUP_BOARDID }, 112 { 0, FIXUP_ARGPTR_LO }, 113 { 0, FIXUP_ENTRYPOINT_LO }, 114 { 0, FIXUP_TERMINATOR } 115 }; 116 117 /* Handling for secondary CPU boot in a multicore system. 118 * Unlike the uniprocessor/primary CPU boot, this is platform 119 * dependent. The default code here is based on the secondary 120 * CPU boot protocol used on realview/vexpress boards, with 121 * some parameterisation to increase its flexibility. 122 * QEMU platform models for which this code is not appropriate 123 * should override write_secondary_boot and secondary_cpu_reset_hook 124 * instead. 125 * 126 * This code enables the interrupt controllers for the secondary 127 * CPUs and then puts all the secondary CPUs into a loop waiting 128 * for an interprocessor interrupt and polling a configurable 129 * location for the kernel secondary CPU entry point. 130 */ 131 #define DSB_INSN 0xf57ff04f 132 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 133 134 static const ARMInsnFixup smpboot[] = { 135 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 136 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 137 { 0xe3a01001 }, /* mov r1, #1 */ 138 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 139 { 0xe3a010ff }, /* mov r1, #0xff */ 140 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 141 { 0, FIXUP_DSB }, /* dsb */ 142 { 0xe320f003 }, /* wfi */ 143 { 0xe5901000 }, /* ldr r1, [r0] */ 144 { 0xe1110001 }, /* tst r1, r1 */ 145 { 0x0afffffb }, /* beq <wfi> */ 146 { 0xe12fff11 }, /* bx r1 */ 147 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 148 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 149 { 0, FIXUP_TERMINATOR } 150 }; 151 152 static void write_bootloader(const char *name, hwaddr addr, 153 const ARMInsnFixup *insns, uint32_t *fixupcontext, 154 AddressSpace *as) 155 { 156 /* Fix up the specified bootloader fragment and write it into 157 * guest memory using rom_add_blob_fixed(). fixupcontext is 158 * an array giving the values to write in for the fixup types 159 * which write a value into the code array. 160 */ 161 int i, len; 162 uint32_t *code; 163 164 len = 0; 165 while (insns[len].fixup != FIXUP_TERMINATOR) { 166 len++; 167 } 168 169 code = g_new0(uint32_t, len); 170 171 for (i = 0; i < len; i++) { 172 uint32_t insn = insns[i].insn; 173 FixupType fixup = insns[i].fixup; 174 175 switch (fixup) { 176 case FIXUP_NONE: 177 break; 178 case FIXUP_BOARDID: 179 case FIXUP_BOARD_SETUP: 180 case FIXUP_ARGPTR_LO: 181 case FIXUP_ARGPTR_HI: 182 case FIXUP_ENTRYPOINT_LO: 183 case FIXUP_ENTRYPOINT_HI: 184 case FIXUP_GIC_CPU_IF: 185 case FIXUP_BOOTREG: 186 case FIXUP_DSB: 187 insn = fixupcontext[fixup]; 188 break; 189 default: 190 abort(); 191 } 192 code[i] = tswap32(insn); 193 } 194 195 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 196 197 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 198 199 g_free(code); 200 } 201 202 static void default_write_secondary(ARMCPU *cpu, 203 const struct arm_boot_info *info) 204 { 205 uint32_t fixupcontext[FIXUP_MAX]; 206 AddressSpace *as = arm_boot_address_space(cpu, info); 207 208 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 209 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 210 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 211 fixupcontext[FIXUP_DSB] = DSB_INSN; 212 } else { 213 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 214 } 215 216 write_bootloader("smpboot", info->smp_loader_start, 217 smpboot, fixupcontext, as); 218 } 219 220 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 221 const struct arm_boot_info *info, 222 hwaddr mvbar_addr) 223 { 224 AddressSpace *as = arm_boot_address_space(cpu, info); 225 int n; 226 uint32_t mvbar_blob[] = { 227 /* mvbar_addr: secure monitor vectors 228 * Default unimplemented and unused vectors to spin. Makes it 229 * easier to debug (as opposed to the CPU running away). 230 */ 231 0xeafffffe, /* (spin) */ 232 0xeafffffe, /* (spin) */ 233 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 234 0xeafffffe, /* (spin) */ 235 0xeafffffe, /* (spin) */ 236 0xeafffffe, /* (spin) */ 237 0xeafffffe, /* (spin) */ 238 0xeafffffe, /* (spin) */ 239 }; 240 uint32_t board_setup_blob[] = { 241 /* board setup addr */ 242 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 243 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 244 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 245 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 246 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 247 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 248 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 249 0xe1a0f001, /* mov pc, r1 ;return */ 250 }; 251 252 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 253 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 254 255 /* check that these blobs don't overlap */ 256 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 257 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 258 259 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 260 mvbar_blob[n] = tswap32(mvbar_blob[n]); 261 } 262 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 263 mvbar_addr, as); 264 265 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 266 board_setup_blob[n] = tswap32(board_setup_blob[n]); 267 } 268 rom_add_blob_fixed_as("board-setup", board_setup_blob, 269 sizeof(board_setup_blob), info->board_setup_addr, as); 270 } 271 272 static void default_reset_secondary(ARMCPU *cpu, 273 const struct arm_boot_info *info) 274 { 275 AddressSpace *as = arm_boot_address_space(cpu, info); 276 CPUState *cs = CPU(cpu); 277 278 address_space_stl_notdirty(as, info->smp_bootreg_addr, 279 0, MEMTXATTRS_UNSPECIFIED, NULL); 280 cpu_set_pc(cs, info->smp_loader_start); 281 } 282 283 static inline bool have_dtb(const struct arm_boot_info *info) 284 { 285 return info->dtb_filename || info->get_dtb; 286 } 287 288 #define WRITE_WORD(p, value) do { \ 289 address_space_stl_notdirty(as, p, value, \ 290 MEMTXATTRS_UNSPECIFIED, NULL); \ 291 p += 4; \ 292 } while (0) 293 294 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 295 { 296 int initrd_size = info->initrd_size; 297 hwaddr base = info->loader_start; 298 hwaddr p; 299 300 p = base + KERNEL_ARGS_ADDR; 301 /* ATAG_CORE */ 302 WRITE_WORD(p, 5); 303 WRITE_WORD(p, 0x54410001); 304 WRITE_WORD(p, 1); 305 WRITE_WORD(p, 0x1000); 306 WRITE_WORD(p, 0); 307 /* ATAG_MEM */ 308 /* TODO: handle multiple chips on one ATAG list */ 309 WRITE_WORD(p, 4); 310 WRITE_WORD(p, 0x54410002); 311 WRITE_WORD(p, info->ram_size); 312 WRITE_WORD(p, info->loader_start); 313 if (initrd_size) { 314 /* ATAG_INITRD2 */ 315 WRITE_WORD(p, 4); 316 WRITE_WORD(p, 0x54420005); 317 WRITE_WORD(p, info->initrd_start); 318 WRITE_WORD(p, initrd_size); 319 } 320 if (info->kernel_cmdline && *info->kernel_cmdline) { 321 /* ATAG_CMDLINE */ 322 int cmdline_size; 323 324 cmdline_size = strlen(info->kernel_cmdline); 325 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 326 (const uint8_t *)info->kernel_cmdline, 327 cmdline_size + 1); 328 cmdline_size = (cmdline_size >> 2) + 1; 329 WRITE_WORD(p, cmdline_size + 2); 330 WRITE_WORD(p, 0x54410009); 331 p += cmdline_size * 4; 332 } 333 if (info->atag_board) { 334 /* ATAG_BOARD */ 335 int atag_board_len; 336 uint8_t atag_board_buf[0x1000]; 337 338 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 339 WRITE_WORD(p, (atag_board_len + 8) >> 2); 340 WRITE_WORD(p, 0x414f4d50); 341 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 342 atag_board_buf, atag_board_len); 343 p += atag_board_len; 344 } 345 /* ATAG_END */ 346 WRITE_WORD(p, 0); 347 WRITE_WORD(p, 0); 348 } 349 350 static void set_kernel_args_old(const struct arm_boot_info *info, 351 AddressSpace *as) 352 { 353 hwaddr p; 354 const char *s; 355 int initrd_size = info->initrd_size; 356 hwaddr base = info->loader_start; 357 358 /* see linux/include/asm-arm/setup.h */ 359 p = base + KERNEL_ARGS_ADDR; 360 /* page_size */ 361 WRITE_WORD(p, 4096); 362 /* nr_pages */ 363 WRITE_WORD(p, info->ram_size / 4096); 364 /* ramdisk_size */ 365 WRITE_WORD(p, 0); 366 #define FLAG_READONLY 1 367 #define FLAG_RDLOAD 4 368 #define FLAG_RDPROMPT 8 369 /* flags */ 370 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 371 /* rootdev */ 372 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 373 /* video_num_cols */ 374 WRITE_WORD(p, 0); 375 /* video_num_rows */ 376 WRITE_WORD(p, 0); 377 /* video_x */ 378 WRITE_WORD(p, 0); 379 /* video_y */ 380 WRITE_WORD(p, 0); 381 /* memc_control_reg */ 382 WRITE_WORD(p, 0); 383 /* unsigned char sounddefault */ 384 /* unsigned char adfsdrives */ 385 /* unsigned char bytes_per_char_h */ 386 /* unsigned char bytes_per_char_v */ 387 WRITE_WORD(p, 0); 388 /* pages_in_bank[4] */ 389 WRITE_WORD(p, 0); 390 WRITE_WORD(p, 0); 391 WRITE_WORD(p, 0); 392 WRITE_WORD(p, 0); 393 /* pages_in_vram */ 394 WRITE_WORD(p, 0); 395 /* initrd_start */ 396 if (initrd_size) { 397 WRITE_WORD(p, info->initrd_start); 398 } else { 399 WRITE_WORD(p, 0); 400 } 401 /* initrd_size */ 402 WRITE_WORD(p, initrd_size); 403 /* rd_start */ 404 WRITE_WORD(p, 0); 405 /* system_rev */ 406 WRITE_WORD(p, 0); 407 /* system_serial_low */ 408 WRITE_WORD(p, 0); 409 /* system_serial_high */ 410 WRITE_WORD(p, 0); 411 /* mem_fclk_21285 */ 412 WRITE_WORD(p, 0); 413 /* zero unused fields */ 414 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 415 WRITE_WORD(p, 0); 416 } 417 s = info->kernel_cmdline; 418 if (s) { 419 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 420 (const uint8_t *)s, strlen(s) + 1); 421 } else { 422 WRITE_WORD(p, 0); 423 } 424 } 425 426 static void fdt_add_psci_node(void *fdt) 427 { 428 uint32_t cpu_suspend_fn; 429 uint32_t cpu_off_fn; 430 uint32_t cpu_on_fn; 431 uint32_t migrate_fn; 432 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 433 const char *psci_method; 434 int64_t psci_conduit; 435 int rc; 436 437 psci_conduit = object_property_get_int(OBJECT(armcpu), 438 "psci-conduit", 439 &error_abort); 440 switch (psci_conduit) { 441 case QEMU_PSCI_CONDUIT_DISABLED: 442 return; 443 case QEMU_PSCI_CONDUIT_HVC: 444 psci_method = "hvc"; 445 break; 446 case QEMU_PSCI_CONDUIT_SMC: 447 psci_method = "smc"; 448 break; 449 default: 450 g_assert_not_reached(); 451 } 452 453 /* 454 * If /psci node is present in provided DTB, assume that no fixup 455 * is necessary and all PSCI configuration should be taken as-is 456 */ 457 rc = fdt_path_offset(fdt, "/psci"); 458 if (rc >= 0) { 459 return; 460 } 461 462 qemu_fdt_add_subnode(fdt, "/psci"); 463 if (armcpu->psci_version == 2) { 464 const char comp[] = "arm,psci-0.2\0arm,psci"; 465 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 466 467 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 468 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 469 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 470 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 471 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 472 } else { 473 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 474 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 475 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 476 } 477 } else { 478 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 479 480 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 481 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 482 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 483 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 484 } 485 486 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 487 * to the instruction that should be used to invoke PSCI functions. 488 * However, the device tree binding uses 'method' instead, so that is 489 * what we should use here. 490 */ 491 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 492 493 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 494 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 495 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 496 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 497 } 498 499 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 500 hwaddr addr_limit, AddressSpace *as) 501 { 502 void *fdt = NULL; 503 int size, rc, n = 0; 504 uint32_t acells, scells; 505 char *nodename; 506 unsigned int i; 507 hwaddr mem_base, mem_len; 508 char **node_path; 509 Error *err = NULL; 510 511 if (binfo->dtb_filename) { 512 char *filename; 513 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 514 if (!filename) { 515 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 516 goto fail; 517 } 518 519 fdt = load_device_tree(filename, &size); 520 if (!fdt) { 521 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 522 g_free(filename); 523 goto fail; 524 } 525 g_free(filename); 526 } else { 527 fdt = binfo->get_dtb(binfo, &size); 528 if (!fdt) { 529 fprintf(stderr, "Board was unable to create a dtb blob\n"); 530 goto fail; 531 } 532 } 533 534 if (addr_limit > addr && size > (addr_limit - addr)) { 535 /* Installing the device tree blob at addr would exceed addr_limit. 536 * Whether this constitutes failure is up to the caller to decide, 537 * so just return 0 as size, i.e., no error. 538 */ 539 g_free(fdt); 540 return 0; 541 } 542 543 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 544 NULL, &error_fatal); 545 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 546 NULL, &error_fatal); 547 if (acells == 0 || scells == 0) { 548 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 549 goto fail; 550 } 551 552 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { 553 /* This is user error so deserves a friendlier error message 554 * than the failure of setprop_sized_cells would provide 555 */ 556 fprintf(stderr, "qemu: dtb file not compatible with " 557 "RAM size > 4GB\n"); 558 goto fail; 559 } 560 561 /* nop all root nodes matching /memory or /memory@unit-address */ 562 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 563 if (err) { 564 error_report_err(err); 565 goto fail; 566 } 567 while (node_path[n]) { 568 if (g_str_has_prefix(node_path[n], "/memory")) { 569 qemu_fdt_nop_node(fdt, node_path[n]); 570 } 571 n++; 572 } 573 g_strfreev(node_path); 574 575 if (nb_numa_nodes > 0) { 576 mem_base = binfo->loader_start; 577 for (i = 0; i < nb_numa_nodes; i++) { 578 mem_len = numa_info[i].node_mem; 579 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 580 qemu_fdt_add_subnode(fdt, nodename); 581 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 582 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 583 acells, mem_base, 584 scells, mem_len); 585 if (rc < 0) { 586 fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename, 587 i); 588 goto fail; 589 } 590 591 qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i); 592 mem_base += mem_len; 593 g_free(nodename); 594 } 595 } else { 596 nodename = g_strdup_printf("/memory@%" PRIx64, binfo->loader_start); 597 qemu_fdt_add_subnode(fdt, nodename); 598 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 599 600 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 601 acells, binfo->loader_start, 602 scells, binfo->ram_size); 603 if (rc < 0) { 604 fprintf(stderr, "couldn't set %s reg\n", nodename); 605 goto fail; 606 } 607 g_free(nodename); 608 } 609 610 rc = fdt_path_offset(fdt, "/chosen"); 611 if (rc < 0) { 612 qemu_fdt_add_subnode(fdt, "/chosen"); 613 } 614 615 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { 616 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 617 binfo->kernel_cmdline); 618 if (rc < 0) { 619 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 620 goto fail; 621 } 622 } 623 624 if (binfo->initrd_size) { 625 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 626 binfo->initrd_start); 627 if (rc < 0) { 628 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 629 goto fail; 630 } 631 632 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 633 binfo->initrd_start + binfo->initrd_size); 634 if (rc < 0) { 635 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 636 goto fail; 637 } 638 } 639 640 fdt_add_psci_node(fdt); 641 642 if (binfo->modify_dtb) { 643 binfo->modify_dtb(binfo, fdt); 644 } 645 646 qemu_fdt_dumpdtb(fdt, size); 647 648 /* Put the DTB into the memory map as a ROM image: this will ensure 649 * the DTB is copied again upon reset, even if addr points into RAM. 650 */ 651 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 652 653 g_free(fdt); 654 655 return size; 656 657 fail: 658 g_free(fdt); 659 return -1; 660 } 661 662 static void do_cpu_reset(void *opaque) 663 { 664 ARMCPU *cpu = opaque; 665 CPUState *cs = CPU(cpu); 666 CPUARMState *env = &cpu->env; 667 const struct arm_boot_info *info = env->boot_info; 668 669 cpu_reset(cs); 670 if (info) { 671 if (!info->is_linux) { 672 int i; 673 /* Jump to the entry point. */ 674 uint64_t entry = info->entry; 675 676 switch (info->endianness) { 677 case ARM_ENDIANNESS_LE: 678 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 679 for (i = 1; i < 4; ++i) { 680 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 681 } 682 env->uncached_cpsr &= ~CPSR_E; 683 break; 684 case ARM_ENDIANNESS_BE8: 685 env->cp15.sctlr_el[1] |= SCTLR_E0E; 686 for (i = 1; i < 4; ++i) { 687 env->cp15.sctlr_el[i] |= SCTLR_EE; 688 } 689 env->uncached_cpsr |= CPSR_E; 690 break; 691 case ARM_ENDIANNESS_BE32: 692 env->cp15.sctlr_el[1] |= SCTLR_B; 693 break; 694 case ARM_ENDIANNESS_UNKNOWN: 695 break; /* Board's decision */ 696 default: 697 g_assert_not_reached(); 698 } 699 700 cpu_set_pc(cs, entry); 701 } else { 702 /* If we are booting Linux then we need to check whether we are 703 * booting into secure or non-secure state and adjust the state 704 * accordingly. Out of reset, ARM is defined to be in secure state 705 * (SCR.NS = 0), we change that here if non-secure boot has been 706 * requested. 707 */ 708 if (arm_feature(env, ARM_FEATURE_EL3)) { 709 /* AArch64 is defined to come out of reset into EL3 if enabled. 710 * If we are booting Linux then we need to adjust our EL as 711 * Linux expects us to be in EL2 or EL1. AArch32 resets into 712 * SVC, which Linux expects, so no privilege/exception level to 713 * adjust. 714 */ 715 if (env->aarch64) { 716 env->cp15.scr_el3 |= SCR_RW; 717 if (arm_feature(env, ARM_FEATURE_EL2)) { 718 env->cp15.hcr_el2 |= HCR_RW; 719 env->pstate = PSTATE_MODE_EL2h; 720 } else { 721 env->pstate = PSTATE_MODE_EL1h; 722 } 723 /* AArch64 kernels never boot in secure mode */ 724 assert(!info->secure_boot); 725 /* This hook is only supported for AArch32 currently: 726 * bootloader_aarch64[] will not call the hook, and 727 * the code above has already dropped us into EL2 or EL1. 728 */ 729 assert(!info->secure_board_setup); 730 } 731 732 if (arm_feature(env, ARM_FEATURE_EL2)) { 733 /* If we have EL2 then Linux expects the HVC insn to work */ 734 env->cp15.scr_el3 |= SCR_HCE; 735 } 736 737 /* Set to non-secure if not a secure boot */ 738 if (!info->secure_boot && 739 (cs != first_cpu || !info->secure_board_setup)) { 740 /* Linux expects non-secure state */ 741 env->cp15.scr_el3 |= SCR_NS; 742 } 743 } 744 745 if (!env->aarch64 && !info->secure_boot && 746 arm_feature(env, ARM_FEATURE_EL2)) { 747 /* 748 * This is an AArch32 boot not to Secure state, and 749 * we have Hyp mode available, so boot the kernel into 750 * Hyp mode. This is not how the CPU comes out of reset, 751 * so we need to manually put it there. 752 */ 753 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw); 754 } 755 756 if (cs == first_cpu) { 757 AddressSpace *as = arm_boot_address_space(cpu, info); 758 759 cpu_set_pc(cs, info->loader_start); 760 761 if (!have_dtb(info)) { 762 if (old_param) { 763 set_kernel_args_old(info, as); 764 } else { 765 set_kernel_args(info, as); 766 } 767 } 768 } else { 769 info->secondary_cpu_reset_hook(cpu, info); 770 } 771 } 772 } 773 } 774 775 /** 776 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 777 * by key. 778 * @fw_cfg: The firmware config instance to store the data in. 779 * @size_key: The firmware config key to store the size of the loaded 780 * data under, with fw_cfg_add_i32(). 781 * @data_key: The firmware config key to store the loaded data under, 782 * with fw_cfg_add_bytes(). 783 * @image_name: The name of the image file to load. If it is NULL, the 784 * function returns without doing anything. 785 * @try_decompress: Whether the image should be decompressed (gunzipped) before 786 * adding it to fw_cfg. If decompression fails, the image is 787 * loaded as-is. 788 * 789 * In case of failure, the function prints an error message to stderr and the 790 * process exits with status 1. 791 */ 792 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 793 uint16_t data_key, const char *image_name, 794 bool try_decompress) 795 { 796 size_t size = -1; 797 uint8_t *data; 798 799 if (image_name == NULL) { 800 return; 801 } 802 803 if (try_decompress) { 804 size = load_image_gzipped_buffer(image_name, 805 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 806 } 807 808 if (size == (size_t)-1) { 809 gchar *contents; 810 gsize length; 811 812 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 813 error_report("failed to load \"%s\"", image_name); 814 exit(1); 815 } 816 size = length; 817 data = (uint8_t *)contents; 818 } 819 820 fw_cfg_add_i32(fw_cfg, size_key, size); 821 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 822 } 823 824 static int do_arm_linux_init(Object *obj, void *opaque) 825 { 826 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 827 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 828 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 829 struct arm_boot_info *info = opaque; 830 831 if (albifc->arm_linux_init) { 832 albifc->arm_linux_init(albif, info->secure_boot); 833 } 834 } 835 return 0; 836 } 837 838 static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 839 uint64_t *lowaddr, uint64_t *highaddr, 840 int elf_machine, AddressSpace *as) 841 { 842 bool elf_is64; 843 union { 844 Elf32_Ehdr h32; 845 Elf64_Ehdr h64; 846 } elf_header; 847 int data_swab = 0; 848 bool big_endian; 849 int64_t ret = -1; 850 Error *err = NULL; 851 852 853 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 854 if (err) { 855 error_free(err); 856 return ret; 857 } 858 859 if (elf_is64) { 860 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 861 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 862 : ARM_ENDIANNESS_LE; 863 } else { 864 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 865 if (big_endian) { 866 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 867 info->endianness = ARM_ENDIANNESS_BE8; 868 } else { 869 info->endianness = ARM_ENDIANNESS_BE32; 870 /* In BE32, the CPU has a different view of the per-byte 871 * address map than the rest of the system. BE32 ELF files 872 * are organised such that they can be programmed through 873 * the CPU's per-word byte-reversed view of the world. QEMU 874 * however loads ELF files independently of the CPU. So 875 * tell the ELF loader to byte reverse the data for us. 876 */ 877 data_swab = 2; 878 } 879 } else { 880 info->endianness = ARM_ENDIANNESS_LE; 881 } 882 } 883 884 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL, 885 pentry, lowaddr, highaddr, big_endian, elf_machine, 886 1, data_swab, as); 887 if (ret <= 0) { 888 /* The header loaded but the image didn't */ 889 exit(1); 890 } 891 892 return ret; 893 } 894 895 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 896 hwaddr *entry, AddressSpace *as) 897 { 898 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 899 uint8_t *buffer; 900 int size; 901 902 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 903 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 904 &buffer); 905 906 if (size < 0) { 907 gsize len; 908 909 /* Load as raw file otherwise */ 910 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 911 return -1; 912 } 913 size = len; 914 } 915 916 /* check the arm64 magic header value -- very old kernels may not have it */ 917 if (size > ARM64_MAGIC_OFFSET + 4 && 918 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 919 uint64_t hdrvals[2]; 920 921 /* The arm64 Image header has text_offset and image_size fields at 8 and 922 * 16 bytes into the Image header, respectively. The text_offset field 923 * is only valid if the image_size is non-zero. 924 */ 925 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 926 if (hdrvals[1] != 0) { 927 kernel_load_offset = le64_to_cpu(hdrvals[0]); 928 929 /* 930 * We write our startup "bootloader" at the very bottom of RAM, 931 * so that bit can't be used for the image. Luckily the Image 932 * format specification is that the image requests only an offset 933 * from a 2MB boundary, not an absolute load address. So if the 934 * image requests an offset that might mean it overlaps with the 935 * bootloader, we can just load it starting at 2MB+offset rather 936 * than 0MB + offset. 937 */ 938 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 939 kernel_load_offset += 2 * MiB; 940 } 941 } 942 } 943 944 *entry = mem_base + kernel_load_offset; 945 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 946 947 g_free(buffer); 948 949 return size; 950 } 951 952 static void arm_setup_direct_kernel_boot(ARMCPU *cpu, 953 struct arm_boot_info *info) 954 { 955 /* Set up for a direct boot of a kernel image file. */ 956 CPUState *cs; 957 AddressSpace *as = arm_boot_address_space(cpu, info); 958 int kernel_size; 959 int initrd_size; 960 int is_linux = 0; 961 uint64_t elf_entry, elf_low_addr, elf_high_addr; 962 int elf_machine; 963 hwaddr entry; 964 static const ARMInsnFixup *primary_loader; 965 966 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 967 primary_loader = bootloader_aarch64; 968 elf_machine = EM_AARCH64; 969 } else { 970 primary_loader = bootloader; 971 if (!info->write_board_setup) { 972 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 973 } 974 elf_machine = EM_ARM; 975 } 976 977 if (!info->secondary_cpu_reset_hook) { 978 info->secondary_cpu_reset_hook = default_reset_secondary; 979 } 980 if (!info->write_secondary_boot) { 981 info->write_secondary_boot = default_write_secondary; 982 } 983 984 if (info->nb_cpus == 0) 985 info->nb_cpus = 1; 986 987 /* 988 * We want to put the initrd far enough into RAM that when the 989 * kernel is uncompressed it will not clobber the initrd. However 990 * on boards without much RAM we must ensure that we still leave 991 * enough room for a decent sized initrd, and on boards with large 992 * amounts of RAM we must avoid the initrd being so far up in RAM 993 * that it is outside lowmem and inaccessible to the kernel. 994 * So for boards with less than 256MB of RAM we put the initrd 995 * halfway into RAM, and for boards with 256MB of RAM or more we put 996 * the initrd at 128MB. 997 */ 998 info->initrd_start = info->loader_start + 999 MIN(info->ram_size / 2, 128 * 1024 * 1024); 1000 1001 /* Assume that raw images are linux kernels, and ELF images are not. */ 1002 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, 1003 &elf_high_addr, elf_machine, as); 1004 if (kernel_size > 0 && have_dtb(info)) { 1005 /* 1006 * If there is still some room left at the base of RAM, try and put 1007 * the DTB there like we do for images loaded with -bios or -pflash. 1008 */ 1009 if (elf_low_addr > info->loader_start 1010 || elf_high_addr < info->loader_start) { 1011 /* 1012 * Set elf_low_addr as address limit for arm_load_dtb if it may be 1013 * pointing into RAM, otherwise pass '0' (no limit) 1014 */ 1015 if (elf_low_addr < info->loader_start) { 1016 elf_low_addr = 0; 1017 } 1018 info->dtb_start = info->loader_start; 1019 info->dtb_limit = elf_low_addr; 1020 } 1021 } 1022 entry = elf_entry; 1023 if (kernel_size < 0) { 1024 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; 1025 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, 1026 &is_linux, NULL, NULL, as); 1027 } 1028 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1029 kernel_size = load_aarch64_image(info->kernel_filename, 1030 info->loader_start, &entry, as); 1031 is_linux = 1; 1032 } else if (kernel_size < 0) { 1033 /* 32-bit ARM */ 1034 entry = info->loader_start + KERNEL_LOAD_ADDR; 1035 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1036 info->ram_size - KERNEL_LOAD_ADDR, 1037 as); 1038 is_linux = 1; 1039 } 1040 if (kernel_size < 0) { 1041 error_report("could not load kernel '%s'", info->kernel_filename); 1042 exit(1); 1043 } 1044 info->entry = entry; 1045 if (is_linux) { 1046 uint32_t fixupcontext[FIXUP_MAX]; 1047 1048 if (info->initrd_filename) { 1049 initrd_size = load_ramdisk_as(info->initrd_filename, 1050 info->initrd_start, 1051 info->ram_size - info->initrd_start, 1052 as); 1053 if (initrd_size < 0) { 1054 initrd_size = load_image_targphys_as(info->initrd_filename, 1055 info->initrd_start, 1056 info->ram_size - 1057 info->initrd_start, 1058 as); 1059 } 1060 if (initrd_size < 0) { 1061 error_report("could not load initrd '%s'", 1062 info->initrd_filename); 1063 exit(1); 1064 } 1065 } else { 1066 initrd_size = 0; 1067 } 1068 info->initrd_size = initrd_size; 1069 1070 fixupcontext[FIXUP_BOARDID] = info->board_id; 1071 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1072 1073 /* 1074 * for device tree boot, we pass the DTB directly in r2. Otherwise 1075 * we point to the kernel args. 1076 */ 1077 if (have_dtb(info)) { 1078 hwaddr align; 1079 1080 if (elf_machine == EM_AARCH64) { 1081 /* 1082 * Some AArch64 kernels on early bootup map the fdt region as 1083 * 1084 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1085 * 1086 * Let's play safe and prealign it to 2MB to give us some space. 1087 */ 1088 align = 2 * 1024 * 1024; 1089 } else { 1090 /* 1091 * Some 32bit kernels will trash anything in the 4K page the 1092 * initrd ends in, so make sure the DTB isn't caught up in that. 1093 */ 1094 align = 4096; 1095 } 1096 1097 /* Place the DTB after the initrd in memory with alignment. */ 1098 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1099 align); 1100 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; 1101 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; 1102 } else { 1103 fixupcontext[FIXUP_ARGPTR_LO] = 1104 info->loader_start + KERNEL_ARGS_ADDR; 1105 fixupcontext[FIXUP_ARGPTR_HI] = 1106 (info->loader_start + KERNEL_ARGS_ADDR) >> 32; 1107 if (info->ram_size >= (1ULL << 32)) { 1108 error_report("RAM size must be less than 4GB to boot" 1109 " Linux kernel using ATAGS (try passing a device tree" 1110 " using -dtb)"); 1111 exit(1); 1112 } 1113 } 1114 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; 1115 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; 1116 1117 write_bootloader("bootloader", info->loader_start, 1118 primary_loader, fixupcontext, as); 1119 1120 if (info->nb_cpus > 1) { 1121 info->write_secondary_boot(cpu, info); 1122 } 1123 if (info->write_board_setup) { 1124 info->write_board_setup(cpu, info); 1125 } 1126 1127 /* 1128 * Notify devices which need to fake up firmware initialization 1129 * that we're doing a direct kernel boot. 1130 */ 1131 object_child_foreach_recursive(object_get_root(), 1132 do_arm_linux_init, info); 1133 } 1134 info->is_linux = is_linux; 1135 1136 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1137 ARM_CPU(cs)->env.boot_info = info; 1138 } 1139 } 1140 1141 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) 1142 { 1143 /* Set up for booting firmware (which might load a kernel via fw_cfg) */ 1144 1145 if (have_dtb(info)) { 1146 /* 1147 * If we have a device tree blob, but no kernel to supply it to (or 1148 * the kernel is supposed to be loaded by the bootloader), copy the 1149 * DTB to the base of RAM for the bootloader to pick up. 1150 */ 1151 info->dtb_start = info->loader_start; 1152 } 1153 1154 if (info->kernel_filename) { 1155 FWCfgState *fw_cfg; 1156 bool try_decompressing_kernel; 1157 1158 fw_cfg = fw_cfg_find(); 1159 try_decompressing_kernel = arm_feature(&cpu->env, 1160 ARM_FEATURE_AARCH64); 1161 1162 /* 1163 * Expose the kernel, the command line, and the initrd in fw_cfg. 1164 * We don't process them here at all, it's all left to the 1165 * firmware. 1166 */ 1167 load_image_to_fw_cfg(fw_cfg, 1168 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1169 info->kernel_filename, 1170 try_decompressing_kernel); 1171 load_image_to_fw_cfg(fw_cfg, 1172 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1173 info->initrd_filename, false); 1174 1175 if (info->kernel_cmdline) { 1176 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1177 strlen(info->kernel_cmdline) + 1); 1178 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1179 info->kernel_cmdline); 1180 } 1181 } 1182 1183 /* 1184 * We will start from address 0 (typically a boot ROM image) in the 1185 * same way as hardware. Leave env->boot_info NULL, so that 1186 * do_cpu_reset() knows it does not need to alter the PC on reset. 1187 */ 1188 } 1189 1190 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 1191 { 1192 CPUState *cs; 1193 AddressSpace *as = arm_boot_address_space(cpu, info); 1194 1195 /* 1196 * CPU objects (unlike devices) are not automatically reset on system 1197 * reset, so we must always register a handler to do so. If we're 1198 * actually loading a kernel, the handler is also responsible for 1199 * arranging that we start it correctly. 1200 */ 1201 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1202 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1203 } 1204 1205 /* 1206 * The board code is not supposed to set secure_board_setup unless 1207 * running its code in secure mode is actually possible, and KVM 1208 * doesn't support secure. 1209 */ 1210 assert(!(info->secure_board_setup && kvm_enabled())); 1211 1212 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 1213 info->dtb_limit = 0; 1214 1215 /* Load the kernel. */ 1216 if (!info->kernel_filename || info->firmware_loaded) { 1217 arm_setup_firmware_boot(cpu, info); 1218 } else { 1219 arm_setup_direct_kernel_boot(cpu, info); 1220 } 1221 1222 if (!info->skip_dtb_autoload && have_dtb(info)) { 1223 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { 1224 exit(1); 1225 } 1226 } 1227 } 1228 1229 static const TypeInfo arm_linux_boot_if_info = { 1230 .name = TYPE_ARM_LINUX_BOOT_IF, 1231 .parent = TYPE_INTERFACE, 1232 .class_size = sizeof(ARMLinuxBootIfClass), 1233 }; 1234 1235 static void arm_linux_boot_register_types(void) 1236 { 1237 type_register_static(&arm_linux_boot_if_info); 1238 } 1239 1240 type_init(arm_linux_boot_register_types) 1241