1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu-common.h" 12 #include "qemu/error-report.h" 13 #include "qapi/error.h" 14 #include <libfdt.h> 15 #include "hw/hw.h" 16 #include "hw/arm/boot.h" 17 #include "hw/arm/linux-boot-if.h" 18 #include "sysemu/kvm.h" 19 #include "sysemu/sysemu.h" 20 #include "sysemu/numa.h" 21 #include "sysemu/reset.h" 22 #include "hw/boards.h" 23 #include "hw/loader.h" 24 #include "elf.h" 25 #include "sysemu/device_tree.h" 26 #include "qemu/config-file.h" 27 #include "qemu/option.h" 28 #include "exec/address-spaces.h" 29 #include "qemu/units.h" 30 31 /* Kernel boot protocol is specified in the kernel docs 32 * Documentation/arm/Booting and Documentation/arm64/booting.txt 33 * They have different preferred image load offsets from system RAM base. 34 */ 35 #define KERNEL_ARGS_ADDR 0x100 36 #define KERNEL_NOLOAD_ADDR 0x02000000 37 #define KERNEL_LOAD_ADDR 0x00010000 38 #define KERNEL64_LOAD_ADDR 0x00080000 39 40 #define ARM64_TEXT_OFFSET_OFFSET 8 41 #define ARM64_MAGIC_OFFSET 56 42 43 #define BOOTLOADER_MAX_SIZE (4 * KiB) 44 45 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 46 const struct arm_boot_info *info) 47 { 48 /* Return the address space to use for bootloader reads and writes. 49 * We prefer the secure address space if the CPU has it and we're 50 * going to boot the guest into it. 51 */ 52 int asidx; 53 CPUState *cs = CPU(cpu); 54 55 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 56 asidx = ARMASIdx_S; 57 } else { 58 asidx = ARMASIdx_NS; 59 } 60 61 return cpu_get_address_space(cs, asidx); 62 } 63 64 typedef enum { 65 FIXUP_NONE = 0, /* do nothing */ 66 FIXUP_TERMINATOR, /* end of insns */ 67 FIXUP_BOARDID, /* overwrite with board ID number */ 68 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 69 FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */ 70 FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */ 71 FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */ 72 FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */ 73 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 74 FIXUP_BOOTREG, /* overwrite with boot register address */ 75 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 76 FIXUP_MAX, 77 } FixupType; 78 79 typedef struct ARMInsnFixup { 80 uint32_t insn; 81 FixupType fixup; 82 } ARMInsnFixup; 83 84 static const ARMInsnFixup bootloader_aarch64[] = { 85 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 86 { 0xaa1f03e1 }, /* mov x1, xzr */ 87 { 0xaa1f03e2 }, /* mov x2, xzr */ 88 { 0xaa1f03e3 }, /* mov x3, xzr */ 89 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 90 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 91 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ 92 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ 93 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ 94 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ 95 { 0, FIXUP_TERMINATOR } 96 }; 97 98 /* A very small bootloader: call the board-setup code (if needed), 99 * set r0-r2, then jump to the kernel. 100 * If we're not calling boot setup code then we don't copy across 101 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 102 */ 103 104 static const ARMInsnFixup bootloader[] = { 105 { 0xe28fe004 }, /* add lr, pc, #4 */ 106 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 107 { 0, FIXUP_BOARD_SETUP }, 108 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 109 { 0xe3a00000 }, /* mov r0, #0 */ 110 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 111 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 112 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 113 { 0, FIXUP_BOARDID }, 114 { 0, FIXUP_ARGPTR_LO }, 115 { 0, FIXUP_ENTRYPOINT_LO }, 116 { 0, FIXUP_TERMINATOR } 117 }; 118 119 /* Handling for secondary CPU boot in a multicore system. 120 * Unlike the uniprocessor/primary CPU boot, this is platform 121 * dependent. The default code here is based on the secondary 122 * CPU boot protocol used on realview/vexpress boards, with 123 * some parameterisation to increase its flexibility. 124 * QEMU platform models for which this code is not appropriate 125 * should override write_secondary_boot and secondary_cpu_reset_hook 126 * instead. 127 * 128 * This code enables the interrupt controllers for the secondary 129 * CPUs and then puts all the secondary CPUs into a loop waiting 130 * for an interprocessor interrupt and polling a configurable 131 * location for the kernel secondary CPU entry point. 132 */ 133 #define DSB_INSN 0xf57ff04f 134 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 135 136 static const ARMInsnFixup smpboot[] = { 137 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 138 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 139 { 0xe3a01001 }, /* mov r1, #1 */ 140 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 141 { 0xe3a010ff }, /* mov r1, #0xff */ 142 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 143 { 0, FIXUP_DSB }, /* dsb */ 144 { 0xe320f003 }, /* wfi */ 145 { 0xe5901000 }, /* ldr r1, [r0] */ 146 { 0xe1110001 }, /* tst r1, r1 */ 147 { 0x0afffffb }, /* beq <wfi> */ 148 { 0xe12fff11 }, /* bx r1 */ 149 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 150 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 151 { 0, FIXUP_TERMINATOR } 152 }; 153 154 static void write_bootloader(const char *name, hwaddr addr, 155 const ARMInsnFixup *insns, uint32_t *fixupcontext, 156 AddressSpace *as) 157 { 158 /* Fix up the specified bootloader fragment and write it into 159 * guest memory using rom_add_blob_fixed(). fixupcontext is 160 * an array giving the values to write in for the fixup types 161 * which write a value into the code array. 162 */ 163 int i, len; 164 uint32_t *code; 165 166 len = 0; 167 while (insns[len].fixup != FIXUP_TERMINATOR) { 168 len++; 169 } 170 171 code = g_new0(uint32_t, len); 172 173 for (i = 0; i < len; i++) { 174 uint32_t insn = insns[i].insn; 175 FixupType fixup = insns[i].fixup; 176 177 switch (fixup) { 178 case FIXUP_NONE: 179 break; 180 case FIXUP_BOARDID: 181 case FIXUP_BOARD_SETUP: 182 case FIXUP_ARGPTR_LO: 183 case FIXUP_ARGPTR_HI: 184 case FIXUP_ENTRYPOINT_LO: 185 case FIXUP_ENTRYPOINT_HI: 186 case FIXUP_GIC_CPU_IF: 187 case FIXUP_BOOTREG: 188 case FIXUP_DSB: 189 insn = fixupcontext[fixup]; 190 break; 191 default: 192 abort(); 193 } 194 code[i] = tswap32(insn); 195 } 196 197 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 198 199 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 200 201 g_free(code); 202 } 203 204 static void default_write_secondary(ARMCPU *cpu, 205 const struct arm_boot_info *info) 206 { 207 uint32_t fixupcontext[FIXUP_MAX]; 208 AddressSpace *as = arm_boot_address_space(cpu, info); 209 210 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 211 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 212 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 213 fixupcontext[FIXUP_DSB] = DSB_INSN; 214 } else { 215 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 216 } 217 218 write_bootloader("smpboot", info->smp_loader_start, 219 smpboot, fixupcontext, as); 220 } 221 222 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 223 const struct arm_boot_info *info, 224 hwaddr mvbar_addr) 225 { 226 AddressSpace *as = arm_boot_address_space(cpu, info); 227 int n; 228 uint32_t mvbar_blob[] = { 229 /* mvbar_addr: secure monitor vectors 230 * Default unimplemented and unused vectors to spin. Makes it 231 * easier to debug (as opposed to the CPU running away). 232 */ 233 0xeafffffe, /* (spin) */ 234 0xeafffffe, /* (spin) */ 235 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 236 0xeafffffe, /* (spin) */ 237 0xeafffffe, /* (spin) */ 238 0xeafffffe, /* (spin) */ 239 0xeafffffe, /* (spin) */ 240 0xeafffffe, /* (spin) */ 241 }; 242 uint32_t board_setup_blob[] = { 243 /* board setup addr */ 244 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 245 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 246 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 247 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 248 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 249 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 250 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 251 0xe1a0f001, /* mov pc, r1 ;return */ 252 }; 253 254 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 255 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 256 257 /* check that these blobs don't overlap */ 258 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 259 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 260 261 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 262 mvbar_blob[n] = tswap32(mvbar_blob[n]); 263 } 264 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 265 mvbar_addr, as); 266 267 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 268 board_setup_blob[n] = tswap32(board_setup_blob[n]); 269 } 270 rom_add_blob_fixed_as("board-setup", board_setup_blob, 271 sizeof(board_setup_blob), info->board_setup_addr, as); 272 } 273 274 static void default_reset_secondary(ARMCPU *cpu, 275 const struct arm_boot_info *info) 276 { 277 AddressSpace *as = arm_boot_address_space(cpu, info); 278 CPUState *cs = CPU(cpu); 279 280 address_space_stl_notdirty(as, info->smp_bootreg_addr, 281 0, MEMTXATTRS_UNSPECIFIED, NULL); 282 cpu_set_pc(cs, info->smp_loader_start); 283 } 284 285 static inline bool have_dtb(const struct arm_boot_info *info) 286 { 287 return info->dtb_filename || info->get_dtb; 288 } 289 290 #define WRITE_WORD(p, value) do { \ 291 address_space_stl_notdirty(as, p, value, \ 292 MEMTXATTRS_UNSPECIFIED, NULL); \ 293 p += 4; \ 294 } while (0) 295 296 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 297 { 298 int initrd_size = info->initrd_size; 299 hwaddr base = info->loader_start; 300 hwaddr p; 301 302 p = base + KERNEL_ARGS_ADDR; 303 /* ATAG_CORE */ 304 WRITE_WORD(p, 5); 305 WRITE_WORD(p, 0x54410001); 306 WRITE_WORD(p, 1); 307 WRITE_WORD(p, 0x1000); 308 WRITE_WORD(p, 0); 309 /* ATAG_MEM */ 310 /* TODO: handle multiple chips on one ATAG list */ 311 WRITE_WORD(p, 4); 312 WRITE_WORD(p, 0x54410002); 313 WRITE_WORD(p, info->ram_size); 314 WRITE_WORD(p, info->loader_start); 315 if (initrd_size) { 316 /* ATAG_INITRD2 */ 317 WRITE_WORD(p, 4); 318 WRITE_WORD(p, 0x54420005); 319 WRITE_WORD(p, info->initrd_start); 320 WRITE_WORD(p, initrd_size); 321 } 322 if (info->kernel_cmdline && *info->kernel_cmdline) { 323 /* ATAG_CMDLINE */ 324 int cmdline_size; 325 326 cmdline_size = strlen(info->kernel_cmdline); 327 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 328 (const uint8_t *)info->kernel_cmdline, 329 cmdline_size + 1); 330 cmdline_size = (cmdline_size >> 2) + 1; 331 WRITE_WORD(p, cmdline_size + 2); 332 WRITE_WORD(p, 0x54410009); 333 p += cmdline_size * 4; 334 } 335 if (info->atag_board) { 336 /* ATAG_BOARD */ 337 int atag_board_len; 338 uint8_t atag_board_buf[0x1000]; 339 340 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 341 WRITE_WORD(p, (atag_board_len + 8) >> 2); 342 WRITE_WORD(p, 0x414f4d50); 343 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 344 atag_board_buf, atag_board_len); 345 p += atag_board_len; 346 } 347 /* ATAG_END */ 348 WRITE_WORD(p, 0); 349 WRITE_WORD(p, 0); 350 } 351 352 static void set_kernel_args_old(const struct arm_boot_info *info, 353 AddressSpace *as) 354 { 355 hwaddr p; 356 const char *s; 357 int initrd_size = info->initrd_size; 358 hwaddr base = info->loader_start; 359 360 /* see linux/include/asm-arm/setup.h */ 361 p = base + KERNEL_ARGS_ADDR; 362 /* page_size */ 363 WRITE_WORD(p, 4096); 364 /* nr_pages */ 365 WRITE_WORD(p, info->ram_size / 4096); 366 /* ramdisk_size */ 367 WRITE_WORD(p, 0); 368 #define FLAG_READONLY 1 369 #define FLAG_RDLOAD 4 370 #define FLAG_RDPROMPT 8 371 /* flags */ 372 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 373 /* rootdev */ 374 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 375 /* video_num_cols */ 376 WRITE_WORD(p, 0); 377 /* video_num_rows */ 378 WRITE_WORD(p, 0); 379 /* video_x */ 380 WRITE_WORD(p, 0); 381 /* video_y */ 382 WRITE_WORD(p, 0); 383 /* memc_control_reg */ 384 WRITE_WORD(p, 0); 385 /* unsigned char sounddefault */ 386 /* unsigned char adfsdrives */ 387 /* unsigned char bytes_per_char_h */ 388 /* unsigned char bytes_per_char_v */ 389 WRITE_WORD(p, 0); 390 /* pages_in_bank[4] */ 391 WRITE_WORD(p, 0); 392 WRITE_WORD(p, 0); 393 WRITE_WORD(p, 0); 394 WRITE_WORD(p, 0); 395 /* pages_in_vram */ 396 WRITE_WORD(p, 0); 397 /* initrd_start */ 398 if (initrd_size) { 399 WRITE_WORD(p, info->initrd_start); 400 } else { 401 WRITE_WORD(p, 0); 402 } 403 /* initrd_size */ 404 WRITE_WORD(p, initrd_size); 405 /* rd_start */ 406 WRITE_WORD(p, 0); 407 /* system_rev */ 408 WRITE_WORD(p, 0); 409 /* system_serial_low */ 410 WRITE_WORD(p, 0); 411 /* system_serial_high */ 412 WRITE_WORD(p, 0); 413 /* mem_fclk_21285 */ 414 WRITE_WORD(p, 0); 415 /* zero unused fields */ 416 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 417 WRITE_WORD(p, 0); 418 } 419 s = info->kernel_cmdline; 420 if (s) { 421 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 422 (const uint8_t *)s, strlen(s) + 1); 423 } else { 424 WRITE_WORD(p, 0); 425 } 426 } 427 428 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, 429 uint32_t scells, hwaddr mem_len, 430 int numa_node_id) 431 { 432 char *nodename; 433 int ret; 434 435 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 436 qemu_fdt_add_subnode(fdt, nodename); 437 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 438 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base, 439 scells, mem_len); 440 if (ret < 0) { 441 goto out; 442 } 443 444 /* only set the NUMA ID if it is specified */ 445 if (numa_node_id >= 0) { 446 ret = qemu_fdt_setprop_cell(fdt, nodename, 447 "numa-node-id", numa_node_id); 448 } 449 out: 450 g_free(nodename); 451 return ret; 452 } 453 454 static void fdt_add_psci_node(void *fdt) 455 { 456 uint32_t cpu_suspend_fn; 457 uint32_t cpu_off_fn; 458 uint32_t cpu_on_fn; 459 uint32_t migrate_fn; 460 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 461 const char *psci_method; 462 int64_t psci_conduit; 463 int rc; 464 465 psci_conduit = object_property_get_int(OBJECT(armcpu), 466 "psci-conduit", 467 &error_abort); 468 switch (psci_conduit) { 469 case QEMU_PSCI_CONDUIT_DISABLED: 470 return; 471 case QEMU_PSCI_CONDUIT_HVC: 472 psci_method = "hvc"; 473 break; 474 case QEMU_PSCI_CONDUIT_SMC: 475 psci_method = "smc"; 476 break; 477 default: 478 g_assert_not_reached(); 479 } 480 481 /* 482 * If /psci node is present in provided DTB, assume that no fixup 483 * is necessary and all PSCI configuration should be taken as-is 484 */ 485 rc = fdt_path_offset(fdt, "/psci"); 486 if (rc >= 0) { 487 return; 488 } 489 490 qemu_fdt_add_subnode(fdt, "/psci"); 491 if (armcpu->psci_version == 2) { 492 const char comp[] = "arm,psci-0.2\0arm,psci"; 493 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 494 495 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 496 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 497 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 498 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 499 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 500 } else { 501 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 502 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 503 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 504 } 505 } else { 506 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 507 508 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 509 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 510 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 511 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 512 } 513 514 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 515 * to the instruction that should be used to invoke PSCI functions. 516 * However, the device tree binding uses 'method' instead, so that is 517 * what we should use here. 518 */ 519 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 520 521 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 522 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 523 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 524 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 525 } 526 527 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 528 hwaddr addr_limit, AddressSpace *as) 529 { 530 void *fdt = NULL; 531 int size, rc, n = 0; 532 uint32_t acells, scells; 533 unsigned int i; 534 hwaddr mem_base, mem_len; 535 char **node_path; 536 Error *err = NULL; 537 538 if (binfo->dtb_filename) { 539 char *filename; 540 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 541 if (!filename) { 542 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 543 goto fail; 544 } 545 546 fdt = load_device_tree(filename, &size); 547 if (!fdt) { 548 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 549 g_free(filename); 550 goto fail; 551 } 552 g_free(filename); 553 } else { 554 fdt = binfo->get_dtb(binfo, &size); 555 if (!fdt) { 556 fprintf(stderr, "Board was unable to create a dtb blob\n"); 557 goto fail; 558 } 559 } 560 561 if (addr_limit > addr && size > (addr_limit - addr)) { 562 /* Installing the device tree blob at addr would exceed addr_limit. 563 * Whether this constitutes failure is up to the caller to decide, 564 * so just return 0 as size, i.e., no error. 565 */ 566 g_free(fdt); 567 return 0; 568 } 569 570 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 571 NULL, &error_fatal); 572 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 573 NULL, &error_fatal); 574 if (acells == 0 || scells == 0) { 575 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 576 goto fail; 577 } 578 579 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { 580 /* This is user error so deserves a friendlier error message 581 * than the failure of setprop_sized_cells would provide 582 */ 583 fprintf(stderr, "qemu: dtb file not compatible with " 584 "RAM size > 4GB\n"); 585 goto fail; 586 } 587 588 /* nop all root nodes matching /memory or /memory@unit-address */ 589 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 590 if (err) { 591 error_report_err(err); 592 goto fail; 593 } 594 while (node_path[n]) { 595 if (g_str_has_prefix(node_path[n], "/memory")) { 596 qemu_fdt_nop_node(fdt, node_path[n]); 597 } 598 n++; 599 } 600 g_strfreev(node_path); 601 602 if (nb_numa_nodes > 0) { 603 mem_base = binfo->loader_start; 604 for (i = 0; i < nb_numa_nodes; i++) { 605 mem_len = numa_info[i].node_mem; 606 rc = fdt_add_memory_node(fdt, acells, mem_base, 607 scells, mem_len, i); 608 if (rc < 0) { 609 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 610 mem_base); 611 goto fail; 612 } 613 614 mem_base += mem_len; 615 } 616 } else { 617 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start, 618 scells, binfo->ram_size, -1); 619 if (rc < 0) { 620 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 621 binfo->loader_start); 622 goto fail; 623 } 624 } 625 626 rc = fdt_path_offset(fdt, "/chosen"); 627 if (rc < 0) { 628 qemu_fdt_add_subnode(fdt, "/chosen"); 629 } 630 631 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { 632 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 633 binfo->kernel_cmdline); 634 if (rc < 0) { 635 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 636 goto fail; 637 } 638 } 639 640 if (binfo->initrd_size) { 641 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 642 binfo->initrd_start); 643 if (rc < 0) { 644 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 645 goto fail; 646 } 647 648 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 649 binfo->initrd_start + binfo->initrd_size); 650 if (rc < 0) { 651 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 652 goto fail; 653 } 654 } 655 656 fdt_add_psci_node(fdt); 657 658 if (binfo->modify_dtb) { 659 binfo->modify_dtb(binfo, fdt); 660 } 661 662 qemu_fdt_dumpdtb(fdt, size); 663 664 /* Put the DTB into the memory map as a ROM image: this will ensure 665 * the DTB is copied again upon reset, even if addr points into RAM. 666 */ 667 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 668 669 g_free(fdt); 670 671 return size; 672 673 fail: 674 g_free(fdt); 675 return -1; 676 } 677 678 static void do_cpu_reset(void *opaque) 679 { 680 ARMCPU *cpu = opaque; 681 CPUState *cs = CPU(cpu); 682 CPUARMState *env = &cpu->env; 683 const struct arm_boot_info *info = env->boot_info; 684 685 cpu_reset(cs); 686 if (info) { 687 if (!info->is_linux) { 688 int i; 689 /* Jump to the entry point. */ 690 uint64_t entry = info->entry; 691 692 switch (info->endianness) { 693 case ARM_ENDIANNESS_LE: 694 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 695 for (i = 1; i < 4; ++i) { 696 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 697 } 698 env->uncached_cpsr &= ~CPSR_E; 699 break; 700 case ARM_ENDIANNESS_BE8: 701 env->cp15.sctlr_el[1] |= SCTLR_E0E; 702 for (i = 1; i < 4; ++i) { 703 env->cp15.sctlr_el[i] |= SCTLR_EE; 704 } 705 env->uncached_cpsr |= CPSR_E; 706 break; 707 case ARM_ENDIANNESS_BE32: 708 env->cp15.sctlr_el[1] |= SCTLR_B; 709 break; 710 case ARM_ENDIANNESS_UNKNOWN: 711 break; /* Board's decision */ 712 default: 713 g_assert_not_reached(); 714 } 715 716 cpu_set_pc(cs, entry); 717 } else { 718 /* If we are booting Linux then we need to check whether we are 719 * booting into secure or non-secure state and adjust the state 720 * accordingly. Out of reset, ARM is defined to be in secure state 721 * (SCR.NS = 0), we change that here if non-secure boot has been 722 * requested. 723 */ 724 if (arm_feature(env, ARM_FEATURE_EL3)) { 725 /* AArch64 is defined to come out of reset into EL3 if enabled. 726 * If we are booting Linux then we need to adjust our EL as 727 * Linux expects us to be in EL2 or EL1. AArch32 resets into 728 * SVC, which Linux expects, so no privilege/exception level to 729 * adjust. 730 */ 731 if (env->aarch64) { 732 env->cp15.scr_el3 |= SCR_RW; 733 if (arm_feature(env, ARM_FEATURE_EL2)) { 734 env->cp15.hcr_el2 |= HCR_RW; 735 env->pstate = PSTATE_MODE_EL2h; 736 } else { 737 env->pstate = PSTATE_MODE_EL1h; 738 } 739 /* AArch64 kernels never boot in secure mode */ 740 assert(!info->secure_boot); 741 /* This hook is only supported for AArch32 currently: 742 * bootloader_aarch64[] will not call the hook, and 743 * the code above has already dropped us into EL2 or EL1. 744 */ 745 assert(!info->secure_board_setup); 746 } 747 748 if (arm_feature(env, ARM_FEATURE_EL2)) { 749 /* If we have EL2 then Linux expects the HVC insn to work */ 750 env->cp15.scr_el3 |= SCR_HCE; 751 } 752 753 /* Set to non-secure if not a secure boot */ 754 if (!info->secure_boot && 755 (cs != first_cpu || !info->secure_board_setup)) { 756 /* Linux expects non-secure state */ 757 env->cp15.scr_el3 |= SCR_NS; 758 } 759 } 760 761 if (!env->aarch64 && !info->secure_boot && 762 arm_feature(env, ARM_FEATURE_EL2)) { 763 /* 764 * This is an AArch32 boot not to Secure state, and 765 * we have Hyp mode available, so boot the kernel into 766 * Hyp mode. This is not how the CPU comes out of reset, 767 * so we need to manually put it there. 768 */ 769 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw); 770 } 771 772 if (cs == first_cpu) { 773 AddressSpace *as = arm_boot_address_space(cpu, info); 774 775 cpu_set_pc(cs, info->loader_start); 776 777 if (!have_dtb(info)) { 778 if (old_param) { 779 set_kernel_args_old(info, as); 780 } else { 781 set_kernel_args(info, as); 782 } 783 } 784 } else { 785 info->secondary_cpu_reset_hook(cpu, info); 786 } 787 } 788 } 789 } 790 791 /** 792 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 793 * by key. 794 * @fw_cfg: The firmware config instance to store the data in. 795 * @size_key: The firmware config key to store the size of the loaded 796 * data under, with fw_cfg_add_i32(). 797 * @data_key: The firmware config key to store the loaded data under, 798 * with fw_cfg_add_bytes(). 799 * @image_name: The name of the image file to load. If it is NULL, the 800 * function returns without doing anything. 801 * @try_decompress: Whether the image should be decompressed (gunzipped) before 802 * adding it to fw_cfg. If decompression fails, the image is 803 * loaded as-is. 804 * 805 * In case of failure, the function prints an error message to stderr and the 806 * process exits with status 1. 807 */ 808 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 809 uint16_t data_key, const char *image_name, 810 bool try_decompress) 811 { 812 size_t size = -1; 813 uint8_t *data; 814 815 if (image_name == NULL) { 816 return; 817 } 818 819 if (try_decompress) { 820 size = load_image_gzipped_buffer(image_name, 821 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 822 } 823 824 if (size == (size_t)-1) { 825 gchar *contents; 826 gsize length; 827 828 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 829 error_report("failed to load \"%s\"", image_name); 830 exit(1); 831 } 832 size = length; 833 data = (uint8_t *)contents; 834 } 835 836 fw_cfg_add_i32(fw_cfg, size_key, size); 837 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 838 } 839 840 static int do_arm_linux_init(Object *obj, void *opaque) 841 { 842 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 843 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 844 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 845 struct arm_boot_info *info = opaque; 846 847 if (albifc->arm_linux_init) { 848 albifc->arm_linux_init(albif, info->secure_boot); 849 } 850 } 851 return 0; 852 } 853 854 static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 855 uint64_t *lowaddr, uint64_t *highaddr, 856 int elf_machine, AddressSpace *as) 857 { 858 bool elf_is64; 859 union { 860 Elf32_Ehdr h32; 861 Elf64_Ehdr h64; 862 } elf_header; 863 int data_swab = 0; 864 bool big_endian; 865 int64_t ret = -1; 866 Error *err = NULL; 867 868 869 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 870 if (err) { 871 error_free(err); 872 return ret; 873 } 874 875 if (elf_is64) { 876 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 877 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 878 : ARM_ENDIANNESS_LE; 879 } else { 880 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 881 if (big_endian) { 882 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 883 info->endianness = ARM_ENDIANNESS_BE8; 884 } else { 885 info->endianness = ARM_ENDIANNESS_BE32; 886 /* In BE32, the CPU has a different view of the per-byte 887 * address map than the rest of the system. BE32 ELF files 888 * are organised such that they can be programmed through 889 * the CPU's per-word byte-reversed view of the world. QEMU 890 * however loads ELF files independently of the CPU. So 891 * tell the ELF loader to byte reverse the data for us. 892 */ 893 data_swab = 2; 894 } 895 } else { 896 info->endianness = ARM_ENDIANNESS_LE; 897 } 898 } 899 900 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL, 901 pentry, lowaddr, highaddr, big_endian, elf_machine, 902 1, data_swab, as); 903 if (ret <= 0) { 904 /* The header loaded but the image didn't */ 905 exit(1); 906 } 907 908 return ret; 909 } 910 911 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 912 hwaddr *entry, AddressSpace *as) 913 { 914 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 915 uint64_t kernel_size = 0; 916 uint8_t *buffer; 917 int size; 918 919 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 920 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 921 &buffer); 922 923 if (size < 0) { 924 gsize len; 925 926 /* Load as raw file otherwise */ 927 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 928 return -1; 929 } 930 size = len; 931 } 932 933 /* check the arm64 magic header value -- very old kernels may not have it */ 934 if (size > ARM64_MAGIC_OFFSET + 4 && 935 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 936 uint64_t hdrvals[2]; 937 938 /* The arm64 Image header has text_offset and image_size fields at 8 and 939 * 16 bytes into the Image header, respectively. The text_offset field 940 * is only valid if the image_size is non-zero. 941 */ 942 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 943 944 kernel_size = le64_to_cpu(hdrvals[1]); 945 946 if (kernel_size != 0) { 947 kernel_load_offset = le64_to_cpu(hdrvals[0]); 948 949 /* 950 * We write our startup "bootloader" at the very bottom of RAM, 951 * so that bit can't be used for the image. Luckily the Image 952 * format specification is that the image requests only an offset 953 * from a 2MB boundary, not an absolute load address. So if the 954 * image requests an offset that might mean it overlaps with the 955 * bootloader, we can just load it starting at 2MB+offset rather 956 * than 0MB + offset. 957 */ 958 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 959 kernel_load_offset += 2 * MiB; 960 } 961 } 962 } 963 964 /* 965 * Kernels before v3.17 don't populate the image_size field, and 966 * raw images have no header. For those our best guess at the size 967 * is the size of the Image file itself. 968 */ 969 if (kernel_size == 0) { 970 kernel_size = size; 971 } 972 973 *entry = mem_base + kernel_load_offset; 974 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 975 976 g_free(buffer); 977 978 return kernel_size; 979 } 980 981 static void arm_setup_direct_kernel_boot(ARMCPU *cpu, 982 struct arm_boot_info *info) 983 { 984 /* Set up for a direct boot of a kernel image file. */ 985 CPUState *cs; 986 AddressSpace *as = arm_boot_address_space(cpu, info); 987 int kernel_size; 988 int initrd_size; 989 int is_linux = 0; 990 uint64_t elf_entry; 991 /* Addresses of first byte used and first byte not used by the image */ 992 uint64_t image_low_addr = 0, image_high_addr = 0; 993 int elf_machine; 994 hwaddr entry; 995 static const ARMInsnFixup *primary_loader; 996 uint64_t ram_end = info->loader_start + info->ram_size; 997 998 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 999 primary_loader = bootloader_aarch64; 1000 elf_machine = EM_AARCH64; 1001 } else { 1002 primary_loader = bootloader; 1003 if (!info->write_board_setup) { 1004 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 1005 } 1006 elf_machine = EM_ARM; 1007 } 1008 1009 if (!info->secondary_cpu_reset_hook) { 1010 info->secondary_cpu_reset_hook = default_reset_secondary; 1011 } 1012 if (!info->write_secondary_boot) { 1013 info->write_secondary_boot = default_write_secondary; 1014 } 1015 1016 if (info->nb_cpus == 0) 1017 info->nb_cpus = 1; 1018 1019 /* Assume that raw images are linux kernels, and ELF images are not. */ 1020 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr, 1021 &image_high_addr, elf_machine, as); 1022 if (kernel_size > 0 && have_dtb(info)) { 1023 /* 1024 * If there is still some room left at the base of RAM, try and put 1025 * the DTB there like we do for images loaded with -bios or -pflash. 1026 */ 1027 if (image_low_addr > info->loader_start 1028 || image_high_addr < info->loader_start) { 1029 /* 1030 * Set image_low_addr as address limit for arm_load_dtb if it may be 1031 * pointing into RAM, otherwise pass '0' (no limit) 1032 */ 1033 if (image_low_addr < info->loader_start) { 1034 image_low_addr = 0; 1035 } 1036 info->dtb_start = info->loader_start; 1037 info->dtb_limit = image_low_addr; 1038 } 1039 } 1040 entry = elf_entry; 1041 if (kernel_size < 0) { 1042 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; 1043 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, 1044 &is_linux, NULL, NULL, as); 1045 if (kernel_size >= 0) { 1046 image_low_addr = loadaddr; 1047 image_high_addr = image_low_addr + kernel_size; 1048 } 1049 } 1050 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1051 kernel_size = load_aarch64_image(info->kernel_filename, 1052 info->loader_start, &entry, as); 1053 is_linux = 1; 1054 if (kernel_size >= 0) { 1055 image_low_addr = entry; 1056 image_high_addr = image_low_addr + kernel_size; 1057 } 1058 } else if (kernel_size < 0) { 1059 /* 32-bit ARM */ 1060 entry = info->loader_start + KERNEL_LOAD_ADDR; 1061 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1062 ram_end - KERNEL_LOAD_ADDR, as); 1063 is_linux = 1; 1064 if (kernel_size >= 0) { 1065 image_low_addr = entry; 1066 image_high_addr = image_low_addr + kernel_size; 1067 } 1068 } 1069 if (kernel_size < 0) { 1070 error_report("could not load kernel '%s'", info->kernel_filename); 1071 exit(1); 1072 } 1073 1074 if (kernel_size > info->ram_size) { 1075 error_report("kernel '%s' is too large to fit in RAM " 1076 "(kernel size %d, RAM size %" PRId64 ")", 1077 info->kernel_filename, kernel_size, info->ram_size); 1078 exit(1); 1079 } 1080 1081 info->entry = entry; 1082 1083 /* 1084 * We want to put the initrd far enough into RAM that when the 1085 * kernel is uncompressed it will not clobber the initrd. However 1086 * on boards without much RAM we must ensure that we still leave 1087 * enough room for a decent sized initrd, and on boards with large 1088 * amounts of RAM we must avoid the initrd being so far up in RAM 1089 * that it is outside lowmem and inaccessible to the kernel. 1090 * So for boards with less than 256MB of RAM we put the initrd 1091 * halfway into RAM, and for boards with 256MB of RAM or more we put 1092 * the initrd at 128MB. 1093 * We also refuse to put the initrd somewhere that will definitely 1094 * overlay the kernel we just loaded, though for kernel formats which 1095 * don't tell us their exact size (eg self-decompressing 32-bit kernels) 1096 * we might still make a bad choice here. 1097 */ 1098 info->initrd_start = info->loader_start + 1099 MIN(info->ram_size / 2, 128 * 1024 * 1024); 1100 if (image_high_addr) { 1101 info->initrd_start = MAX(info->initrd_start, image_high_addr); 1102 } 1103 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); 1104 1105 if (is_linux) { 1106 uint32_t fixupcontext[FIXUP_MAX]; 1107 1108 if (info->initrd_filename) { 1109 1110 if (info->initrd_start >= ram_end) { 1111 error_report("not enough space after kernel to load initrd"); 1112 exit(1); 1113 } 1114 1115 initrd_size = load_ramdisk_as(info->initrd_filename, 1116 info->initrd_start, 1117 ram_end - info->initrd_start, as); 1118 if (initrd_size < 0) { 1119 initrd_size = load_image_targphys_as(info->initrd_filename, 1120 info->initrd_start, 1121 ram_end - 1122 info->initrd_start, 1123 as); 1124 } 1125 if (initrd_size < 0) { 1126 error_report("could not load initrd '%s'", 1127 info->initrd_filename); 1128 exit(1); 1129 } 1130 if (info->initrd_start + initrd_size > ram_end) { 1131 error_report("could not load initrd '%s': " 1132 "too big to fit into RAM after the kernel", 1133 info->initrd_filename); 1134 exit(1); 1135 } 1136 } else { 1137 initrd_size = 0; 1138 } 1139 info->initrd_size = initrd_size; 1140 1141 fixupcontext[FIXUP_BOARDID] = info->board_id; 1142 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1143 1144 /* 1145 * for device tree boot, we pass the DTB directly in r2. Otherwise 1146 * we point to the kernel args. 1147 */ 1148 if (have_dtb(info)) { 1149 hwaddr align; 1150 1151 if (elf_machine == EM_AARCH64) { 1152 /* 1153 * Some AArch64 kernels on early bootup map the fdt region as 1154 * 1155 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1156 * 1157 * Let's play safe and prealign it to 2MB to give us some space. 1158 */ 1159 align = 2 * 1024 * 1024; 1160 } else { 1161 /* 1162 * Some 32bit kernels will trash anything in the 4K page the 1163 * initrd ends in, so make sure the DTB isn't caught up in that. 1164 */ 1165 align = 4096; 1166 } 1167 1168 /* Place the DTB after the initrd in memory with alignment. */ 1169 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1170 align); 1171 if (info->dtb_start >= ram_end) { 1172 error_report("Not enough space for DTB after kernel/initrd"); 1173 exit(1); 1174 } 1175 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; 1176 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; 1177 } else { 1178 fixupcontext[FIXUP_ARGPTR_LO] = 1179 info->loader_start + KERNEL_ARGS_ADDR; 1180 fixupcontext[FIXUP_ARGPTR_HI] = 1181 (info->loader_start + KERNEL_ARGS_ADDR) >> 32; 1182 if (info->ram_size >= (1ULL << 32)) { 1183 error_report("RAM size must be less than 4GB to boot" 1184 " Linux kernel using ATAGS (try passing a device tree" 1185 " using -dtb)"); 1186 exit(1); 1187 } 1188 } 1189 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; 1190 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; 1191 1192 write_bootloader("bootloader", info->loader_start, 1193 primary_loader, fixupcontext, as); 1194 1195 if (info->nb_cpus > 1) { 1196 info->write_secondary_boot(cpu, info); 1197 } 1198 if (info->write_board_setup) { 1199 info->write_board_setup(cpu, info); 1200 } 1201 1202 /* 1203 * Notify devices which need to fake up firmware initialization 1204 * that we're doing a direct kernel boot. 1205 */ 1206 object_child_foreach_recursive(object_get_root(), 1207 do_arm_linux_init, info); 1208 } 1209 info->is_linux = is_linux; 1210 1211 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1212 ARM_CPU(cs)->env.boot_info = info; 1213 } 1214 } 1215 1216 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) 1217 { 1218 /* Set up for booting firmware (which might load a kernel via fw_cfg) */ 1219 1220 if (have_dtb(info)) { 1221 /* 1222 * If we have a device tree blob, but no kernel to supply it to (or 1223 * the kernel is supposed to be loaded by the bootloader), copy the 1224 * DTB to the base of RAM for the bootloader to pick up. 1225 */ 1226 info->dtb_start = info->loader_start; 1227 } 1228 1229 if (info->kernel_filename) { 1230 FWCfgState *fw_cfg; 1231 bool try_decompressing_kernel; 1232 1233 fw_cfg = fw_cfg_find(); 1234 try_decompressing_kernel = arm_feature(&cpu->env, 1235 ARM_FEATURE_AARCH64); 1236 1237 /* 1238 * Expose the kernel, the command line, and the initrd in fw_cfg. 1239 * We don't process them here at all, it's all left to the 1240 * firmware. 1241 */ 1242 load_image_to_fw_cfg(fw_cfg, 1243 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1244 info->kernel_filename, 1245 try_decompressing_kernel); 1246 load_image_to_fw_cfg(fw_cfg, 1247 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1248 info->initrd_filename, false); 1249 1250 if (info->kernel_cmdline) { 1251 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1252 strlen(info->kernel_cmdline) + 1); 1253 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1254 info->kernel_cmdline); 1255 } 1256 } 1257 1258 /* 1259 * We will start from address 0 (typically a boot ROM image) in the 1260 * same way as hardware. Leave env->boot_info NULL, so that 1261 * do_cpu_reset() knows it does not need to alter the PC on reset. 1262 */ 1263 } 1264 1265 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 1266 { 1267 CPUState *cs; 1268 AddressSpace *as = arm_boot_address_space(cpu, info); 1269 1270 /* 1271 * CPU objects (unlike devices) are not automatically reset on system 1272 * reset, so we must always register a handler to do so. If we're 1273 * actually loading a kernel, the handler is also responsible for 1274 * arranging that we start it correctly. 1275 */ 1276 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1277 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1278 } 1279 1280 /* 1281 * The board code is not supposed to set secure_board_setup unless 1282 * running its code in secure mode is actually possible, and KVM 1283 * doesn't support secure. 1284 */ 1285 assert(!(info->secure_board_setup && kvm_enabled())); 1286 1287 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 1288 info->dtb_limit = 0; 1289 1290 /* Load the kernel. */ 1291 if (!info->kernel_filename || info->firmware_loaded) { 1292 arm_setup_firmware_boot(cpu, info); 1293 } else { 1294 arm_setup_direct_kernel_boot(cpu, info); 1295 } 1296 1297 if (!info->skip_dtb_autoload && have_dtb(info)) { 1298 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { 1299 exit(1); 1300 } 1301 } 1302 } 1303 1304 static const TypeInfo arm_linux_boot_if_info = { 1305 .name = TYPE_ARM_LINUX_BOOT_IF, 1306 .parent = TYPE_INTERFACE, 1307 .class_size = sizeof(ARMLinuxBootIfClass), 1308 }; 1309 1310 static void arm_linux_boot_register_types(void) 1311 { 1312 type_register_static(&arm_linux_boot_if_info); 1313 } 1314 1315 type_init(arm_linux_boot_register_types) 1316