1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/datadir.h" 12 #include "qemu/error-report.h" 13 #include "qapi/error.h" 14 #include <libfdt.h> 15 #include "hw/arm/boot.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "sysemu/kvm.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/numa.h" 20 #include "hw/boards.h" 21 #include "sysemu/reset.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "sysemu/device_tree.h" 25 #include "qemu/config-file.h" 26 #include "qemu/option.h" 27 #include "qemu/units.h" 28 29 /* Kernel boot protocol is specified in the kernel docs 30 * Documentation/arm/Booting and Documentation/arm64/booting.txt 31 * They have different preferred image load offsets from system RAM base. 32 */ 33 #define KERNEL_ARGS_ADDR 0x100 34 #define KERNEL_NOLOAD_ADDR 0x02000000 35 #define KERNEL_LOAD_ADDR 0x00010000 36 #define KERNEL64_LOAD_ADDR 0x00080000 37 38 #define ARM64_TEXT_OFFSET_OFFSET 8 39 #define ARM64_MAGIC_OFFSET 56 40 41 #define BOOTLOADER_MAX_SIZE (4 * KiB) 42 43 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 44 const struct arm_boot_info *info) 45 { 46 /* Return the address space to use for bootloader reads and writes. 47 * We prefer the secure address space if the CPU has it and we're 48 * going to boot the guest into it. 49 */ 50 int asidx; 51 CPUState *cs = CPU(cpu); 52 53 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 54 asidx = ARMASIdx_S; 55 } else { 56 asidx = ARMASIdx_NS; 57 } 58 59 return cpu_get_address_space(cs, asidx); 60 } 61 62 typedef enum { 63 FIXUP_NONE = 0, /* do nothing */ 64 FIXUP_TERMINATOR, /* end of insns */ 65 FIXUP_BOARDID, /* overwrite with board ID number */ 66 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 67 FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */ 68 FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */ 69 FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */ 70 FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */ 71 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 72 FIXUP_BOOTREG, /* overwrite with boot register address */ 73 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 74 FIXUP_MAX, 75 } FixupType; 76 77 typedef struct ARMInsnFixup { 78 uint32_t insn; 79 FixupType fixup; 80 } ARMInsnFixup; 81 82 static const ARMInsnFixup bootloader_aarch64[] = { 83 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 84 { 0xaa1f03e1 }, /* mov x1, xzr */ 85 { 0xaa1f03e2 }, /* mov x2, xzr */ 86 { 0xaa1f03e3 }, /* mov x3, xzr */ 87 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 88 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 89 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ 90 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ 91 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ 92 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ 93 { 0, FIXUP_TERMINATOR } 94 }; 95 96 /* A very small bootloader: call the board-setup code (if needed), 97 * set r0-r2, then jump to the kernel. 98 * If we're not calling boot setup code then we don't copy across 99 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 100 */ 101 102 static const ARMInsnFixup bootloader[] = { 103 { 0xe28fe004 }, /* add lr, pc, #4 */ 104 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 105 { 0, FIXUP_BOARD_SETUP }, 106 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 107 { 0xe3a00000 }, /* mov r0, #0 */ 108 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 109 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 110 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 111 { 0, FIXUP_BOARDID }, 112 { 0, FIXUP_ARGPTR_LO }, 113 { 0, FIXUP_ENTRYPOINT_LO }, 114 { 0, FIXUP_TERMINATOR } 115 }; 116 117 /* Handling for secondary CPU boot in a multicore system. 118 * Unlike the uniprocessor/primary CPU boot, this is platform 119 * dependent. The default code here is based on the secondary 120 * CPU boot protocol used on realview/vexpress boards, with 121 * some parameterisation to increase its flexibility. 122 * QEMU platform models for which this code is not appropriate 123 * should override write_secondary_boot and secondary_cpu_reset_hook 124 * instead. 125 * 126 * This code enables the interrupt controllers for the secondary 127 * CPUs and then puts all the secondary CPUs into a loop waiting 128 * for an interprocessor interrupt and polling a configurable 129 * location for the kernel secondary CPU entry point. 130 */ 131 #define DSB_INSN 0xf57ff04f 132 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 133 134 static const ARMInsnFixup smpboot[] = { 135 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 136 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 137 { 0xe3a01001 }, /* mov r1, #1 */ 138 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 139 { 0xe3a010ff }, /* mov r1, #0xff */ 140 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 141 { 0, FIXUP_DSB }, /* dsb */ 142 { 0xe320f003 }, /* wfi */ 143 { 0xe5901000 }, /* ldr r1, [r0] */ 144 { 0xe1110001 }, /* tst r1, r1 */ 145 { 0x0afffffb }, /* beq <wfi> */ 146 { 0xe12fff11 }, /* bx r1 */ 147 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 148 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 149 { 0, FIXUP_TERMINATOR } 150 }; 151 152 static void write_bootloader(const char *name, hwaddr addr, 153 const ARMInsnFixup *insns, uint32_t *fixupcontext, 154 AddressSpace *as) 155 { 156 /* Fix up the specified bootloader fragment and write it into 157 * guest memory using rom_add_blob_fixed(). fixupcontext is 158 * an array giving the values to write in for the fixup types 159 * which write a value into the code array. 160 */ 161 int i, len; 162 uint32_t *code; 163 164 len = 0; 165 while (insns[len].fixup != FIXUP_TERMINATOR) { 166 len++; 167 } 168 169 code = g_new0(uint32_t, len); 170 171 for (i = 0; i < len; i++) { 172 uint32_t insn = insns[i].insn; 173 FixupType fixup = insns[i].fixup; 174 175 switch (fixup) { 176 case FIXUP_NONE: 177 break; 178 case FIXUP_BOARDID: 179 case FIXUP_BOARD_SETUP: 180 case FIXUP_ARGPTR_LO: 181 case FIXUP_ARGPTR_HI: 182 case FIXUP_ENTRYPOINT_LO: 183 case FIXUP_ENTRYPOINT_HI: 184 case FIXUP_GIC_CPU_IF: 185 case FIXUP_BOOTREG: 186 case FIXUP_DSB: 187 insn = fixupcontext[fixup]; 188 break; 189 default: 190 abort(); 191 } 192 code[i] = tswap32(insn); 193 } 194 195 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 196 197 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 198 199 g_free(code); 200 } 201 202 static void default_write_secondary(ARMCPU *cpu, 203 const struct arm_boot_info *info) 204 { 205 uint32_t fixupcontext[FIXUP_MAX]; 206 AddressSpace *as = arm_boot_address_space(cpu, info); 207 208 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 209 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 210 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 211 fixupcontext[FIXUP_DSB] = DSB_INSN; 212 } else { 213 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 214 } 215 216 write_bootloader("smpboot", info->smp_loader_start, 217 smpboot, fixupcontext, as); 218 } 219 220 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 221 const struct arm_boot_info *info, 222 hwaddr mvbar_addr) 223 { 224 AddressSpace *as = arm_boot_address_space(cpu, info); 225 int n; 226 uint32_t mvbar_blob[] = { 227 /* mvbar_addr: secure monitor vectors 228 * Default unimplemented and unused vectors to spin. Makes it 229 * easier to debug (as opposed to the CPU running away). 230 */ 231 0xeafffffe, /* (spin) */ 232 0xeafffffe, /* (spin) */ 233 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 234 0xeafffffe, /* (spin) */ 235 0xeafffffe, /* (spin) */ 236 0xeafffffe, /* (spin) */ 237 0xeafffffe, /* (spin) */ 238 0xeafffffe, /* (spin) */ 239 }; 240 uint32_t board_setup_blob[] = { 241 /* board setup addr */ 242 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ 243 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ 244 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ 245 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 246 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 247 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 248 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 249 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 250 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 251 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 252 0xe1a0f001, /* mov pc, r1 ;return */ 253 }; 254 255 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 256 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 257 258 /* check that these blobs don't overlap */ 259 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 260 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 261 262 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 263 mvbar_blob[n] = tswap32(mvbar_blob[n]); 264 } 265 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 266 mvbar_addr, as); 267 268 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 269 board_setup_blob[n] = tswap32(board_setup_blob[n]); 270 } 271 rom_add_blob_fixed_as("board-setup", board_setup_blob, 272 sizeof(board_setup_blob), info->board_setup_addr, as); 273 } 274 275 static void default_reset_secondary(ARMCPU *cpu, 276 const struct arm_boot_info *info) 277 { 278 AddressSpace *as = arm_boot_address_space(cpu, info); 279 CPUState *cs = CPU(cpu); 280 281 address_space_stl_notdirty(as, info->smp_bootreg_addr, 282 0, MEMTXATTRS_UNSPECIFIED, NULL); 283 cpu_set_pc(cs, info->smp_loader_start); 284 } 285 286 static inline bool have_dtb(const struct arm_boot_info *info) 287 { 288 return info->dtb_filename || info->get_dtb; 289 } 290 291 #define WRITE_WORD(p, value) do { \ 292 address_space_stl_notdirty(as, p, value, \ 293 MEMTXATTRS_UNSPECIFIED, NULL); \ 294 p += 4; \ 295 } while (0) 296 297 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 298 { 299 int initrd_size = info->initrd_size; 300 hwaddr base = info->loader_start; 301 hwaddr p; 302 303 p = base + KERNEL_ARGS_ADDR; 304 /* ATAG_CORE */ 305 WRITE_WORD(p, 5); 306 WRITE_WORD(p, 0x54410001); 307 WRITE_WORD(p, 1); 308 WRITE_WORD(p, 0x1000); 309 WRITE_WORD(p, 0); 310 /* ATAG_MEM */ 311 /* TODO: handle multiple chips on one ATAG list */ 312 WRITE_WORD(p, 4); 313 WRITE_WORD(p, 0x54410002); 314 WRITE_WORD(p, info->ram_size); 315 WRITE_WORD(p, info->loader_start); 316 if (initrd_size) { 317 /* ATAG_INITRD2 */ 318 WRITE_WORD(p, 4); 319 WRITE_WORD(p, 0x54420005); 320 WRITE_WORD(p, info->initrd_start); 321 WRITE_WORD(p, initrd_size); 322 } 323 if (info->kernel_cmdline && *info->kernel_cmdline) { 324 /* ATAG_CMDLINE */ 325 int cmdline_size; 326 327 cmdline_size = strlen(info->kernel_cmdline); 328 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 329 info->kernel_cmdline, cmdline_size + 1); 330 cmdline_size = (cmdline_size >> 2) + 1; 331 WRITE_WORD(p, cmdline_size + 2); 332 WRITE_WORD(p, 0x54410009); 333 p += cmdline_size * 4; 334 } 335 if (info->atag_board) { 336 /* ATAG_BOARD */ 337 int atag_board_len; 338 uint8_t atag_board_buf[0x1000]; 339 340 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 341 WRITE_WORD(p, (atag_board_len + 8) >> 2); 342 WRITE_WORD(p, 0x414f4d50); 343 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 344 atag_board_buf, atag_board_len); 345 p += atag_board_len; 346 } 347 /* ATAG_END */ 348 WRITE_WORD(p, 0); 349 WRITE_WORD(p, 0); 350 } 351 352 static void set_kernel_args_old(const struct arm_boot_info *info, 353 AddressSpace *as) 354 { 355 hwaddr p; 356 const char *s; 357 int initrd_size = info->initrd_size; 358 hwaddr base = info->loader_start; 359 360 /* see linux/include/asm-arm/setup.h */ 361 p = base + KERNEL_ARGS_ADDR; 362 /* page_size */ 363 WRITE_WORD(p, 4096); 364 /* nr_pages */ 365 WRITE_WORD(p, info->ram_size / 4096); 366 /* ramdisk_size */ 367 WRITE_WORD(p, 0); 368 #define FLAG_READONLY 1 369 #define FLAG_RDLOAD 4 370 #define FLAG_RDPROMPT 8 371 /* flags */ 372 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 373 /* rootdev */ 374 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 375 /* video_num_cols */ 376 WRITE_WORD(p, 0); 377 /* video_num_rows */ 378 WRITE_WORD(p, 0); 379 /* video_x */ 380 WRITE_WORD(p, 0); 381 /* video_y */ 382 WRITE_WORD(p, 0); 383 /* memc_control_reg */ 384 WRITE_WORD(p, 0); 385 /* unsigned char sounddefault */ 386 /* unsigned char adfsdrives */ 387 /* unsigned char bytes_per_char_h */ 388 /* unsigned char bytes_per_char_v */ 389 WRITE_WORD(p, 0); 390 /* pages_in_bank[4] */ 391 WRITE_WORD(p, 0); 392 WRITE_WORD(p, 0); 393 WRITE_WORD(p, 0); 394 WRITE_WORD(p, 0); 395 /* pages_in_vram */ 396 WRITE_WORD(p, 0); 397 /* initrd_start */ 398 if (initrd_size) { 399 WRITE_WORD(p, info->initrd_start); 400 } else { 401 WRITE_WORD(p, 0); 402 } 403 /* initrd_size */ 404 WRITE_WORD(p, initrd_size); 405 /* rd_start */ 406 WRITE_WORD(p, 0); 407 /* system_rev */ 408 WRITE_WORD(p, 0); 409 /* system_serial_low */ 410 WRITE_WORD(p, 0); 411 /* system_serial_high */ 412 WRITE_WORD(p, 0); 413 /* mem_fclk_21285 */ 414 WRITE_WORD(p, 0); 415 /* zero unused fields */ 416 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 417 WRITE_WORD(p, 0); 418 } 419 s = info->kernel_cmdline; 420 if (s) { 421 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1); 422 } else { 423 WRITE_WORD(p, 0); 424 } 425 } 426 427 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, 428 uint32_t scells, hwaddr mem_len, 429 int numa_node_id) 430 { 431 char *nodename; 432 int ret; 433 434 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 435 qemu_fdt_add_subnode(fdt, nodename); 436 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 437 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base, 438 scells, mem_len); 439 if (ret < 0) { 440 goto out; 441 } 442 443 /* only set the NUMA ID if it is specified */ 444 if (numa_node_id >= 0) { 445 ret = qemu_fdt_setprop_cell(fdt, nodename, 446 "numa-node-id", numa_node_id); 447 } 448 out: 449 g_free(nodename); 450 return ret; 451 } 452 453 static void fdt_add_psci_node(void *fdt) 454 { 455 uint32_t cpu_suspend_fn; 456 uint32_t cpu_off_fn; 457 uint32_t cpu_on_fn; 458 uint32_t migrate_fn; 459 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 460 const char *psci_method; 461 int64_t psci_conduit; 462 int rc; 463 464 psci_conduit = object_property_get_int(OBJECT(armcpu), 465 "psci-conduit", 466 &error_abort); 467 switch (psci_conduit) { 468 case QEMU_PSCI_CONDUIT_DISABLED: 469 return; 470 case QEMU_PSCI_CONDUIT_HVC: 471 psci_method = "hvc"; 472 break; 473 case QEMU_PSCI_CONDUIT_SMC: 474 psci_method = "smc"; 475 break; 476 default: 477 g_assert_not_reached(); 478 } 479 480 /* 481 * If /psci node is present in provided DTB, assume that no fixup 482 * is necessary and all PSCI configuration should be taken as-is 483 */ 484 rc = fdt_path_offset(fdt, "/psci"); 485 if (rc >= 0) { 486 return; 487 } 488 489 qemu_fdt_add_subnode(fdt, "/psci"); 490 if (armcpu->psci_version == 2) { 491 const char comp[] = "arm,psci-0.2\0arm,psci"; 492 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 493 494 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 495 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 496 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 497 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 498 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 499 } else { 500 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 501 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 502 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 503 } 504 } else { 505 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 506 507 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 508 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 509 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 510 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 511 } 512 513 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 514 * to the instruction that should be used to invoke PSCI functions. 515 * However, the device tree binding uses 'method' instead, so that is 516 * what we should use here. 517 */ 518 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 519 520 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 521 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 522 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 523 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 524 } 525 526 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 527 hwaddr addr_limit, AddressSpace *as, MachineState *ms) 528 { 529 void *fdt = NULL; 530 int size, rc, n = 0; 531 uint32_t acells, scells; 532 unsigned int i; 533 hwaddr mem_base, mem_len; 534 char **node_path; 535 Error *err = NULL; 536 537 if (binfo->dtb_filename) { 538 char *filename; 539 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 540 if (!filename) { 541 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 542 goto fail; 543 } 544 545 fdt = load_device_tree(filename, &size); 546 if (!fdt) { 547 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 548 g_free(filename); 549 goto fail; 550 } 551 g_free(filename); 552 } else { 553 fdt = binfo->get_dtb(binfo, &size); 554 if (!fdt) { 555 fprintf(stderr, "Board was unable to create a dtb blob\n"); 556 goto fail; 557 } 558 } 559 560 if (addr_limit > addr && size > (addr_limit - addr)) { 561 /* Installing the device tree blob at addr would exceed addr_limit. 562 * Whether this constitutes failure is up to the caller to decide, 563 * so just return 0 as size, i.e., no error. 564 */ 565 g_free(fdt); 566 return 0; 567 } 568 569 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 570 NULL, &error_fatal); 571 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 572 NULL, &error_fatal); 573 if (acells == 0 || scells == 0) { 574 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 575 goto fail; 576 } 577 578 if (scells < 2 && binfo->ram_size >= 4 * GiB) { 579 /* This is user error so deserves a friendlier error message 580 * than the failure of setprop_sized_cells would provide 581 */ 582 fprintf(stderr, "qemu: dtb file not compatible with " 583 "RAM size > 4GB\n"); 584 goto fail; 585 } 586 587 /* nop all root nodes matching /memory or /memory@unit-address */ 588 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 589 if (err) { 590 error_report_err(err); 591 goto fail; 592 } 593 while (node_path[n]) { 594 if (g_str_has_prefix(node_path[n], "/memory")) { 595 qemu_fdt_nop_node(fdt, node_path[n]); 596 } 597 n++; 598 } 599 g_strfreev(node_path); 600 601 /* 602 * We drop all the memory nodes which correspond to empty NUMA nodes 603 * from the device tree, because the Linux NUMA binding document 604 * states they should not be generated. Linux will get the NUMA node 605 * IDs of the empty NUMA nodes from the distance map if they are needed. 606 * This means QEMU users may be obliged to provide command lines which 607 * configure distance maps when the empty NUMA node IDs are needed and 608 * Linux's default distance map isn't sufficient. 609 */ 610 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) { 611 mem_base = binfo->loader_start; 612 for (i = 0; i < ms->numa_state->num_nodes; i++) { 613 mem_len = ms->numa_state->nodes[i].node_mem; 614 if (!mem_len) { 615 continue; 616 } 617 618 rc = fdt_add_memory_node(fdt, acells, mem_base, 619 scells, mem_len, i); 620 if (rc < 0) { 621 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 622 mem_base); 623 goto fail; 624 } 625 626 mem_base += mem_len; 627 } 628 } else { 629 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start, 630 scells, binfo->ram_size, -1); 631 if (rc < 0) { 632 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 633 binfo->loader_start); 634 goto fail; 635 } 636 } 637 638 rc = fdt_path_offset(fdt, "/chosen"); 639 if (rc < 0) { 640 qemu_fdt_add_subnode(fdt, "/chosen"); 641 } 642 643 if (ms->kernel_cmdline && *ms->kernel_cmdline) { 644 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 645 ms->kernel_cmdline); 646 if (rc < 0) { 647 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 648 goto fail; 649 } 650 } 651 652 if (binfo->initrd_size) { 653 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 654 binfo->initrd_start); 655 if (rc < 0) { 656 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 657 goto fail; 658 } 659 660 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 661 binfo->initrd_start + binfo->initrd_size); 662 if (rc < 0) { 663 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 664 goto fail; 665 } 666 } 667 668 fdt_add_psci_node(fdt); 669 670 if (binfo->modify_dtb) { 671 binfo->modify_dtb(binfo, fdt); 672 } 673 674 qemu_fdt_dumpdtb(fdt, size); 675 676 /* Put the DTB into the memory map as a ROM image: this will ensure 677 * the DTB is copied again upon reset, even if addr points into RAM. 678 */ 679 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 680 681 g_free(fdt); 682 683 return size; 684 685 fail: 686 g_free(fdt); 687 return -1; 688 } 689 690 static void do_cpu_reset(void *opaque) 691 { 692 ARMCPU *cpu = opaque; 693 CPUState *cs = CPU(cpu); 694 CPUARMState *env = &cpu->env; 695 const struct arm_boot_info *info = env->boot_info; 696 697 cpu_reset(cs); 698 if (info) { 699 if (!info->is_linux) { 700 int i; 701 /* Jump to the entry point. */ 702 uint64_t entry = info->entry; 703 704 switch (info->endianness) { 705 case ARM_ENDIANNESS_LE: 706 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 707 for (i = 1; i < 4; ++i) { 708 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 709 } 710 env->uncached_cpsr &= ~CPSR_E; 711 break; 712 case ARM_ENDIANNESS_BE8: 713 env->cp15.sctlr_el[1] |= SCTLR_E0E; 714 for (i = 1; i < 4; ++i) { 715 env->cp15.sctlr_el[i] |= SCTLR_EE; 716 } 717 env->uncached_cpsr |= CPSR_E; 718 break; 719 case ARM_ENDIANNESS_BE32: 720 env->cp15.sctlr_el[1] |= SCTLR_B; 721 break; 722 case ARM_ENDIANNESS_UNKNOWN: 723 break; /* Board's decision */ 724 default: 725 g_assert_not_reached(); 726 } 727 728 cpu_set_pc(cs, entry); 729 } else { 730 /* If we are booting Linux then we need to check whether we are 731 * booting into secure or non-secure state and adjust the state 732 * accordingly. Out of reset, ARM is defined to be in secure state 733 * (SCR.NS = 0), we change that here if non-secure boot has been 734 * requested. 735 */ 736 if (arm_feature(env, ARM_FEATURE_EL3)) { 737 /* AArch64 is defined to come out of reset into EL3 if enabled. 738 * If we are booting Linux then we need to adjust our EL as 739 * Linux expects us to be in EL2 or EL1. AArch32 resets into 740 * SVC, which Linux expects, so no privilege/exception level to 741 * adjust. 742 */ 743 if (env->aarch64) { 744 env->cp15.scr_el3 |= SCR_RW; 745 if (arm_feature(env, ARM_FEATURE_EL2)) { 746 env->cp15.hcr_el2 |= HCR_RW; 747 env->pstate = PSTATE_MODE_EL2h; 748 } else { 749 env->pstate = PSTATE_MODE_EL1h; 750 } 751 if (cpu_isar_feature(aa64_pauth, cpu)) { 752 env->cp15.scr_el3 |= SCR_API | SCR_APK; 753 } 754 if (cpu_isar_feature(aa64_mte, cpu)) { 755 env->cp15.scr_el3 |= SCR_ATA; 756 } 757 if (cpu_isar_feature(aa64_sve, cpu)) { 758 env->cp15.cptr_el[3] |= CPTR_EZ; 759 } 760 /* AArch64 kernels never boot in secure mode */ 761 assert(!info->secure_boot); 762 /* This hook is only supported for AArch32 currently: 763 * bootloader_aarch64[] will not call the hook, and 764 * the code above has already dropped us into EL2 or EL1. 765 */ 766 assert(!info->secure_board_setup); 767 } 768 769 if (arm_feature(env, ARM_FEATURE_EL2)) { 770 /* If we have EL2 then Linux expects the HVC insn to work */ 771 env->cp15.scr_el3 |= SCR_HCE; 772 } 773 774 /* Set to non-secure if not a secure boot */ 775 if (!info->secure_boot && 776 (cs != first_cpu || !info->secure_board_setup)) { 777 /* Linux expects non-secure state */ 778 env->cp15.scr_el3 |= SCR_NS; 779 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 780 env->cp15.nsacr |= 3 << 10; 781 } 782 } 783 784 if (!env->aarch64 && !info->secure_boot && 785 arm_feature(env, ARM_FEATURE_EL2)) { 786 /* 787 * This is an AArch32 boot not to Secure state, and 788 * we have Hyp mode available, so boot the kernel into 789 * Hyp mode. This is not how the CPU comes out of reset, 790 * so we need to manually put it there. 791 */ 792 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw); 793 } 794 795 if (cs == first_cpu) { 796 AddressSpace *as = arm_boot_address_space(cpu, info); 797 798 cpu_set_pc(cs, info->loader_start); 799 800 if (!have_dtb(info)) { 801 if (old_param) { 802 set_kernel_args_old(info, as); 803 } else { 804 set_kernel_args(info, as); 805 } 806 } 807 } else { 808 info->secondary_cpu_reset_hook(cpu, info); 809 } 810 } 811 arm_rebuild_hflags(env); 812 } 813 } 814 815 /** 816 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 817 * by key. 818 * @fw_cfg: The firmware config instance to store the data in. 819 * @size_key: The firmware config key to store the size of the loaded 820 * data under, with fw_cfg_add_i32(). 821 * @data_key: The firmware config key to store the loaded data under, 822 * with fw_cfg_add_bytes(). 823 * @image_name: The name of the image file to load. If it is NULL, the 824 * function returns without doing anything. 825 * @try_decompress: Whether the image should be decompressed (gunzipped) before 826 * adding it to fw_cfg. If decompression fails, the image is 827 * loaded as-is. 828 * 829 * In case of failure, the function prints an error message to stderr and the 830 * process exits with status 1. 831 */ 832 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 833 uint16_t data_key, const char *image_name, 834 bool try_decompress) 835 { 836 size_t size = -1; 837 uint8_t *data; 838 839 if (image_name == NULL) { 840 return; 841 } 842 843 if (try_decompress) { 844 size = load_image_gzipped_buffer(image_name, 845 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 846 } 847 848 if (size == (size_t)-1) { 849 gchar *contents; 850 gsize length; 851 852 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 853 error_report("failed to load \"%s\"", image_name); 854 exit(1); 855 } 856 size = length; 857 data = (uint8_t *)contents; 858 } 859 860 fw_cfg_add_i32(fw_cfg, size_key, size); 861 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 862 } 863 864 static int do_arm_linux_init(Object *obj, void *opaque) 865 { 866 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 867 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 868 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 869 struct arm_boot_info *info = opaque; 870 871 if (albifc->arm_linux_init) { 872 albifc->arm_linux_init(albif, info->secure_boot); 873 } 874 } 875 return 0; 876 } 877 878 static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 879 uint64_t *lowaddr, uint64_t *highaddr, 880 int elf_machine, AddressSpace *as) 881 { 882 bool elf_is64; 883 union { 884 Elf32_Ehdr h32; 885 Elf64_Ehdr h64; 886 } elf_header; 887 int data_swab = 0; 888 bool big_endian; 889 int64_t ret = -1; 890 Error *err = NULL; 891 892 893 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 894 if (err) { 895 error_free(err); 896 return ret; 897 } 898 899 if (elf_is64) { 900 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 901 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 902 : ARM_ENDIANNESS_LE; 903 } else { 904 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 905 if (big_endian) { 906 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 907 info->endianness = ARM_ENDIANNESS_BE8; 908 } else { 909 info->endianness = ARM_ENDIANNESS_BE32; 910 /* In BE32, the CPU has a different view of the per-byte 911 * address map than the rest of the system. BE32 ELF files 912 * are organised such that they can be programmed through 913 * the CPU's per-word byte-reversed view of the world. QEMU 914 * however loads ELF files independently of the CPU. So 915 * tell the ELF loader to byte reverse the data for us. 916 */ 917 data_swab = 2; 918 } 919 } else { 920 info->endianness = ARM_ENDIANNESS_LE; 921 } 922 } 923 924 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL, 925 pentry, lowaddr, highaddr, NULL, big_endian, elf_machine, 926 1, data_swab, as); 927 if (ret <= 0) { 928 /* The header loaded but the image didn't */ 929 exit(1); 930 } 931 932 return ret; 933 } 934 935 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 936 hwaddr *entry, AddressSpace *as) 937 { 938 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 939 uint64_t kernel_size = 0; 940 uint8_t *buffer; 941 int size; 942 943 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 944 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 945 &buffer); 946 947 if (size < 0) { 948 gsize len; 949 950 /* Load as raw file otherwise */ 951 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 952 return -1; 953 } 954 size = len; 955 } 956 957 /* check the arm64 magic header value -- very old kernels may not have it */ 958 if (size > ARM64_MAGIC_OFFSET + 4 && 959 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 960 uint64_t hdrvals[2]; 961 962 /* The arm64 Image header has text_offset and image_size fields at 8 and 963 * 16 bytes into the Image header, respectively. The text_offset field 964 * is only valid if the image_size is non-zero. 965 */ 966 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 967 968 kernel_size = le64_to_cpu(hdrvals[1]); 969 970 if (kernel_size != 0) { 971 kernel_load_offset = le64_to_cpu(hdrvals[0]); 972 973 /* 974 * We write our startup "bootloader" at the very bottom of RAM, 975 * so that bit can't be used for the image. Luckily the Image 976 * format specification is that the image requests only an offset 977 * from a 2MB boundary, not an absolute load address. So if the 978 * image requests an offset that might mean it overlaps with the 979 * bootloader, we can just load it starting at 2MB+offset rather 980 * than 0MB + offset. 981 */ 982 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 983 kernel_load_offset += 2 * MiB; 984 } 985 } 986 } 987 988 /* 989 * Kernels before v3.17 don't populate the image_size field, and 990 * raw images have no header. For those our best guess at the size 991 * is the size of the Image file itself. 992 */ 993 if (kernel_size == 0) { 994 kernel_size = size; 995 } 996 997 *entry = mem_base + kernel_load_offset; 998 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 999 1000 g_free(buffer); 1001 1002 return kernel_size; 1003 } 1004 1005 static void arm_setup_direct_kernel_boot(ARMCPU *cpu, 1006 struct arm_boot_info *info) 1007 { 1008 /* Set up for a direct boot of a kernel image file. */ 1009 CPUState *cs; 1010 AddressSpace *as = arm_boot_address_space(cpu, info); 1011 int kernel_size; 1012 int initrd_size; 1013 int is_linux = 0; 1014 uint64_t elf_entry; 1015 /* Addresses of first byte used and first byte not used by the image */ 1016 uint64_t image_low_addr = 0, image_high_addr = 0; 1017 int elf_machine; 1018 hwaddr entry; 1019 static const ARMInsnFixup *primary_loader; 1020 uint64_t ram_end = info->loader_start + info->ram_size; 1021 1022 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1023 primary_loader = bootloader_aarch64; 1024 elf_machine = EM_AARCH64; 1025 } else { 1026 primary_loader = bootloader; 1027 if (!info->write_board_setup) { 1028 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 1029 } 1030 elf_machine = EM_ARM; 1031 } 1032 1033 if (!info->secondary_cpu_reset_hook) { 1034 info->secondary_cpu_reset_hook = default_reset_secondary; 1035 } 1036 if (!info->write_secondary_boot) { 1037 info->write_secondary_boot = default_write_secondary; 1038 } 1039 1040 if (info->nb_cpus == 0) 1041 info->nb_cpus = 1; 1042 1043 /* Assume that raw images are linux kernels, and ELF images are not. */ 1044 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr, 1045 &image_high_addr, elf_machine, as); 1046 if (kernel_size > 0 && have_dtb(info)) { 1047 /* 1048 * If there is still some room left at the base of RAM, try and put 1049 * the DTB there like we do for images loaded with -bios or -pflash. 1050 */ 1051 if (image_low_addr > info->loader_start 1052 || image_high_addr < info->loader_start) { 1053 /* 1054 * Set image_low_addr as address limit for arm_load_dtb if it may be 1055 * pointing into RAM, otherwise pass '0' (no limit) 1056 */ 1057 if (image_low_addr < info->loader_start) { 1058 image_low_addr = 0; 1059 } 1060 info->dtb_start = info->loader_start; 1061 info->dtb_limit = image_low_addr; 1062 } 1063 } 1064 entry = elf_entry; 1065 if (kernel_size < 0) { 1066 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; 1067 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, 1068 &is_linux, NULL, NULL, as); 1069 if (kernel_size >= 0) { 1070 image_low_addr = loadaddr; 1071 image_high_addr = image_low_addr + kernel_size; 1072 } 1073 } 1074 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1075 kernel_size = load_aarch64_image(info->kernel_filename, 1076 info->loader_start, &entry, as); 1077 is_linux = 1; 1078 if (kernel_size >= 0) { 1079 image_low_addr = entry; 1080 image_high_addr = image_low_addr + kernel_size; 1081 } 1082 } else if (kernel_size < 0) { 1083 /* 32-bit ARM */ 1084 entry = info->loader_start + KERNEL_LOAD_ADDR; 1085 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1086 ram_end - KERNEL_LOAD_ADDR, as); 1087 is_linux = 1; 1088 if (kernel_size >= 0) { 1089 image_low_addr = entry; 1090 image_high_addr = image_low_addr + kernel_size; 1091 } 1092 } 1093 if (kernel_size < 0) { 1094 error_report("could not load kernel '%s'", info->kernel_filename); 1095 exit(1); 1096 } 1097 1098 if (kernel_size > info->ram_size) { 1099 error_report("kernel '%s' is too large to fit in RAM " 1100 "(kernel size %d, RAM size %" PRId64 ")", 1101 info->kernel_filename, kernel_size, info->ram_size); 1102 exit(1); 1103 } 1104 1105 info->entry = entry; 1106 1107 /* 1108 * We want to put the initrd far enough into RAM that when the 1109 * kernel is uncompressed it will not clobber the initrd. However 1110 * on boards without much RAM we must ensure that we still leave 1111 * enough room for a decent sized initrd, and on boards with large 1112 * amounts of RAM we must avoid the initrd being so far up in RAM 1113 * that it is outside lowmem and inaccessible to the kernel. 1114 * So for boards with less than 256MB of RAM we put the initrd 1115 * halfway into RAM, and for boards with 256MB of RAM or more we put 1116 * the initrd at 128MB. 1117 * We also refuse to put the initrd somewhere that will definitely 1118 * overlay the kernel we just loaded, though for kernel formats which 1119 * don't tell us their exact size (eg self-decompressing 32-bit kernels) 1120 * we might still make a bad choice here. 1121 */ 1122 info->initrd_start = info->loader_start + 1123 MIN(info->ram_size / 2, 128 * MiB); 1124 if (image_high_addr) { 1125 info->initrd_start = MAX(info->initrd_start, image_high_addr); 1126 } 1127 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); 1128 1129 if (is_linux) { 1130 uint32_t fixupcontext[FIXUP_MAX]; 1131 1132 if (info->initrd_filename) { 1133 1134 if (info->initrd_start >= ram_end) { 1135 error_report("not enough space after kernel to load initrd"); 1136 exit(1); 1137 } 1138 1139 initrd_size = load_ramdisk_as(info->initrd_filename, 1140 info->initrd_start, 1141 ram_end - info->initrd_start, as); 1142 if (initrd_size < 0) { 1143 initrd_size = load_image_targphys_as(info->initrd_filename, 1144 info->initrd_start, 1145 ram_end - 1146 info->initrd_start, 1147 as); 1148 } 1149 if (initrd_size < 0) { 1150 error_report("could not load initrd '%s'", 1151 info->initrd_filename); 1152 exit(1); 1153 } 1154 if (info->initrd_start + initrd_size > ram_end) { 1155 error_report("could not load initrd '%s': " 1156 "too big to fit into RAM after the kernel", 1157 info->initrd_filename); 1158 exit(1); 1159 } 1160 } else { 1161 initrd_size = 0; 1162 } 1163 info->initrd_size = initrd_size; 1164 1165 fixupcontext[FIXUP_BOARDID] = info->board_id; 1166 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1167 1168 /* 1169 * for device tree boot, we pass the DTB directly in r2. Otherwise 1170 * we point to the kernel args. 1171 */ 1172 if (have_dtb(info)) { 1173 hwaddr align; 1174 1175 if (elf_machine == EM_AARCH64) { 1176 /* 1177 * Some AArch64 kernels on early bootup map the fdt region as 1178 * 1179 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1180 * 1181 * Let's play safe and prealign it to 2MB to give us some space. 1182 */ 1183 align = 2 * MiB; 1184 } else { 1185 /* 1186 * Some 32bit kernels will trash anything in the 4K page the 1187 * initrd ends in, so make sure the DTB isn't caught up in that. 1188 */ 1189 align = 4 * KiB; 1190 } 1191 1192 /* Place the DTB after the initrd in memory with alignment. */ 1193 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1194 align); 1195 if (info->dtb_start >= ram_end) { 1196 error_report("Not enough space for DTB after kernel/initrd"); 1197 exit(1); 1198 } 1199 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; 1200 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; 1201 } else { 1202 fixupcontext[FIXUP_ARGPTR_LO] = 1203 info->loader_start + KERNEL_ARGS_ADDR; 1204 fixupcontext[FIXUP_ARGPTR_HI] = 1205 (info->loader_start + KERNEL_ARGS_ADDR) >> 32; 1206 if (info->ram_size >= 4 * GiB) { 1207 error_report("RAM size must be less than 4GB to boot" 1208 " Linux kernel using ATAGS (try passing a device tree" 1209 " using -dtb)"); 1210 exit(1); 1211 } 1212 } 1213 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; 1214 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; 1215 1216 write_bootloader("bootloader", info->loader_start, 1217 primary_loader, fixupcontext, as); 1218 1219 if (info->nb_cpus > 1) { 1220 info->write_secondary_boot(cpu, info); 1221 } 1222 if (info->write_board_setup) { 1223 info->write_board_setup(cpu, info); 1224 } 1225 1226 /* 1227 * Notify devices which need to fake up firmware initialization 1228 * that we're doing a direct kernel boot. 1229 */ 1230 object_child_foreach_recursive(object_get_root(), 1231 do_arm_linux_init, info); 1232 } 1233 info->is_linux = is_linux; 1234 1235 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1236 ARM_CPU(cs)->env.boot_info = info; 1237 } 1238 } 1239 1240 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) 1241 { 1242 /* Set up for booting firmware (which might load a kernel via fw_cfg) */ 1243 1244 if (have_dtb(info)) { 1245 /* 1246 * If we have a device tree blob, but no kernel to supply it to (or 1247 * the kernel is supposed to be loaded by the bootloader), copy the 1248 * DTB to the base of RAM for the bootloader to pick up. 1249 */ 1250 info->dtb_start = info->loader_start; 1251 } 1252 1253 if (info->kernel_filename) { 1254 FWCfgState *fw_cfg; 1255 bool try_decompressing_kernel; 1256 1257 fw_cfg = fw_cfg_find(); 1258 1259 if (!fw_cfg) { 1260 error_report("This machine type does not support loading both " 1261 "a guest firmware/BIOS image and a guest kernel at " 1262 "the same time. You should change your QEMU command " 1263 "line to specify one or the other, but not both."); 1264 exit(1); 1265 } 1266 1267 try_decompressing_kernel = arm_feature(&cpu->env, 1268 ARM_FEATURE_AARCH64); 1269 1270 /* 1271 * Expose the kernel, the command line, and the initrd in fw_cfg. 1272 * We don't process them here at all, it's all left to the 1273 * firmware. 1274 */ 1275 load_image_to_fw_cfg(fw_cfg, 1276 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1277 info->kernel_filename, 1278 try_decompressing_kernel); 1279 load_image_to_fw_cfg(fw_cfg, 1280 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1281 info->initrd_filename, false); 1282 1283 if (info->kernel_cmdline) { 1284 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1285 strlen(info->kernel_cmdline) + 1); 1286 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1287 info->kernel_cmdline); 1288 } 1289 } 1290 1291 /* 1292 * We will start from address 0 (typically a boot ROM image) in the 1293 * same way as hardware. Leave env->boot_info NULL, so that 1294 * do_cpu_reset() knows it does not need to alter the PC on reset. 1295 */ 1296 } 1297 1298 void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) 1299 { 1300 CPUState *cs; 1301 AddressSpace *as = arm_boot_address_space(cpu, info); 1302 1303 /* 1304 * CPU objects (unlike devices) are not automatically reset on system 1305 * reset, so we must always register a handler to do so. If we're 1306 * actually loading a kernel, the handler is also responsible for 1307 * arranging that we start it correctly. 1308 */ 1309 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1310 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1311 } 1312 1313 /* 1314 * The board code is not supposed to set secure_board_setup unless 1315 * running its code in secure mode is actually possible, and KVM 1316 * doesn't support secure. 1317 */ 1318 assert(!(info->secure_board_setup && kvm_enabled())); 1319 info->kernel_filename = ms->kernel_filename; 1320 info->kernel_cmdline = ms->kernel_cmdline; 1321 info->initrd_filename = ms->initrd_filename; 1322 info->dtb_filename = ms->dtb; 1323 info->dtb_limit = 0; 1324 1325 /* Load the kernel. */ 1326 if (!info->kernel_filename || info->firmware_loaded) { 1327 arm_setup_firmware_boot(cpu, info); 1328 } else { 1329 arm_setup_direct_kernel_boot(cpu, info); 1330 } 1331 1332 if (!info->skip_dtb_autoload && have_dtb(info)) { 1333 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1334 exit(1); 1335 } 1336 } 1337 } 1338 1339 static const TypeInfo arm_linux_boot_if_info = { 1340 .name = TYPE_ARM_LINUX_BOOT_IF, 1341 .parent = TYPE_INTERFACE, 1342 .class_size = sizeof(ARMLinuxBootIfClass), 1343 }; 1344 1345 static void arm_linux_boot_register_types(void) 1346 { 1347 type_register_static(&arm_linux_boot_if_info); 1348 } 1349 1350 type_init(arm_linux_boot_register_types) 1351