1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/datadir.h" 12 #include "qemu/error-report.h" 13 #include "qapi/error.h" 14 #include <libfdt.h> 15 #include "hw/arm/boot.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "sysemu/kvm.h" 18 #include "sysemu/tcg.h" 19 #include "sysemu/sysemu.h" 20 #include "sysemu/numa.h" 21 #include "hw/boards.h" 22 #include "sysemu/reset.h" 23 #include "hw/loader.h" 24 #include "elf.h" 25 #include "sysemu/device_tree.h" 26 #include "qemu/config-file.h" 27 #include "qemu/option.h" 28 #include "qemu/units.h" 29 30 /* Kernel boot protocol is specified in the kernel docs 31 * Documentation/arm/Booting and Documentation/arm64/booting.txt 32 * They have different preferred image load offsets from system RAM base. 33 */ 34 #define KERNEL_ARGS_ADDR 0x100 35 #define KERNEL_NOLOAD_ADDR 0x02000000 36 #define KERNEL_LOAD_ADDR 0x00010000 37 #define KERNEL64_LOAD_ADDR 0x00080000 38 39 #define ARM64_TEXT_OFFSET_OFFSET 8 40 #define ARM64_MAGIC_OFFSET 56 41 42 #define BOOTLOADER_MAX_SIZE (4 * KiB) 43 44 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 45 const struct arm_boot_info *info) 46 { 47 /* Return the address space to use for bootloader reads and writes. 48 * We prefer the secure address space if the CPU has it and we're 49 * going to boot the guest into it. 50 */ 51 int asidx; 52 CPUState *cs = CPU(cpu); 53 54 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 55 asidx = ARMASIdx_S; 56 } else { 57 asidx = ARMASIdx_NS; 58 } 59 60 return cpu_get_address_space(cs, asidx); 61 } 62 63 typedef enum { 64 FIXUP_NONE = 0, /* do nothing */ 65 FIXUP_TERMINATOR, /* end of insns */ 66 FIXUP_BOARDID, /* overwrite with board ID number */ 67 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 68 FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */ 69 FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */ 70 FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */ 71 FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */ 72 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 73 FIXUP_BOOTREG, /* overwrite with boot register address */ 74 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 75 FIXUP_MAX, 76 } FixupType; 77 78 typedef struct ARMInsnFixup { 79 uint32_t insn; 80 FixupType fixup; 81 } ARMInsnFixup; 82 83 static const ARMInsnFixup bootloader_aarch64[] = { 84 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 85 { 0xaa1f03e1 }, /* mov x1, xzr */ 86 { 0xaa1f03e2 }, /* mov x2, xzr */ 87 { 0xaa1f03e3 }, /* mov x3, xzr */ 88 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 89 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 90 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ 91 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ 92 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ 93 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ 94 { 0, FIXUP_TERMINATOR } 95 }; 96 97 /* A very small bootloader: call the board-setup code (if needed), 98 * set r0-r2, then jump to the kernel. 99 * If we're not calling boot setup code then we don't copy across 100 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 101 */ 102 103 static const ARMInsnFixup bootloader[] = { 104 { 0xe28fe004 }, /* add lr, pc, #4 */ 105 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 106 { 0, FIXUP_BOARD_SETUP }, 107 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 108 { 0xe3a00000 }, /* mov r0, #0 */ 109 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 110 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 111 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 112 { 0, FIXUP_BOARDID }, 113 { 0, FIXUP_ARGPTR_LO }, 114 { 0, FIXUP_ENTRYPOINT_LO }, 115 { 0, FIXUP_TERMINATOR } 116 }; 117 118 /* Handling for secondary CPU boot in a multicore system. 119 * Unlike the uniprocessor/primary CPU boot, this is platform 120 * dependent. The default code here is based on the secondary 121 * CPU boot protocol used on realview/vexpress boards, with 122 * some parameterisation to increase its flexibility. 123 * QEMU platform models for which this code is not appropriate 124 * should override write_secondary_boot and secondary_cpu_reset_hook 125 * instead. 126 * 127 * This code enables the interrupt controllers for the secondary 128 * CPUs and then puts all the secondary CPUs into a loop waiting 129 * for an interprocessor interrupt and polling a configurable 130 * location for the kernel secondary CPU entry point. 131 */ 132 #define DSB_INSN 0xf57ff04f 133 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 134 135 static const ARMInsnFixup smpboot[] = { 136 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 137 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 138 { 0xe3a01001 }, /* mov r1, #1 */ 139 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 140 { 0xe3a010ff }, /* mov r1, #0xff */ 141 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 142 { 0, FIXUP_DSB }, /* dsb */ 143 { 0xe320f003 }, /* wfi */ 144 { 0xe5901000 }, /* ldr r1, [r0] */ 145 { 0xe1110001 }, /* tst r1, r1 */ 146 { 0x0afffffb }, /* beq <wfi> */ 147 { 0xe12fff11 }, /* bx r1 */ 148 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 149 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 150 { 0, FIXUP_TERMINATOR } 151 }; 152 153 static void write_bootloader(const char *name, hwaddr addr, 154 const ARMInsnFixup *insns, uint32_t *fixupcontext, 155 AddressSpace *as) 156 { 157 /* Fix up the specified bootloader fragment and write it into 158 * guest memory using rom_add_blob_fixed(). fixupcontext is 159 * an array giving the values to write in for the fixup types 160 * which write a value into the code array. 161 */ 162 int i, len; 163 uint32_t *code; 164 165 len = 0; 166 while (insns[len].fixup != FIXUP_TERMINATOR) { 167 len++; 168 } 169 170 code = g_new0(uint32_t, len); 171 172 for (i = 0; i < len; i++) { 173 uint32_t insn = insns[i].insn; 174 FixupType fixup = insns[i].fixup; 175 176 switch (fixup) { 177 case FIXUP_NONE: 178 break; 179 case FIXUP_BOARDID: 180 case FIXUP_BOARD_SETUP: 181 case FIXUP_ARGPTR_LO: 182 case FIXUP_ARGPTR_HI: 183 case FIXUP_ENTRYPOINT_LO: 184 case FIXUP_ENTRYPOINT_HI: 185 case FIXUP_GIC_CPU_IF: 186 case FIXUP_BOOTREG: 187 case FIXUP_DSB: 188 insn = fixupcontext[fixup]; 189 break; 190 default: 191 abort(); 192 } 193 code[i] = tswap32(insn); 194 } 195 196 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 197 198 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 199 200 g_free(code); 201 } 202 203 static void default_write_secondary(ARMCPU *cpu, 204 const struct arm_boot_info *info) 205 { 206 uint32_t fixupcontext[FIXUP_MAX]; 207 AddressSpace *as = arm_boot_address_space(cpu, info); 208 209 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 210 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 211 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 212 fixupcontext[FIXUP_DSB] = DSB_INSN; 213 } else { 214 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 215 } 216 217 write_bootloader("smpboot", info->smp_loader_start, 218 smpboot, fixupcontext, as); 219 } 220 221 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 222 const struct arm_boot_info *info, 223 hwaddr mvbar_addr) 224 { 225 AddressSpace *as = arm_boot_address_space(cpu, info); 226 int n; 227 uint32_t mvbar_blob[] = { 228 /* mvbar_addr: secure monitor vectors 229 * Default unimplemented and unused vectors to spin. Makes it 230 * easier to debug (as opposed to the CPU running away). 231 */ 232 0xeafffffe, /* (spin) */ 233 0xeafffffe, /* (spin) */ 234 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 235 0xeafffffe, /* (spin) */ 236 0xeafffffe, /* (spin) */ 237 0xeafffffe, /* (spin) */ 238 0xeafffffe, /* (spin) */ 239 0xeafffffe, /* (spin) */ 240 }; 241 uint32_t board_setup_blob[] = { 242 /* board setup addr */ 243 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ 244 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ 245 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ 246 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 247 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 248 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 249 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 250 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 251 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 252 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 253 0xe1a0f001, /* mov pc, r1 ;return */ 254 }; 255 256 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 257 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 258 259 /* check that these blobs don't overlap */ 260 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 261 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 262 263 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 264 mvbar_blob[n] = tswap32(mvbar_blob[n]); 265 } 266 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 267 mvbar_addr, as); 268 269 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 270 board_setup_blob[n] = tswap32(board_setup_blob[n]); 271 } 272 rom_add_blob_fixed_as("board-setup", board_setup_blob, 273 sizeof(board_setup_blob), info->board_setup_addr, as); 274 } 275 276 static void default_reset_secondary(ARMCPU *cpu, 277 const struct arm_boot_info *info) 278 { 279 AddressSpace *as = arm_boot_address_space(cpu, info); 280 CPUState *cs = CPU(cpu); 281 282 address_space_stl_notdirty(as, info->smp_bootreg_addr, 283 0, MEMTXATTRS_UNSPECIFIED, NULL); 284 cpu_set_pc(cs, info->smp_loader_start); 285 } 286 287 static inline bool have_dtb(const struct arm_boot_info *info) 288 { 289 return info->dtb_filename || info->get_dtb; 290 } 291 292 #define WRITE_WORD(p, value) do { \ 293 address_space_stl_notdirty(as, p, value, \ 294 MEMTXATTRS_UNSPECIFIED, NULL); \ 295 p += 4; \ 296 } while (0) 297 298 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 299 { 300 int initrd_size = info->initrd_size; 301 hwaddr base = info->loader_start; 302 hwaddr p; 303 304 p = base + KERNEL_ARGS_ADDR; 305 /* ATAG_CORE */ 306 WRITE_WORD(p, 5); 307 WRITE_WORD(p, 0x54410001); 308 WRITE_WORD(p, 1); 309 WRITE_WORD(p, 0x1000); 310 WRITE_WORD(p, 0); 311 /* ATAG_MEM */ 312 /* TODO: handle multiple chips on one ATAG list */ 313 WRITE_WORD(p, 4); 314 WRITE_WORD(p, 0x54410002); 315 WRITE_WORD(p, info->ram_size); 316 WRITE_WORD(p, info->loader_start); 317 if (initrd_size) { 318 /* ATAG_INITRD2 */ 319 WRITE_WORD(p, 4); 320 WRITE_WORD(p, 0x54420005); 321 WRITE_WORD(p, info->initrd_start); 322 WRITE_WORD(p, initrd_size); 323 } 324 if (info->kernel_cmdline && *info->kernel_cmdline) { 325 /* ATAG_CMDLINE */ 326 int cmdline_size; 327 328 cmdline_size = strlen(info->kernel_cmdline); 329 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 330 info->kernel_cmdline, cmdline_size + 1); 331 cmdline_size = (cmdline_size >> 2) + 1; 332 WRITE_WORD(p, cmdline_size + 2); 333 WRITE_WORD(p, 0x54410009); 334 p += cmdline_size * 4; 335 } 336 if (info->atag_board) { 337 /* ATAG_BOARD */ 338 int atag_board_len; 339 uint8_t atag_board_buf[0x1000]; 340 341 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 342 WRITE_WORD(p, (atag_board_len + 8) >> 2); 343 WRITE_WORD(p, 0x414f4d50); 344 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 345 atag_board_buf, atag_board_len); 346 p += atag_board_len; 347 } 348 /* ATAG_END */ 349 WRITE_WORD(p, 0); 350 WRITE_WORD(p, 0); 351 } 352 353 static void set_kernel_args_old(const struct arm_boot_info *info, 354 AddressSpace *as) 355 { 356 hwaddr p; 357 const char *s; 358 int initrd_size = info->initrd_size; 359 hwaddr base = info->loader_start; 360 361 /* see linux/include/asm-arm/setup.h */ 362 p = base + KERNEL_ARGS_ADDR; 363 /* page_size */ 364 WRITE_WORD(p, 4096); 365 /* nr_pages */ 366 WRITE_WORD(p, info->ram_size / 4096); 367 /* ramdisk_size */ 368 WRITE_WORD(p, 0); 369 #define FLAG_READONLY 1 370 #define FLAG_RDLOAD 4 371 #define FLAG_RDPROMPT 8 372 /* flags */ 373 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 374 /* rootdev */ 375 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 376 /* video_num_cols */ 377 WRITE_WORD(p, 0); 378 /* video_num_rows */ 379 WRITE_WORD(p, 0); 380 /* video_x */ 381 WRITE_WORD(p, 0); 382 /* video_y */ 383 WRITE_WORD(p, 0); 384 /* memc_control_reg */ 385 WRITE_WORD(p, 0); 386 /* unsigned char sounddefault */ 387 /* unsigned char adfsdrives */ 388 /* unsigned char bytes_per_char_h */ 389 /* unsigned char bytes_per_char_v */ 390 WRITE_WORD(p, 0); 391 /* pages_in_bank[4] */ 392 WRITE_WORD(p, 0); 393 WRITE_WORD(p, 0); 394 WRITE_WORD(p, 0); 395 WRITE_WORD(p, 0); 396 /* pages_in_vram */ 397 WRITE_WORD(p, 0); 398 /* initrd_start */ 399 if (initrd_size) { 400 WRITE_WORD(p, info->initrd_start); 401 } else { 402 WRITE_WORD(p, 0); 403 } 404 /* initrd_size */ 405 WRITE_WORD(p, initrd_size); 406 /* rd_start */ 407 WRITE_WORD(p, 0); 408 /* system_rev */ 409 WRITE_WORD(p, 0); 410 /* system_serial_low */ 411 WRITE_WORD(p, 0); 412 /* system_serial_high */ 413 WRITE_WORD(p, 0); 414 /* mem_fclk_21285 */ 415 WRITE_WORD(p, 0); 416 /* zero unused fields */ 417 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 418 WRITE_WORD(p, 0); 419 } 420 s = info->kernel_cmdline; 421 if (s) { 422 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1); 423 } else { 424 WRITE_WORD(p, 0); 425 } 426 } 427 428 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, 429 uint32_t scells, hwaddr mem_len, 430 int numa_node_id) 431 { 432 char *nodename; 433 int ret; 434 435 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 436 qemu_fdt_add_subnode(fdt, nodename); 437 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 438 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base, 439 scells, mem_len); 440 if (ret < 0) { 441 goto out; 442 } 443 444 /* only set the NUMA ID if it is specified */ 445 if (numa_node_id >= 0) { 446 ret = qemu_fdt_setprop_cell(fdt, nodename, 447 "numa-node-id", numa_node_id); 448 } 449 out: 450 g_free(nodename); 451 return ret; 452 } 453 454 static void fdt_add_psci_node(void *fdt) 455 { 456 uint32_t cpu_suspend_fn; 457 uint32_t cpu_off_fn; 458 uint32_t cpu_on_fn; 459 uint32_t migrate_fn; 460 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 461 const char *psci_method; 462 int64_t psci_conduit; 463 int rc; 464 465 psci_conduit = object_property_get_int(OBJECT(armcpu), 466 "psci-conduit", 467 &error_abort); 468 switch (psci_conduit) { 469 case QEMU_PSCI_CONDUIT_DISABLED: 470 return; 471 case QEMU_PSCI_CONDUIT_HVC: 472 psci_method = "hvc"; 473 break; 474 case QEMU_PSCI_CONDUIT_SMC: 475 psci_method = "smc"; 476 break; 477 default: 478 g_assert_not_reached(); 479 } 480 481 /* 482 * A pre-existing /psci node might specify function ID values 483 * that don't match QEMU's PSCI implementation. Delete the whole 484 * node and put our own in instead. 485 */ 486 rc = fdt_path_offset(fdt, "/psci"); 487 if (rc >= 0) { 488 qemu_fdt_nop_node(fdt, "/psci"); 489 } 490 491 qemu_fdt_add_subnode(fdt, "/psci"); 492 if (armcpu->psci_version >= QEMU_PSCI_VERSION_0_2) { 493 if (armcpu->psci_version < QEMU_PSCI_VERSION_1_0) { 494 const char comp[] = "arm,psci-0.2\0arm,psci"; 495 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 496 } else { 497 const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci"; 498 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 499 } 500 501 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 502 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 503 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 504 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 505 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 506 } else { 507 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 508 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 509 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 510 } 511 } else { 512 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 513 514 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 515 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 516 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 517 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 518 } 519 520 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 521 * to the instruction that should be used to invoke PSCI functions. 522 * However, the device tree binding uses 'method' instead, so that is 523 * what we should use here. 524 */ 525 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 526 527 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 528 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 529 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 530 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 531 } 532 533 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 534 hwaddr addr_limit, AddressSpace *as, MachineState *ms) 535 { 536 void *fdt = NULL; 537 int size, rc, n = 0; 538 uint32_t acells, scells; 539 unsigned int i; 540 hwaddr mem_base, mem_len; 541 char **node_path; 542 Error *err = NULL; 543 544 if (binfo->dtb_filename) { 545 char *filename; 546 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 547 if (!filename) { 548 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 549 goto fail; 550 } 551 552 fdt = load_device_tree(filename, &size); 553 if (!fdt) { 554 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 555 g_free(filename); 556 goto fail; 557 } 558 g_free(filename); 559 } else { 560 fdt = binfo->get_dtb(binfo, &size); 561 if (!fdt) { 562 fprintf(stderr, "Board was unable to create a dtb blob\n"); 563 goto fail; 564 } 565 } 566 567 if (addr_limit > addr && size > (addr_limit - addr)) { 568 /* Installing the device tree blob at addr would exceed addr_limit. 569 * Whether this constitutes failure is up to the caller to decide, 570 * so just return 0 as size, i.e., no error. 571 */ 572 g_free(fdt); 573 return 0; 574 } 575 576 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 577 NULL, &error_fatal); 578 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 579 NULL, &error_fatal); 580 if (acells == 0 || scells == 0) { 581 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 582 goto fail; 583 } 584 585 if (scells < 2 && binfo->ram_size >= 4 * GiB) { 586 /* This is user error so deserves a friendlier error message 587 * than the failure of setprop_sized_cells would provide 588 */ 589 fprintf(stderr, "qemu: dtb file not compatible with " 590 "RAM size > 4GB\n"); 591 goto fail; 592 } 593 594 /* nop all root nodes matching /memory or /memory@unit-address */ 595 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 596 if (err) { 597 error_report_err(err); 598 goto fail; 599 } 600 while (node_path[n]) { 601 if (g_str_has_prefix(node_path[n], "/memory")) { 602 qemu_fdt_nop_node(fdt, node_path[n]); 603 } 604 n++; 605 } 606 g_strfreev(node_path); 607 608 /* 609 * We drop all the memory nodes which correspond to empty NUMA nodes 610 * from the device tree, because the Linux NUMA binding document 611 * states they should not be generated. Linux will get the NUMA node 612 * IDs of the empty NUMA nodes from the distance map if they are needed. 613 * This means QEMU users may be obliged to provide command lines which 614 * configure distance maps when the empty NUMA node IDs are needed and 615 * Linux's default distance map isn't sufficient. 616 */ 617 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) { 618 mem_base = binfo->loader_start; 619 for (i = 0; i < ms->numa_state->num_nodes; i++) { 620 mem_len = ms->numa_state->nodes[i].node_mem; 621 if (!mem_len) { 622 continue; 623 } 624 625 rc = fdt_add_memory_node(fdt, acells, mem_base, 626 scells, mem_len, i); 627 if (rc < 0) { 628 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 629 mem_base); 630 goto fail; 631 } 632 633 mem_base += mem_len; 634 } 635 } else { 636 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start, 637 scells, binfo->ram_size, -1); 638 if (rc < 0) { 639 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 640 binfo->loader_start); 641 goto fail; 642 } 643 } 644 645 rc = fdt_path_offset(fdt, "/chosen"); 646 if (rc < 0) { 647 qemu_fdt_add_subnode(fdt, "/chosen"); 648 } 649 650 if (ms->kernel_cmdline && *ms->kernel_cmdline) { 651 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 652 ms->kernel_cmdline); 653 if (rc < 0) { 654 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 655 goto fail; 656 } 657 } 658 659 if (binfo->initrd_size) { 660 rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start", 661 acells, binfo->initrd_start); 662 if (rc < 0) { 663 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 664 goto fail; 665 } 666 667 rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end", 668 acells, 669 binfo->initrd_start + 670 binfo->initrd_size); 671 if (rc < 0) { 672 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 673 goto fail; 674 } 675 } 676 677 fdt_add_psci_node(fdt); 678 679 if (binfo->modify_dtb) { 680 binfo->modify_dtb(binfo, fdt); 681 } 682 683 qemu_fdt_dumpdtb(fdt, size); 684 685 /* Put the DTB into the memory map as a ROM image: this will ensure 686 * the DTB is copied again upon reset, even if addr points into RAM. 687 */ 688 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 689 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 690 rom_ptr_for_as(as, addr, size)); 691 692 g_free(fdt); 693 694 return size; 695 696 fail: 697 g_free(fdt); 698 return -1; 699 } 700 701 static void do_cpu_reset(void *opaque) 702 { 703 ARMCPU *cpu = opaque; 704 CPUState *cs = CPU(cpu); 705 CPUARMState *env = &cpu->env; 706 const struct arm_boot_info *info = env->boot_info; 707 708 cpu_reset(cs); 709 if (info) { 710 if (!info->is_linux) { 711 int i; 712 /* Jump to the entry point. */ 713 uint64_t entry = info->entry; 714 715 switch (info->endianness) { 716 case ARM_ENDIANNESS_LE: 717 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 718 for (i = 1; i < 4; ++i) { 719 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 720 } 721 env->uncached_cpsr &= ~CPSR_E; 722 break; 723 case ARM_ENDIANNESS_BE8: 724 env->cp15.sctlr_el[1] |= SCTLR_E0E; 725 for (i = 1; i < 4; ++i) { 726 env->cp15.sctlr_el[i] |= SCTLR_EE; 727 } 728 env->uncached_cpsr |= CPSR_E; 729 break; 730 case ARM_ENDIANNESS_BE32: 731 env->cp15.sctlr_el[1] |= SCTLR_B; 732 break; 733 case ARM_ENDIANNESS_UNKNOWN: 734 break; /* Board's decision */ 735 default: 736 g_assert_not_reached(); 737 } 738 739 cpu_set_pc(cs, entry); 740 } else { 741 /* If we are booting Linux then we need to check whether we are 742 * booting into secure or non-secure state and adjust the state 743 * accordingly. Out of reset, ARM is defined to be in secure state 744 * (SCR.NS = 0), we change that here if non-secure boot has been 745 * requested. 746 */ 747 if (arm_feature(env, ARM_FEATURE_EL3)) { 748 /* AArch64 is defined to come out of reset into EL3 if enabled. 749 * If we are booting Linux then we need to adjust our EL as 750 * Linux expects us to be in EL2 or EL1. AArch32 resets into 751 * SVC, which Linux expects, so no privilege/exception level to 752 * adjust. 753 */ 754 if (env->aarch64) { 755 env->cp15.scr_el3 |= SCR_RW; 756 if (arm_feature(env, ARM_FEATURE_EL2)) { 757 env->cp15.hcr_el2 |= HCR_RW; 758 env->pstate = PSTATE_MODE_EL2h; 759 } else { 760 env->pstate = PSTATE_MODE_EL1h; 761 } 762 if (cpu_isar_feature(aa64_pauth, cpu)) { 763 env->cp15.scr_el3 |= SCR_API | SCR_APK; 764 } 765 if (cpu_isar_feature(aa64_mte, cpu)) { 766 env->cp15.scr_el3 |= SCR_ATA; 767 } 768 if (cpu_isar_feature(aa64_sve, cpu)) { 769 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; 770 env->vfp.zcr_el[3] = 0xf; 771 } 772 if (cpu_isar_feature(aa64_sme, cpu)) { 773 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; 774 env->cp15.scr_el3 |= SCR_ENTP2; 775 env->vfp.smcr_el[3] = 0xf; 776 } 777 if (cpu_isar_feature(aa64_hcx, cpu)) { 778 env->cp15.scr_el3 |= SCR_HXEN; 779 } 780 /* AArch64 kernels never boot in secure mode */ 781 assert(!info->secure_boot); 782 /* This hook is only supported for AArch32 currently: 783 * bootloader_aarch64[] will not call the hook, and 784 * the code above has already dropped us into EL2 or EL1. 785 */ 786 assert(!info->secure_board_setup); 787 } 788 789 if (arm_feature(env, ARM_FEATURE_EL2)) { 790 /* If we have EL2 then Linux expects the HVC insn to work */ 791 env->cp15.scr_el3 |= SCR_HCE; 792 } 793 794 /* Set to non-secure if not a secure boot */ 795 if (!info->secure_boot && 796 (cs != first_cpu || !info->secure_board_setup)) { 797 /* Linux expects non-secure state */ 798 env->cp15.scr_el3 |= SCR_NS; 799 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 800 env->cp15.nsacr |= 3 << 10; 801 } 802 } 803 804 if (!env->aarch64 && !info->secure_boot && 805 arm_feature(env, ARM_FEATURE_EL2)) { 806 /* 807 * This is an AArch32 boot not to Secure state, and 808 * we have Hyp mode available, so boot the kernel into 809 * Hyp mode. This is not how the CPU comes out of reset, 810 * so we need to manually put it there. 811 */ 812 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw); 813 } 814 815 if (cs == first_cpu) { 816 AddressSpace *as = arm_boot_address_space(cpu, info); 817 818 cpu_set_pc(cs, info->loader_start); 819 820 if (!have_dtb(info)) { 821 if (old_param) { 822 set_kernel_args_old(info, as); 823 } else { 824 set_kernel_args(info, as); 825 } 826 } 827 } else if (info->secondary_cpu_reset_hook) { 828 info->secondary_cpu_reset_hook(cpu, info); 829 } 830 } 831 832 if (tcg_enabled()) { 833 arm_rebuild_hflags(env); 834 } 835 } 836 } 837 838 static int do_arm_linux_init(Object *obj, void *opaque) 839 { 840 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 841 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 842 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 843 struct arm_boot_info *info = opaque; 844 845 if (albifc->arm_linux_init) { 846 albifc->arm_linux_init(albif, info->secure_boot); 847 } 848 } 849 return 0; 850 } 851 852 static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 853 uint64_t *lowaddr, uint64_t *highaddr, 854 int elf_machine, AddressSpace *as) 855 { 856 bool elf_is64; 857 union { 858 Elf32_Ehdr h32; 859 Elf64_Ehdr h64; 860 } elf_header; 861 int data_swab = 0; 862 bool big_endian; 863 ssize_t ret = -1; 864 Error *err = NULL; 865 866 867 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 868 if (err) { 869 error_free(err); 870 return ret; 871 } 872 873 if (elf_is64) { 874 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 875 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 876 : ARM_ENDIANNESS_LE; 877 } else { 878 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 879 if (big_endian) { 880 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 881 info->endianness = ARM_ENDIANNESS_BE8; 882 } else { 883 info->endianness = ARM_ENDIANNESS_BE32; 884 /* In BE32, the CPU has a different view of the per-byte 885 * address map than the rest of the system. BE32 ELF files 886 * are organised such that they can be programmed through 887 * the CPU's per-word byte-reversed view of the world. QEMU 888 * however loads ELF files independently of the CPU. So 889 * tell the ELF loader to byte reverse the data for us. 890 */ 891 data_swab = 2; 892 } 893 } else { 894 info->endianness = ARM_ENDIANNESS_LE; 895 } 896 } 897 898 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL, 899 pentry, lowaddr, highaddr, NULL, big_endian, elf_machine, 900 1, data_swab, as); 901 if (ret <= 0) { 902 /* The header loaded but the image didn't */ 903 exit(1); 904 } 905 906 return ret; 907 } 908 909 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 910 hwaddr *entry, AddressSpace *as) 911 { 912 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 913 uint64_t kernel_size = 0; 914 uint8_t *buffer; 915 int size; 916 917 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 918 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 919 &buffer); 920 921 if (size < 0) { 922 gsize len; 923 924 /* Load as raw file otherwise */ 925 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 926 return -1; 927 } 928 size = len; 929 } 930 931 /* check the arm64 magic header value -- very old kernels may not have it */ 932 if (size > ARM64_MAGIC_OFFSET + 4 && 933 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 934 uint64_t hdrvals[2]; 935 936 /* The arm64 Image header has text_offset and image_size fields at 8 and 937 * 16 bytes into the Image header, respectively. The text_offset field 938 * is only valid if the image_size is non-zero. 939 */ 940 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 941 942 kernel_size = le64_to_cpu(hdrvals[1]); 943 944 if (kernel_size != 0) { 945 kernel_load_offset = le64_to_cpu(hdrvals[0]); 946 947 /* 948 * We write our startup "bootloader" at the very bottom of RAM, 949 * so that bit can't be used for the image. Luckily the Image 950 * format specification is that the image requests only an offset 951 * from a 2MB boundary, not an absolute load address. So if the 952 * image requests an offset that might mean it overlaps with the 953 * bootloader, we can just load it starting at 2MB+offset rather 954 * than 0MB + offset. 955 */ 956 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 957 kernel_load_offset += 2 * MiB; 958 } 959 } 960 } 961 962 /* 963 * Kernels before v3.17 don't populate the image_size field, and 964 * raw images have no header. For those our best guess at the size 965 * is the size of the Image file itself. 966 */ 967 if (kernel_size == 0) { 968 kernel_size = size; 969 } 970 971 *entry = mem_base + kernel_load_offset; 972 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 973 974 g_free(buffer); 975 976 return kernel_size; 977 } 978 979 static void arm_setup_direct_kernel_boot(ARMCPU *cpu, 980 struct arm_boot_info *info) 981 { 982 /* Set up for a direct boot of a kernel image file. */ 983 CPUState *cs; 984 AddressSpace *as = arm_boot_address_space(cpu, info); 985 ssize_t kernel_size; 986 int initrd_size; 987 int is_linux = 0; 988 uint64_t elf_entry; 989 /* Addresses of first byte used and first byte not used by the image */ 990 uint64_t image_low_addr = 0, image_high_addr = 0; 991 int elf_machine; 992 hwaddr entry; 993 static const ARMInsnFixup *primary_loader; 994 uint64_t ram_end = info->loader_start + info->ram_size; 995 996 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 997 primary_loader = bootloader_aarch64; 998 elf_machine = EM_AARCH64; 999 } else { 1000 primary_loader = bootloader; 1001 if (!info->write_board_setup) { 1002 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 1003 } 1004 elf_machine = EM_ARM; 1005 } 1006 1007 /* Assume that raw images are linux kernels, and ELF images are not. */ 1008 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr, 1009 &image_high_addr, elf_machine, as); 1010 if (kernel_size > 0 && have_dtb(info)) { 1011 /* 1012 * If there is still some room left at the base of RAM, try and put 1013 * the DTB there like we do for images loaded with -bios or -pflash. 1014 */ 1015 if (image_low_addr > info->loader_start 1016 || image_high_addr < info->loader_start) { 1017 /* 1018 * Set image_low_addr as address limit for arm_load_dtb if it may be 1019 * pointing into RAM, otherwise pass '0' (no limit) 1020 */ 1021 if (image_low_addr < info->loader_start) { 1022 image_low_addr = 0; 1023 } 1024 info->dtb_start = info->loader_start; 1025 info->dtb_limit = image_low_addr; 1026 } 1027 } 1028 entry = elf_entry; 1029 if (kernel_size < 0) { 1030 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; 1031 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, 1032 &is_linux, NULL, NULL, as); 1033 if (kernel_size >= 0) { 1034 image_low_addr = loadaddr; 1035 image_high_addr = image_low_addr + kernel_size; 1036 } 1037 } 1038 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1039 kernel_size = load_aarch64_image(info->kernel_filename, 1040 info->loader_start, &entry, as); 1041 is_linux = 1; 1042 if (kernel_size >= 0) { 1043 image_low_addr = entry; 1044 image_high_addr = image_low_addr + kernel_size; 1045 } 1046 } else if (kernel_size < 0) { 1047 /* 32-bit ARM */ 1048 entry = info->loader_start + KERNEL_LOAD_ADDR; 1049 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1050 ram_end - KERNEL_LOAD_ADDR, as); 1051 is_linux = 1; 1052 if (kernel_size >= 0) { 1053 image_low_addr = entry; 1054 image_high_addr = image_low_addr + kernel_size; 1055 } 1056 } 1057 if (kernel_size < 0) { 1058 error_report("could not load kernel '%s'", info->kernel_filename); 1059 exit(1); 1060 } 1061 1062 if (kernel_size > info->ram_size) { 1063 error_report("kernel '%s' is too large to fit in RAM " 1064 "(kernel size %zd, RAM size %" PRId64 ")", 1065 info->kernel_filename, kernel_size, info->ram_size); 1066 exit(1); 1067 } 1068 1069 info->entry = entry; 1070 1071 /* 1072 * We want to put the initrd far enough into RAM that when the 1073 * kernel is uncompressed it will not clobber the initrd. However 1074 * on boards without much RAM we must ensure that we still leave 1075 * enough room for a decent sized initrd, and on boards with large 1076 * amounts of RAM we must avoid the initrd being so far up in RAM 1077 * that it is outside lowmem and inaccessible to the kernel. 1078 * So for boards with less than 256MB of RAM we put the initrd 1079 * halfway into RAM, and for boards with 256MB of RAM or more we put 1080 * the initrd at 128MB. 1081 * We also refuse to put the initrd somewhere that will definitely 1082 * overlay the kernel we just loaded, though for kernel formats which 1083 * don't tell us their exact size (eg self-decompressing 32-bit kernels) 1084 * we might still make a bad choice here. 1085 */ 1086 info->initrd_start = info->loader_start + 1087 MIN(info->ram_size / 2, 128 * MiB); 1088 if (image_high_addr) { 1089 info->initrd_start = MAX(info->initrd_start, image_high_addr); 1090 } 1091 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); 1092 1093 if (is_linux) { 1094 uint32_t fixupcontext[FIXUP_MAX]; 1095 1096 if (info->initrd_filename) { 1097 1098 if (info->initrd_start >= ram_end) { 1099 error_report("not enough space after kernel to load initrd"); 1100 exit(1); 1101 } 1102 1103 initrd_size = load_ramdisk_as(info->initrd_filename, 1104 info->initrd_start, 1105 ram_end - info->initrd_start, as); 1106 if (initrd_size < 0) { 1107 initrd_size = load_image_targphys_as(info->initrd_filename, 1108 info->initrd_start, 1109 ram_end - 1110 info->initrd_start, 1111 as); 1112 } 1113 if (initrd_size < 0) { 1114 error_report("could not load initrd '%s'", 1115 info->initrd_filename); 1116 exit(1); 1117 } 1118 if (info->initrd_start + initrd_size > ram_end) { 1119 error_report("could not load initrd '%s': " 1120 "too big to fit into RAM after the kernel", 1121 info->initrd_filename); 1122 exit(1); 1123 } 1124 } else { 1125 initrd_size = 0; 1126 } 1127 info->initrd_size = initrd_size; 1128 1129 fixupcontext[FIXUP_BOARDID] = info->board_id; 1130 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1131 1132 /* 1133 * for device tree boot, we pass the DTB directly in r2. Otherwise 1134 * we point to the kernel args. 1135 */ 1136 if (have_dtb(info)) { 1137 hwaddr align; 1138 1139 if (elf_machine == EM_AARCH64) { 1140 /* 1141 * Some AArch64 kernels on early bootup map the fdt region as 1142 * 1143 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1144 * 1145 * Let's play safe and prealign it to 2MB to give us some space. 1146 */ 1147 align = 2 * MiB; 1148 } else { 1149 /* 1150 * Some 32bit kernels will trash anything in the 4K page the 1151 * initrd ends in, so make sure the DTB isn't caught up in that. 1152 */ 1153 align = 4 * KiB; 1154 } 1155 1156 /* Place the DTB after the initrd in memory with alignment. */ 1157 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1158 align); 1159 if (info->dtb_start >= ram_end) { 1160 error_report("Not enough space for DTB after kernel/initrd"); 1161 exit(1); 1162 } 1163 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; 1164 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; 1165 } else { 1166 fixupcontext[FIXUP_ARGPTR_LO] = 1167 info->loader_start + KERNEL_ARGS_ADDR; 1168 fixupcontext[FIXUP_ARGPTR_HI] = 1169 (info->loader_start + KERNEL_ARGS_ADDR) >> 32; 1170 if (info->ram_size >= 4 * GiB) { 1171 error_report("RAM size must be less than 4GB to boot" 1172 " Linux kernel using ATAGS (try passing a device tree" 1173 " using -dtb)"); 1174 exit(1); 1175 } 1176 } 1177 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; 1178 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; 1179 1180 write_bootloader("bootloader", info->loader_start, 1181 primary_loader, fixupcontext, as); 1182 1183 if (info->write_board_setup) { 1184 info->write_board_setup(cpu, info); 1185 } 1186 1187 /* 1188 * Notify devices which need to fake up firmware initialization 1189 * that we're doing a direct kernel boot. 1190 */ 1191 object_child_foreach_recursive(object_get_root(), 1192 do_arm_linux_init, info); 1193 } 1194 info->is_linux = is_linux; 1195 1196 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1197 ARM_CPU(cs)->env.boot_info = info; 1198 } 1199 } 1200 1201 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) 1202 { 1203 /* Set up for booting firmware (which might load a kernel via fw_cfg) */ 1204 1205 if (have_dtb(info)) { 1206 /* 1207 * If we have a device tree blob, but no kernel to supply it to (or 1208 * the kernel is supposed to be loaded by the bootloader), copy the 1209 * DTB to the base of RAM for the bootloader to pick up. 1210 */ 1211 info->dtb_start = info->loader_start; 1212 } 1213 1214 if (info->kernel_filename) { 1215 FWCfgState *fw_cfg; 1216 bool try_decompressing_kernel; 1217 1218 fw_cfg = fw_cfg_find(); 1219 1220 if (!fw_cfg) { 1221 error_report("This machine type does not support loading both " 1222 "a guest firmware/BIOS image and a guest kernel at " 1223 "the same time. You should change your QEMU command " 1224 "line to specify one or the other, but not both."); 1225 exit(1); 1226 } 1227 1228 try_decompressing_kernel = arm_feature(&cpu->env, 1229 ARM_FEATURE_AARCH64); 1230 1231 /* 1232 * Expose the kernel, the command line, and the initrd in fw_cfg. 1233 * We don't process them here at all, it's all left to the 1234 * firmware. 1235 */ 1236 load_image_to_fw_cfg(fw_cfg, 1237 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1238 info->kernel_filename, 1239 try_decompressing_kernel); 1240 load_image_to_fw_cfg(fw_cfg, 1241 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1242 info->initrd_filename, false); 1243 1244 if (info->kernel_cmdline) { 1245 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1246 strlen(info->kernel_cmdline) + 1); 1247 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1248 info->kernel_cmdline); 1249 } 1250 } 1251 1252 /* 1253 * We will start from address 0 (typically a boot ROM image) in the 1254 * same way as hardware. Leave env->boot_info NULL, so that 1255 * do_cpu_reset() knows it does not need to alter the PC on reset. 1256 */ 1257 } 1258 1259 void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) 1260 { 1261 CPUState *cs; 1262 AddressSpace *as = arm_boot_address_space(cpu, info); 1263 int boot_el; 1264 CPUARMState *env = &cpu->env; 1265 int nb_cpus = 0; 1266 1267 /* 1268 * CPU objects (unlike devices) are not automatically reset on system 1269 * reset, so we must always register a handler to do so. If we're 1270 * actually loading a kernel, the handler is also responsible for 1271 * arranging that we start it correctly. 1272 */ 1273 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1274 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1275 nb_cpus++; 1276 } 1277 1278 /* 1279 * The board code is not supposed to set secure_board_setup unless 1280 * running its code in secure mode is actually possible, and KVM 1281 * doesn't support secure. 1282 */ 1283 assert(!(info->secure_board_setup && kvm_enabled())); 1284 info->kernel_filename = ms->kernel_filename; 1285 info->kernel_cmdline = ms->kernel_cmdline; 1286 info->initrd_filename = ms->initrd_filename; 1287 info->dtb_filename = ms->dtb; 1288 info->dtb_limit = 0; 1289 1290 /* Load the kernel. */ 1291 if (!info->kernel_filename || info->firmware_loaded) { 1292 arm_setup_firmware_boot(cpu, info); 1293 } else { 1294 arm_setup_direct_kernel_boot(cpu, info); 1295 } 1296 1297 /* 1298 * Disable the PSCI conduit if it is set up to target the same 1299 * or a lower EL than the one we're going to start the guest code in. 1300 * This logic needs to agree with the code in do_cpu_reset() which 1301 * decides whether we're going to boot the guest in the highest 1302 * supported exception level or in a lower one. 1303 */ 1304 1305 /* 1306 * If PSCI is enabled, then SMC calls all go to the PSCI handler and 1307 * are never emulated to trap into guest code. It therefore does not 1308 * make sense for the board to have a setup code fragment that runs 1309 * in Secure, because this will probably need to itself issue an SMC of some 1310 * kind as part of its operation. 1311 */ 1312 assert(info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED || 1313 !info->secure_board_setup); 1314 1315 /* Boot into highest supported EL ... */ 1316 if (arm_feature(env, ARM_FEATURE_EL3)) { 1317 boot_el = 3; 1318 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 1319 boot_el = 2; 1320 } else { 1321 boot_el = 1; 1322 } 1323 /* ...except that if we're booting Linux we adjust the EL we boot into */ 1324 if (info->is_linux && !info->secure_boot) { 1325 boot_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; 1326 } 1327 1328 if ((info->psci_conduit == QEMU_PSCI_CONDUIT_HVC && boot_el >= 2) || 1329 (info->psci_conduit == QEMU_PSCI_CONDUIT_SMC && boot_el == 3)) { 1330 info->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1331 } 1332 1333 if (info->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1334 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1335 Object *cpuobj = OBJECT(cs); 1336 1337 object_property_set_int(cpuobj, "psci-conduit", info->psci_conduit, 1338 &error_abort); 1339 /* 1340 * Secondary CPUs start in PSCI powered-down state. Like the 1341 * code in do_cpu_reset(), we assume first_cpu is the primary 1342 * CPU. 1343 */ 1344 if (cs != first_cpu) { 1345 object_property_set_bool(cpuobj, "start-powered-off", true, 1346 &error_abort); 1347 } 1348 } 1349 } 1350 1351 if (info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED && 1352 info->is_linux && nb_cpus > 1) { 1353 /* 1354 * We're booting Linux but not using PSCI, so for SMP we need 1355 * to write a custom secondary CPU boot loader stub, and arrange 1356 * for the secondary CPU reset to make the accompanying initialization. 1357 */ 1358 if (!info->secondary_cpu_reset_hook) { 1359 info->secondary_cpu_reset_hook = default_reset_secondary; 1360 } 1361 if (!info->write_secondary_boot) { 1362 info->write_secondary_boot = default_write_secondary; 1363 } 1364 info->write_secondary_boot(cpu, info); 1365 } else { 1366 /* 1367 * No secondary boot stub; don't use the reset hook that would 1368 * have set the CPU up to call it 1369 */ 1370 info->write_secondary_boot = NULL; 1371 info->secondary_cpu_reset_hook = NULL; 1372 } 1373 1374 /* 1375 * arm_load_dtb() may add a PSCI node so it must be called after we have 1376 * decided whether to enable PSCI and set the psci-conduit CPU properties. 1377 */ 1378 if (!info->skip_dtb_autoload && have_dtb(info)) { 1379 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1380 exit(1); 1381 } 1382 } 1383 } 1384 1385 static const TypeInfo arm_linux_boot_if_info = { 1386 .name = TYPE_ARM_LINUX_BOOT_IF, 1387 .parent = TYPE_INTERFACE, 1388 .class_size = sizeof(ARMLinuxBootIfClass), 1389 }; 1390 1391 static void arm_linux_boot_register_types(void) 1392 { 1393 type_register_static(&arm_linux_boot_if_info); 1394 } 1395 1396 type_init(arm_linux_boot_register_types) 1397