1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/error-report.h" 12 #include "qapi/error.h" 13 #include <libfdt.h> 14 #include "hw/hw.h" 15 #include "hw/arm/arm.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "sysemu/kvm.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/numa.h" 20 #include "hw/boards.h" 21 #include "hw/loader.h" 22 #include "elf.h" 23 #include "sysemu/device_tree.h" 24 #include "qemu/config-file.h" 25 #include "qemu/option.h" 26 #include "exec/address-spaces.h" 27 #include "qemu/units.h" 28 29 /* Kernel boot protocol is specified in the kernel docs 30 * Documentation/arm/Booting and Documentation/arm64/booting.txt 31 * They have different preferred image load offsets from system RAM base. 32 */ 33 #define KERNEL_ARGS_ADDR 0x100 34 #define KERNEL_LOAD_ADDR 0x00010000 35 #define KERNEL64_LOAD_ADDR 0x00080000 36 37 #define ARM64_TEXT_OFFSET_OFFSET 8 38 #define ARM64_MAGIC_OFFSET 56 39 40 #define BOOTLOADER_MAX_SIZE (4 * KiB) 41 42 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 43 const struct arm_boot_info *info) 44 { 45 /* Return the address space to use for bootloader reads and writes. 46 * We prefer the secure address space if the CPU has it and we're 47 * going to boot the guest into it. 48 */ 49 int asidx; 50 CPUState *cs = CPU(cpu); 51 52 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 53 asidx = ARMASIdx_S; 54 } else { 55 asidx = ARMASIdx_NS; 56 } 57 58 return cpu_get_address_space(cs, asidx); 59 } 60 61 typedef enum { 62 FIXUP_NONE = 0, /* do nothing */ 63 FIXUP_TERMINATOR, /* end of insns */ 64 FIXUP_BOARDID, /* overwrite with board ID number */ 65 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 66 FIXUP_ARGPTR, /* overwrite with pointer to kernel args */ 67 FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */ 68 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 69 FIXUP_BOOTREG, /* overwrite with boot register address */ 70 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 71 FIXUP_MAX, 72 } FixupType; 73 74 typedef struct ARMInsnFixup { 75 uint32_t insn; 76 FixupType fixup; 77 } ARMInsnFixup; 78 79 static const ARMInsnFixup bootloader_aarch64[] = { 80 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 81 { 0xaa1f03e1 }, /* mov x1, xzr */ 82 { 0xaa1f03e2 }, /* mov x2, xzr */ 83 { 0xaa1f03e3 }, /* mov x3, xzr */ 84 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 85 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 86 { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */ 87 { 0 }, /* .word @DTB Higher 32-bits */ 88 { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */ 89 { 0 }, /* .word @Kernel Entry Higher 32-bits */ 90 { 0, FIXUP_TERMINATOR } 91 }; 92 93 /* A very small bootloader: call the board-setup code (if needed), 94 * set r0-r2, then jump to the kernel. 95 * If we're not calling boot setup code then we don't copy across 96 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 97 */ 98 99 static const ARMInsnFixup bootloader[] = { 100 { 0xe28fe004 }, /* add lr, pc, #4 */ 101 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 102 { 0, FIXUP_BOARD_SETUP }, 103 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 104 { 0xe3a00000 }, /* mov r0, #0 */ 105 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 106 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 107 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 108 { 0, FIXUP_BOARDID }, 109 { 0, FIXUP_ARGPTR }, 110 { 0, FIXUP_ENTRYPOINT }, 111 { 0, FIXUP_TERMINATOR } 112 }; 113 114 /* Handling for secondary CPU boot in a multicore system. 115 * Unlike the uniprocessor/primary CPU boot, this is platform 116 * dependent. The default code here is based on the secondary 117 * CPU boot protocol used on realview/vexpress boards, with 118 * some parameterisation to increase its flexibility. 119 * QEMU platform models for which this code is not appropriate 120 * should override write_secondary_boot and secondary_cpu_reset_hook 121 * instead. 122 * 123 * This code enables the interrupt controllers for the secondary 124 * CPUs and then puts all the secondary CPUs into a loop waiting 125 * for an interprocessor interrupt and polling a configurable 126 * location for the kernel secondary CPU entry point. 127 */ 128 #define DSB_INSN 0xf57ff04f 129 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 130 131 static const ARMInsnFixup smpboot[] = { 132 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 133 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 134 { 0xe3a01001 }, /* mov r1, #1 */ 135 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 136 { 0xe3a010ff }, /* mov r1, #0xff */ 137 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 138 { 0, FIXUP_DSB }, /* dsb */ 139 { 0xe320f003 }, /* wfi */ 140 { 0xe5901000 }, /* ldr r1, [r0] */ 141 { 0xe1110001 }, /* tst r1, r1 */ 142 { 0x0afffffb }, /* beq <wfi> */ 143 { 0xe12fff11 }, /* bx r1 */ 144 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 145 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 146 { 0, FIXUP_TERMINATOR } 147 }; 148 149 static void write_bootloader(const char *name, hwaddr addr, 150 const ARMInsnFixup *insns, uint32_t *fixupcontext, 151 AddressSpace *as) 152 { 153 /* Fix up the specified bootloader fragment and write it into 154 * guest memory using rom_add_blob_fixed(). fixupcontext is 155 * an array giving the values to write in for the fixup types 156 * which write a value into the code array. 157 */ 158 int i, len; 159 uint32_t *code; 160 161 len = 0; 162 while (insns[len].fixup != FIXUP_TERMINATOR) { 163 len++; 164 } 165 166 code = g_new0(uint32_t, len); 167 168 for (i = 0; i < len; i++) { 169 uint32_t insn = insns[i].insn; 170 FixupType fixup = insns[i].fixup; 171 172 switch (fixup) { 173 case FIXUP_NONE: 174 break; 175 case FIXUP_BOARDID: 176 case FIXUP_BOARD_SETUP: 177 case FIXUP_ARGPTR: 178 case FIXUP_ENTRYPOINT: 179 case FIXUP_GIC_CPU_IF: 180 case FIXUP_BOOTREG: 181 case FIXUP_DSB: 182 insn = fixupcontext[fixup]; 183 break; 184 default: 185 abort(); 186 } 187 code[i] = tswap32(insn); 188 } 189 190 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 191 192 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 193 194 g_free(code); 195 } 196 197 static void default_write_secondary(ARMCPU *cpu, 198 const struct arm_boot_info *info) 199 { 200 uint32_t fixupcontext[FIXUP_MAX]; 201 AddressSpace *as = arm_boot_address_space(cpu, info); 202 203 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 204 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 205 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 206 fixupcontext[FIXUP_DSB] = DSB_INSN; 207 } else { 208 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 209 } 210 211 write_bootloader("smpboot", info->smp_loader_start, 212 smpboot, fixupcontext, as); 213 } 214 215 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 216 const struct arm_boot_info *info, 217 hwaddr mvbar_addr) 218 { 219 AddressSpace *as = arm_boot_address_space(cpu, info); 220 int n; 221 uint32_t mvbar_blob[] = { 222 /* mvbar_addr: secure monitor vectors 223 * Default unimplemented and unused vectors to spin. Makes it 224 * easier to debug (as opposed to the CPU running away). 225 */ 226 0xeafffffe, /* (spin) */ 227 0xeafffffe, /* (spin) */ 228 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 229 0xeafffffe, /* (spin) */ 230 0xeafffffe, /* (spin) */ 231 0xeafffffe, /* (spin) */ 232 0xeafffffe, /* (spin) */ 233 0xeafffffe, /* (spin) */ 234 }; 235 uint32_t board_setup_blob[] = { 236 /* board setup addr */ 237 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 238 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 239 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 240 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 241 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 242 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 243 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 244 0xe1a0f001, /* mov pc, r1 ;return */ 245 }; 246 247 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 248 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 249 250 /* check that these blobs don't overlap */ 251 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 252 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 253 254 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 255 mvbar_blob[n] = tswap32(mvbar_blob[n]); 256 } 257 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 258 mvbar_addr, as); 259 260 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 261 board_setup_blob[n] = tswap32(board_setup_blob[n]); 262 } 263 rom_add_blob_fixed_as("board-setup", board_setup_blob, 264 sizeof(board_setup_blob), info->board_setup_addr, as); 265 } 266 267 static void default_reset_secondary(ARMCPU *cpu, 268 const struct arm_boot_info *info) 269 { 270 AddressSpace *as = arm_boot_address_space(cpu, info); 271 CPUState *cs = CPU(cpu); 272 273 address_space_stl_notdirty(as, info->smp_bootreg_addr, 274 0, MEMTXATTRS_UNSPECIFIED, NULL); 275 cpu_set_pc(cs, info->smp_loader_start); 276 } 277 278 static inline bool have_dtb(const struct arm_boot_info *info) 279 { 280 return info->dtb_filename || info->get_dtb; 281 } 282 283 #define WRITE_WORD(p, value) do { \ 284 address_space_stl_notdirty(as, p, value, \ 285 MEMTXATTRS_UNSPECIFIED, NULL); \ 286 p += 4; \ 287 } while (0) 288 289 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 290 { 291 int initrd_size = info->initrd_size; 292 hwaddr base = info->loader_start; 293 hwaddr p; 294 295 p = base + KERNEL_ARGS_ADDR; 296 /* ATAG_CORE */ 297 WRITE_WORD(p, 5); 298 WRITE_WORD(p, 0x54410001); 299 WRITE_WORD(p, 1); 300 WRITE_WORD(p, 0x1000); 301 WRITE_WORD(p, 0); 302 /* ATAG_MEM */ 303 /* TODO: handle multiple chips on one ATAG list */ 304 WRITE_WORD(p, 4); 305 WRITE_WORD(p, 0x54410002); 306 WRITE_WORD(p, info->ram_size); 307 WRITE_WORD(p, info->loader_start); 308 if (initrd_size) { 309 /* ATAG_INITRD2 */ 310 WRITE_WORD(p, 4); 311 WRITE_WORD(p, 0x54420005); 312 WRITE_WORD(p, info->initrd_start); 313 WRITE_WORD(p, initrd_size); 314 } 315 if (info->kernel_cmdline && *info->kernel_cmdline) { 316 /* ATAG_CMDLINE */ 317 int cmdline_size; 318 319 cmdline_size = strlen(info->kernel_cmdline); 320 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 321 (const uint8_t *)info->kernel_cmdline, 322 cmdline_size + 1); 323 cmdline_size = (cmdline_size >> 2) + 1; 324 WRITE_WORD(p, cmdline_size + 2); 325 WRITE_WORD(p, 0x54410009); 326 p += cmdline_size * 4; 327 } 328 if (info->atag_board) { 329 /* ATAG_BOARD */ 330 int atag_board_len; 331 uint8_t atag_board_buf[0x1000]; 332 333 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 334 WRITE_WORD(p, (atag_board_len + 8) >> 2); 335 WRITE_WORD(p, 0x414f4d50); 336 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 337 atag_board_buf, atag_board_len); 338 p += atag_board_len; 339 } 340 /* ATAG_END */ 341 WRITE_WORD(p, 0); 342 WRITE_WORD(p, 0); 343 } 344 345 static void set_kernel_args_old(const struct arm_boot_info *info, 346 AddressSpace *as) 347 { 348 hwaddr p; 349 const char *s; 350 int initrd_size = info->initrd_size; 351 hwaddr base = info->loader_start; 352 353 /* see linux/include/asm-arm/setup.h */ 354 p = base + KERNEL_ARGS_ADDR; 355 /* page_size */ 356 WRITE_WORD(p, 4096); 357 /* nr_pages */ 358 WRITE_WORD(p, info->ram_size / 4096); 359 /* ramdisk_size */ 360 WRITE_WORD(p, 0); 361 #define FLAG_READONLY 1 362 #define FLAG_RDLOAD 4 363 #define FLAG_RDPROMPT 8 364 /* flags */ 365 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 366 /* rootdev */ 367 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 368 /* video_num_cols */ 369 WRITE_WORD(p, 0); 370 /* video_num_rows */ 371 WRITE_WORD(p, 0); 372 /* video_x */ 373 WRITE_WORD(p, 0); 374 /* video_y */ 375 WRITE_WORD(p, 0); 376 /* memc_control_reg */ 377 WRITE_WORD(p, 0); 378 /* unsigned char sounddefault */ 379 /* unsigned char adfsdrives */ 380 /* unsigned char bytes_per_char_h */ 381 /* unsigned char bytes_per_char_v */ 382 WRITE_WORD(p, 0); 383 /* pages_in_bank[4] */ 384 WRITE_WORD(p, 0); 385 WRITE_WORD(p, 0); 386 WRITE_WORD(p, 0); 387 WRITE_WORD(p, 0); 388 /* pages_in_vram */ 389 WRITE_WORD(p, 0); 390 /* initrd_start */ 391 if (initrd_size) { 392 WRITE_WORD(p, info->initrd_start); 393 } else { 394 WRITE_WORD(p, 0); 395 } 396 /* initrd_size */ 397 WRITE_WORD(p, initrd_size); 398 /* rd_start */ 399 WRITE_WORD(p, 0); 400 /* system_rev */ 401 WRITE_WORD(p, 0); 402 /* system_serial_low */ 403 WRITE_WORD(p, 0); 404 /* system_serial_high */ 405 WRITE_WORD(p, 0); 406 /* mem_fclk_21285 */ 407 WRITE_WORD(p, 0); 408 /* zero unused fields */ 409 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 410 WRITE_WORD(p, 0); 411 } 412 s = info->kernel_cmdline; 413 if (s) { 414 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 415 (const uint8_t *)s, strlen(s) + 1); 416 } else { 417 WRITE_WORD(p, 0); 418 } 419 } 420 421 static void fdt_add_psci_node(void *fdt) 422 { 423 uint32_t cpu_suspend_fn; 424 uint32_t cpu_off_fn; 425 uint32_t cpu_on_fn; 426 uint32_t migrate_fn; 427 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 428 const char *psci_method; 429 int64_t psci_conduit; 430 int rc; 431 432 psci_conduit = object_property_get_int(OBJECT(armcpu), 433 "psci-conduit", 434 &error_abort); 435 switch (psci_conduit) { 436 case QEMU_PSCI_CONDUIT_DISABLED: 437 return; 438 case QEMU_PSCI_CONDUIT_HVC: 439 psci_method = "hvc"; 440 break; 441 case QEMU_PSCI_CONDUIT_SMC: 442 psci_method = "smc"; 443 break; 444 default: 445 g_assert_not_reached(); 446 } 447 448 /* 449 * If /psci node is present in provided DTB, assume that no fixup 450 * is necessary and all PSCI configuration should be taken as-is 451 */ 452 rc = fdt_path_offset(fdt, "/psci"); 453 if (rc >= 0) { 454 return; 455 } 456 457 qemu_fdt_add_subnode(fdt, "/psci"); 458 if (armcpu->psci_version == 2) { 459 const char comp[] = "arm,psci-0.2\0arm,psci"; 460 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 461 462 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 463 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 464 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 465 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 466 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 467 } else { 468 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 469 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 470 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 471 } 472 } else { 473 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 474 475 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 476 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 477 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 478 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 479 } 480 481 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 482 * to the instruction that should be used to invoke PSCI functions. 483 * However, the device tree binding uses 'method' instead, so that is 484 * what we should use here. 485 */ 486 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 487 488 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 489 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 490 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 491 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 492 } 493 494 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 495 hwaddr addr_limit, AddressSpace *as) 496 { 497 void *fdt = NULL; 498 int size, rc, n = 0; 499 uint32_t acells, scells; 500 char *nodename; 501 unsigned int i; 502 hwaddr mem_base, mem_len; 503 char **node_path; 504 Error *err = NULL; 505 506 if (binfo->dtb_filename) { 507 char *filename; 508 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 509 if (!filename) { 510 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 511 goto fail; 512 } 513 514 fdt = load_device_tree(filename, &size); 515 if (!fdt) { 516 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 517 g_free(filename); 518 goto fail; 519 } 520 g_free(filename); 521 } else { 522 fdt = binfo->get_dtb(binfo, &size); 523 if (!fdt) { 524 fprintf(stderr, "Board was unable to create a dtb blob\n"); 525 goto fail; 526 } 527 } 528 529 if (addr_limit > addr && size > (addr_limit - addr)) { 530 /* Installing the device tree blob at addr would exceed addr_limit. 531 * Whether this constitutes failure is up to the caller to decide, 532 * so just return 0 as size, i.e., no error. 533 */ 534 g_free(fdt); 535 return 0; 536 } 537 538 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 539 NULL, &error_fatal); 540 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 541 NULL, &error_fatal); 542 if (acells == 0 || scells == 0) { 543 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 544 goto fail; 545 } 546 547 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { 548 /* This is user error so deserves a friendlier error message 549 * than the failure of setprop_sized_cells would provide 550 */ 551 fprintf(stderr, "qemu: dtb file not compatible with " 552 "RAM size > 4GB\n"); 553 goto fail; 554 } 555 556 /* nop all root nodes matching /memory or /memory@unit-address */ 557 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 558 if (err) { 559 error_report_err(err); 560 goto fail; 561 } 562 while (node_path[n]) { 563 if (g_str_has_prefix(node_path[n], "/memory")) { 564 qemu_fdt_nop_node(fdt, node_path[n]); 565 } 566 n++; 567 } 568 g_strfreev(node_path); 569 570 if (nb_numa_nodes > 0) { 571 mem_base = binfo->loader_start; 572 for (i = 0; i < nb_numa_nodes; i++) { 573 mem_len = numa_info[i].node_mem; 574 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 575 qemu_fdt_add_subnode(fdt, nodename); 576 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 577 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 578 acells, mem_base, 579 scells, mem_len); 580 if (rc < 0) { 581 fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename, 582 i); 583 goto fail; 584 } 585 586 qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i); 587 mem_base += mem_len; 588 g_free(nodename); 589 } 590 } else { 591 nodename = g_strdup_printf("/memory@%" PRIx64, binfo->loader_start); 592 qemu_fdt_add_subnode(fdt, nodename); 593 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 594 595 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 596 acells, binfo->loader_start, 597 scells, binfo->ram_size); 598 if (rc < 0) { 599 fprintf(stderr, "couldn't set %s reg\n", nodename); 600 goto fail; 601 } 602 g_free(nodename); 603 } 604 605 rc = fdt_path_offset(fdt, "/chosen"); 606 if (rc < 0) { 607 qemu_fdt_add_subnode(fdt, "/chosen"); 608 } 609 610 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { 611 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 612 binfo->kernel_cmdline); 613 if (rc < 0) { 614 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 615 goto fail; 616 } 617 } 618 619 if (binfo->initrd_size) { 620 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 621 binfo->initrd_start); 622 if (rc < 0) { 623 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 624 goto fail; 625 } 626 627 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 628 binfo->initrd_start + binfo->initrd_size); 629 if (rc < 0) { 630 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 631 goto fail; 632 } 633 } 634 635 fdt_add_psci_node(fdt); 636 637 if (binfo->modify_dtb) { 638 binfo->modify_dtb(binfo, fdt); 639 } 640 641 qemu_fdt_dumpdtb(fdt, size); 642 643 /* Put the DTB into the memory map as a ROM image: this will ensure 644 * the DTB is copied again upon reset, even if addr points into RAM. 645 */ 646 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 647 648 g_free(fdt); 649 650 return size; 651 652 fail: 653 g_free(fdt); 654 return -1; 655 } 656 657 static void do_cpu_reset(void *opaque) 658 { 659 ARMCPU *cpu = opaque; 660 CPUState *cs = CPU(cpu); 661 CPUARMState *env = &cpu->env; 662 const struct arm_boot_info *info = env->boot_info; 663 664 cpu_reset(cs); 665 if (info) { 666 if (!info->is_linux) { 667 int i; 668 /* Jump to the entry point. */ 669 uint64_t entry = info->entry; 670 671 switch (info->endianness) { 672 case ARM_ENDIANNESS_LE: 673 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 674 for (i = 1; i < 4; ++i) { 675 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 676 } 677 env->uncached_cpsr &= ~CPSR_E; 678 break; 679 case ARM_ENDIANNESS_BE8: 680 env->cp15.sctlr_el[1] |= SCTLR_E0E; 681 for (i = 1; i < 4; ++i) { 682 env->cp15.sctlr_el[i] |= SCTLR_EE; 683 } 684 env->uncached_cpsr |= CPSR_E; 685 break; 686 case ARM_ENDIANNESS_BE32: 687 env->cp15.sctlr_el[1] |= SCTLR_B; 688 break; 689 case ARM_ENDIANNESS_UNKNOWN: 690 break; /* Board's decision */ 691 default: 692 g_assert_not_reached(); 693 } 694 695 if (!env->aarch64) { 696 env->thumb = info->entry & 1; 697 entry &= 0xfffffffe; 698 } 699 cpu_set_pc(cs, entry); 700 } else { 701 /* If we are booting Linux then we need to check whether we are 702 * booting into secure or non-secure state and adjust the state 703 * accordingly. Out of reset, ARM is defined to be in secure state 704 * (SCR.NS = 0), we change that here if non-secure boot has been 705 * requested. 706 */ 707 if (arm_feature(env, ARM_FEATURE_EL3)) { 708 /* AArch64 is defined to come out of reset into EL3 if enabled. 709 * If we are booting Linux then we need to adjust our EL as 710 * Linux expects us to be in EL2 or EL1. AArch32 resets into 711 * SVC, which Linux expects, so no privilege/exception level to 712 * adjust. 713 */ 714 if (env->aarch64) { 715 env->cp15.scr_el3 |= SCR_RW; 716 if (arm_feature(env, ARM_FEATURE_EL2)) { 717 env->cp15.hcr_el2 |= HCR_RW; 718 env->pstate = PSTATE_MODE_EL2h; 719 } else { 720 env->pstate = PSTATE_MODE_EL1h; 721 } 722 /* AArch64 kernels never boot in secure mode */ 723 assert(!info->secure_boot); 724 /* This hook is only supported for AArch32 currently: 725 * bootloader_aarch64[] will not call the hook, and 726 * the code above has already dropped us into EL2 or EL1. 727 */ 728 assert(!info->secure_board_setup); 729 } 730 731 if (arm_feature(env, ARM_FEATURE_EL2)) { 732 /* If we have EL2 then Linux expects the HVC insn to work */ 733 env->cp15.scr_el3 |= SCR_HCE; 734 } 735 736 /* Set to non-secure if not a secure boot */ 737 if (!info->secure_boot && 738 (cs != first_cpu || !info->secure_board_setup)) { 739 /* Linux expects non-secure state */ 740 env->cp15.scr_el3 |= SCR_NS; 741 } 742 } 743 744 if (!env->aarch64 && !info->secure_boot && 745 arm_feature(env, ARM_FEATURE_EL2)) { 746 /* 747 * This is an AArch32 boot not to Secure state, and 748 * we have Hyp mode available, so boot the kernel into 749 * Hyp mode. This is not how the CPU comes out of reset, 750 * so we need to manually put it there. 751 */ 752 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw); 753 } 754 755 if (cs == first_cpu) { 756 AddressSpace *as = arm_boot_address_space(cpu, info); 757 758 cpu_set_pc(cs, info->loader_start); 759 760 if (!have_dtb(info)) { 761 if (old_param) { 762 set_kernel_args_old(info, as); 763 } else { 764 set_kernel_args(info, as); 765 } 766 } 767 } else { 768 info->secondary_cpu_reset_hook(cpu, info); 769 } 770 } 771 } 772 } 773 774 /** 775 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 776 * by key. 777 * @fw_cfg: The firmware config instance to store the data in. 778 * @size_key: The firmware config key to store the size of the loaded 779 * data under, with fw_cfg_add_i32(). 780 * @data_key: The firmware config key to store the loaded data under, 781 * with fw_cfg_add_bytes(). 782 * @image_name: The name of the image file to load. If it is NULL, the 783 * function returns without doing anything. 784 * @try_decompress: Whether the image should be decompressed (gunzipped) before 785 * adding it to fw_cfg. If decompression fails, the image is 786 * loaded as-is. 787 * 788 * In case of failure, the function prints an error message to stderr and the 789 * process exits with status 1. 790 */ 791 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 792 uint16_t data_key, const char *image_name, 793 bool try_decompress) 794 { 795 size_t size = -1; 796 uint8_t *data; 797 798 if (image_name == NULL) { 799 return; 800 } 801 802 if (try_decompress) { 803 size = load_image_gzipped_buffer(image_name, 804 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 805 } 806 807 if (size == (size_t)-1) { 808 gchar *contents; 809 gsize length; 810 811 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 812 error_report("failed to load \"%s\"", image_name); 813 exit(1); 814 } 815 size = length; 816 data = (uint8_t *)contents; 817 } 818 819 fw_cfg_add_i32(fw_cfg, size_key, size); 820 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 821 } 822 823 static int do_arm_linux_init(Object *obj, void *opaque) 824 { 825 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 826 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 827 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 828 struct arm_boot_info *info = opaque; 829 830 if (albifc->arm_linux_init) { 831 albifc->arm_linux_init(albif, info->secure_boot); 832 } 833 } 834 return 0; 835 } 836 837 static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 838 uint64_t *lowaddr, uint64_t *highaddr, 839 int elf_machine, AddressSpace *as) 840 { 841 bool elf_is64; 842 union { 843 Elf32_Ehdr h32; 844 Elf64_Ehdr h64; 845 } elf_header; 846 int data_swab = 0; 847 bool big_endian; 848 int64_t ret = -1; 849 Error *err = NULL; 850 851 852 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 853 if (err) { 854 error_free(err); 855 return ret; 856 } 857 858 if (elf_is64) { 859 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 860 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 861 : ARM_ENDIANNESS_LE; 862 } else { 863 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 864 if (big_endian) { 865 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 866 info->endianness = ARM_ENDIANNESS_BE8; 867 } else { 868 info->endianness = ARM_ENDIANNESS_BE32; 869 /* In BE32, the CPU has a different view of the per-byte 870 * address map than the rest of the system. BE32 ELF files 871 * are organised such that they can be programmed through 872 * the CPU's per-word byte-reversed view of the world. QEMU 873 * however loads ELF files independently of the CPU. So 874 * tell the ELF loader to byte reverse the data for us. 875 */ 876 data_swab = 2; 877 } 878 } else { 879 info->endianness = ARM_ENDIANNESS_LE; 880 } 881 } 882 883 ret = load_elf_as(info->kernel_filename, NULL, NULL, 884 pentry, lowaddr, highaddr, big_endian, elf_machine, 885 1, data_swab, as); 886 if (ret <= 0) { 887 /* The header loaded but the image didn't */ 888 exit(1); 889 } 890 891 return ret; 892 } 893 894 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 895 hwaddr *entry, AddressSpace *as) 896 { 897 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 898 uint8_t *buffer; 899 int size; 900 901 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 902 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 903 &buffer); 904 905 if (size < 0) { 906 gsize len; 907 908 /* Load as raw file otherwise */ 909 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 910 return -1; 911 } 912 size = len; 913 } 914 915 /* check the arm64 magic header value -- very old kernels may not have it */ 916 if (size > ARM64_MAGIC_OFFSET + 4 && 917 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 918 uint64_t hdrvals[2]; 919 920 /* The arm64 Image header has text_offset and image_size fields at 8 and 921 * 16 bytes into the Image header, respectively. The text_offset field 922 * is only valid if the image_size is non-zero. 923 */ 924 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 925 if (hdrvals[1] != 0) { 926 kernel_load_offset = le64_to_cpu(hdrvals[0]); 927 928 /* 929 * We write our startup "bootloader" at the very bottom of RAM, 930 * so that bit can't be used for the image. Luckily the Image 931 * format specification is that the image requests only an offset 932 * from a 2MB boundary, not an absolute load address. So if the 933 * image requests an offset that might mean it overlaps with the 934 * bootloader, we can just load it starting at 2MB+offset rather 935 * than 0MB + offset. 936 */ 937 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 938 kernel_load_offset += 2 * MiB; 939 } 940 } 941 } 942 943 *entry = mem_base + kernel_load_offset; 944 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 945 946 g_free(buffer); 947 948 return size; 949 } 950 951 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 952 { 953 CPUState *cs; 954 int kernel_size; 955 int initrd_size; 956 int is_linux = 0; 957 uint64_t elf_entry, elf_low_addr, elf_high_addr; 958 int elf_machine; 959 hwaddr entry; 960 static const ARMInsnFixup *primary_loader; 961 AddressSpace *as = arm_boot_address_space(cpu, info); 962 963 /* CPU objects (unlike devices) are not automatically reset on system 964 * reset, so we must always register a handler to do so. If we're 965 * actually loading a kernel, the handler is also responsible for 966 * arranging that we start it correctly. 967 */ 968 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 969 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 970 } 971 972 /* The board code is not supposed to set secure_board_setup unless 973 * running its code in secure mode is actually possible, and KVM 974 * doesn't support secure. 975 */ 976 assert(!(info->secure_board_setup && kvm_enabled())); 977 978 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 979 info->dtb_limit = 0; 980 981 /* Load the kernel. */ 982 if (!info->kernel_filename || info->firmware_loaded) { 983 984 if (have_dtb(info)) { 985 /* If we have a device tree blob, but no kernel to supply it to (or 986 * the kernel is supposed to be loaded by the bootloader), copy the 987 * DTB to the base of RAM for the bootloader to pick up. 988 */ 989 info->dtb_start = info->loader_start; 990 } 991 992 if (info->kernel_filename) { 993 FWCfgState *fw_cfg; 994 bool try_decompressing_kernel; 995 996 fw_cfg = fw_cfg_find(); 997 try_decompressing_kernel = arm_feature(&cpu->env, 998 ARM_FEATURE_AARCH64); 999 1000 /* Expose the kernel, the command line, and the initrd in fw_cfg. 1001 * We don't process them here at all, it's all left to the 1002 * firmware. 1003 */ 1004 load_image_to_fw_cfg(fw_cfg, 1005 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1006 info->kernel_filename, 1007 try_decompressing_kernel); 1008 load_image_to_fw_cfg(fw_cfg, 1009 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1010 info->initrd_filename, false); 1011 1012 if (info->kernel_cmdline) { 1013 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1014 strlen(info->kernel_cmdline) + 1); 1015 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1016 info->kernel_cmdline); 1017 } 1018 } 1019 1020 /* We will start from address 0 (typically a boot ROM image) in the 1021 * same way as hardware. 1022 */ 1023 return; 1024 } 1025 1026 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1027 primary_loader = bootloader_aarch64; 1028 elf_machine = EM_AARCH64; 1029 } else { 1030 primary_loader = bootloader; 1031 if (!info->write_board_setup) { 1032 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 1033 } 1034 elf_machine = EM_ARM; 1035 } 1036 1037 if (!info->secondary_cpu_reset_hook) { 1038 info->secondary_cpu_reset_hook = default_reset_secondary; 1039 } 1040 if (!info->write_secondary_boot) { 1041 info->write_secondary_boot = default_write_secondary; 1042 } 1043 1044 if (info->nb_cpus == 0) 1045 info->nb_cpus = 1; 1046 1047 /* We want to put the initrd far enough into RAM that when the 1048 * kernel is uncompressed it will not clobber the initrd. However 1049 * on boards without much RAM we must ensure that we still leave 1050 * enough room for a decent sized initrd, and on boards with large 1051 * amounts of RAM we must avoid the initrd being so far up in RAM 1052 * that it is outside lowmem and inaccessible to the kernel. 1053 * So for boards with less than 256MB of RAM we put the initrd 1054 * halfway into RAM, and for boards with 256MB of RAM or more we put 1055 * the initrd at 128MB. 1056 */ 1057 info->initrd_start = info->loader_start + 1058 MIN(info->ram_size / 2, 128 * 1024 * 1024); 1059 1060 /* Assume that raw images are linux kernels, and ELF images are not. */ 1061 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, 1062 &elf_high_addr, elf_machine, as); 1063 if (kernel_size > 0 && have_dtb(info)) { 1064 /* If there is still some room left at the base of RAM, try and put 1065 * the DTB there like we do for images loaded with -bios or -pflash. 1066 */ 1067 if (elf_low_addr > info->loader_start 1068 || elf_high_addr < info->loader_start) { 1069 /* Set elf_low_addr as address limit for arm_load_dtb if it may be 1070 * pointing into RAM, otherwise pass '0' (no limit) 1071 */ 1072 if (elf_low_addr < info->loader_start) { 1073 elf_low_addr = 0; 1074 } 1075 info->dtb_start = info->loader_start; 1076 info->dtb_limit = elf_low_addr; 1077 } 1078 } 1079 entry = elf_entry; 1080 if (kernel_size < 0) { 1081 kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL, 1082 &is_linux, NULL, NULL, as); 1083 } 1084 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1085 kernel_size = load_aarch64_image(info->kernel_filename, 1086 info->loader_start, &entry, as); 1087 is_linux = 1; 1088 } else if (kernel_size < 0) { 1089 /* 32-bit ARM */ 1090 entry = info->loader_start + KERNEL_LOAD_ADDR; 1091 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1092 info->ram_size - KERNEL_LOAD_ADDR, 1093 as); 1094 is_linux = 1; 1095 } 1096 if (kernel_size < 0) { 1097 error_report("could not load kernel '%s'", info->kernel_filename); 1098 exit(1); 1099 } 1100 info->entry = entry; 1101 if (is_linux) { 1102 uint32_t fixupcontext[FIXUP_MAX]; 1103 1104 if (info->initrd_filename) { 1105 initrd_size = load_ramdisk_as(info->initrd_filename, 1106 info->initrd_start, 1107 info->ram_size - info->initrd_start, 1108 as); 1109 if (initrd_size < 0) { 1110 initrd_size = load_image_targphys_as(info->initrd_filename, 1111 info->initrd_start, 1112 info->ram_size - 1113 info->initrd_start, 1114 as); 1115 } 1116 if (initrd_size < 0) { 1117 error_report("could not load initrd '%s'", 1118 info->initrd_filename); 1119 exit(1); 1120 } 1121 } else { 1122 initrd_size = 0; 1123 } 1124 info->initrd_size = initrd_size; 1125 1126 fixupcontext[FIXUP_BOARDID] = info->board_id; 1127 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1128 1129 /* for device tree boot, we pass the DTB directly in r2. Otherwise 1130 * we point to the kernel args. 1131 */ 1132 if (have_dtb(info)) { 1133 hwaddr align; 1134 1135 if (elf_machine == EM_AARCH64) { 1136 /* 1137 * Some AArch64 kernels on early bootup map the fdt region as 1138 * 1139 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1140 * 1141 * Let's play safe and prealign it to 2MB to give us some space. 1142 */ 1143 align = 2 * 1024 * 1024; 1144 } else { 1145 /* 1146 * Some 32bit kernels will trash anything in the 4K page the 1147 * initrd ends in, so make sure the DTB isn't caught up in that. 1148 */ 1149 align = 4096; 1150 } 1151 1152 /* Place the DTB after the initrd in memory with alignment. */ 1153 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1154 align); 1155 fixupcontext[FIXUP_ARGPTR] = info->dtb_start; 1156 } else { 1157 fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR; 1158 if (info->ram_size >= (1ULL << 32)) { 1159 error_report("RAM size must be less than 4GB to boot" 1160 " Linux kernel using ATAGS (try passing a device tree" 1161 " using -dtb)"); 1162 exit(1); 1163 } 1164 } 1165 fixupcontext[FIXUP_ENTRYPOINT] = entry; 1166 1167 write_bootloader("bootloader", info->loader_start, 1168 primary_loader, fixupcontext, as); 1169 1170 if (info->nb_cpus > 1) { 1171 info->write_secondary_boot(cpu, info); 1172 } 1173 if (info->write_board_setup) { 1174 info->write_board_setup(cpu, info); 1175 } 1176 1177 /* Notify devices which need to fake up firmware initialization 1178 * that we're doing a direct kernel boot. 1179 */ 1180 object_child_foreach_recursive(object_get_root(), 1181 do_arm_linux_init, info); 1182 } 1183 info->is_linux = is_linux; 1184 1185 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1186 ARM_CPU(cs)->env.boot_info = info; 1187 } 1188 1189 if (!info->skip_dtb_autoload && have_dtb(info)) { 1190 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { 1191 exit(1); 1192 } 1193 } 1194 } 1195 1196 static const TypeInfo arm_linux_boot_if_info = { 1197 .name = TYPE_ARM_LINUX_BOOT_IF, 1198 .parent = TYPE_INTERFACE, 1199 .class_size = sizeof(ARMLinuxBootIfClass), 1200 }; 1201 1202 static void arm_linux_boot_register_types(void) 1203 { 1204 type_register_static(&arm_linux_boot_if_info); 1205 } 1206 1207 type_init(arm_linux_boot_register_types) 1208