1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/hw.h" 13 #include "hw/arm/arm.h" 14 #include "hw/arm/linux-boot-if.h" 15 #include "sysemu/kvm.h" 16 #include "sysemu/sysemu.h" 17 #include "sysemu/numa.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "elf.h" 21 #include "sysemu/device_tree.h" 22 #include "qemu/config-file.h" 23 #include "exec/address-spaces.h" 24 25 /* Kernel boot protocol is specified in the kernel docs 26 * Documentation/arm/Booting and Documentation/arm64/booting.txt 27 * They have different preferred image load offsets from system RAM base. 28 */ 29 #define KERNEL_ARGS_ADDR 0x100 30 #define KERNEL_LOAD_ADDR 0x00010000 31 #define KERNEL64_LOAD_ADDR 0x00080000 32 33 typedef enum { 34 FIXUP_NONE = 0, /* do nothing */ 35 FIXUP_TERMINATOR, /* end of insns */ 36 FIXUP_BOARDID, /* overwrite with board ID number */ 37 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 38 FIXUP_ARGPTR, /* overwrite with pointer to kernel args */ 39 FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */ 40 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 41 FIXUP_BOOTREG, /* overwrite with boot register address */ 42 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 43 FIXUP_MAX, 44 } FixupType; 45 46 typedef struct ARMInsnFixup { 47 uint32_t insn; 48 FixupType fixup; 49 } ARMInsnFixup; 50 51 static const ARMInsnFixup bootloader_aarch64[] = { 52 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 53 { 0xaa1f03e1 }, /* mov x1, xzr */ 54 { 0xaa1f03e2 }, /* mov x2, xzr */ 55 { 0xaa1f03e3 }, /* mov x3, xzr */ 56 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 57 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 58 { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */ 59 { 0 }, /* .word @DTB Higher 32-bits */ 60 { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */ 61 { 0 }, /* .word @Kernel Entry Higher 32-bits */ 62 { 0, FIXUP_TERMINATOR } 63 }; 64 65 /* A very small bootloader: call the board-setup code (if needed), 66 * set r0-r2, then jump to the kernel. 67 * If we're not calling boot setup code then we don't copy across 68 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 69 */ 70 71 static const ARMInsnFixup bootloader[] = { 72 { 0xe28fe004 }, /* add lr, pc, #4 */ 73 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 74 { 0, FIXUP_BOARD_SETUP }, 75 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 76 { 0xe3a00000 }, /* mov r0, #0 */ 77 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 78 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 79 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 80 { 0, FIXUP_BOARDID }, 81 { 0, FIXUP_ARGPTR }, 82 { 0, FIXUP_ENTRYPOINT }, 83 { 0, FIXUP_TERMINATOR } 84 }; 85 86 /* Handling for secondary CPU boot in a multicore system. 87 * Unlike the uniprocessor/primary CPU boot, this is platform 88 * dependent. The default code here is based on the secondary 89 * CPU boot protocol used on realview/vexpress boards, with 90 * some parameterisation to increase its flexibility. 91 * QEMU platform models for which this code is not appropriate 92 * should override write_secondary_boot and secondary_cpu_reset_hook 93 * instead. 94 * 95 * This code enables the interrupt controllers for the secondary 96 * CPUs and then puts all the secondary CPUs into a loop waiting 97 * for an interprocessor interrupt and polling a configurable 98 * location for the kernel secondary CPU entry point. 99 */ 100 #define DSB_INSN 0xf57ff04f 101 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 102 103 static const ARMInsnFixup smpboot[] = { 104 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 105 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 106 { 0xe3a01001 }, /* mov r1, #1 */ 107 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 108 { 0xe3a010ff }, /* mov r1, #0xff */ 109 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 110 { 0, FIXUP_DSB }, /* dsb */ 111 { 0xe320f003 }, /* wfi */ 112 { 0xe5901000 }, /* ldr r1, [r0] */ 113 { 0xe1110001 }, /* tst r1, r1 */ 114 { 0x0afffffb }, /* beq <wfi> */ 115 { 0xe12fff11 }, /* bx r1 */ 116 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 117 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 118 { 0, FIXUP_TERMINATOR } 119 }; 120 121 static void write_bootloader(const char *name, hwaddr addr, 122 const ARMInsnFixup *insns, uint32_t *fixupcontext) 123 { 124 /* Fix up the specified bootloader fragment and write it into 125 * guest memory using rom_add_blob_fixed(). fixupcontext is 126 * an array giving the values to write in for the fixup types 127 * which write a value into the code array. 128 */ 129 int i, len; 130 uint32_t *code; 131 132 len = 0; 133 while (insns[len].fixup != FIXUP_TERMINATOR) { 134 len++; 135 } 136 137 code = g_new0(uint32_t, len); 138 139 for (i = 0; i < len; i++) { 140 uint32_t insn = insns[i].insn; 141 FixupType fixup = insns[i].fixup; 142 143 switch (fixup) { 144 case FIXUP_NONE: 145 break; 146 case FIXUP_BOARDID: 147 case FIXUP_BOARD_SETUP: 148 case FIXUP_ARGPTR: 149 case FIXUP_ENTRYPOINT: 150 case FIXUP_GIC_CPU_IF: 151 case FIXUP_BOOTREG: 152 case FIXUP_DSB: 153 insn = fixupcontext[fixup]; 154 break; 155 default: 156 abort(); 157 } 158 code[i] = tswap32(insn); 159 } 160 161 rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr); 162 163 g_free(code); 164 } 165 166 static void default_write_secondary(ARMCPU *cpu, 167 const struct arm_boot_info *info) 168 { 169 uint32_t fixupcontext[FIXUP_MAX]; 170 171 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 172 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 173 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 174 fixupcontext[FIXUP_DSB] = DSB_INSN; 175 } else { 176 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 177 } 178 179 write_bootloader("smpboot", info->smp_loader_start, 180 smpboot, fixupcontext); 181 } 182 183 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 184 const struct arm_boot_info *info, 185 hwaddr mvbar_addr) 186 { 187 int n; 188 uint32_t mvbar_blob[] = { 189 /* mvbar_addr: secure monitor vectors 190 * Default unimplemented and unused vectors to spin. Makes it 191 * easier to debug (as opposed to the CPU running away). 192 */ 193 0xeafffffe, /* (spin) */ 194 0xeafffffe, /* (spin) */ 195 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 196 0xeafffffe, /* (spin) */ 197 0xeafffffe, /* (spin) */ 198 0xeafffffe, /* (spin) */ 199 0xeafffffe, /* (spin) */ 200 0xeafffffe, /* (spin) */ 201 }; 202 uint32_t board_setup_blob[] = { 203 /* board setup addr */ 204 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 205 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 206 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 207 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 208 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 209 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 210 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 211 0xe1a0f001, /* mov pc, r1 ;return */ 212 }; 213 214 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 215 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 216 217 /* check that these blobs don't overlap */ 218 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 219 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 220 221 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 222 mvbar_blob[n] = tswap32(mvbar_blob[n]); 223 } 224 rom_add_blob_fixed("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 225 mvbar_addr); 226 227 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 228 board_setup_blob[n] = tswap32(board_setup_blob[n]); 229 } 230 rom_add_blob_fixed("board-setup", board_setup_blob, 231 sizeof(board_setup_blob), info->board_setup_addr); 232 } 233 234 static void default_reset_secondary(ARMCPU *cpu, 235 const struct arm_boot_info *info) 236 { 237 CPUState *cs = CPU(cpu); 238 239 address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr, 240 0, MEMTXATTRS_UNSPECIFIED, NULL); 241 cpu_set_pc(cs, info->smp_loader_start); 242 } 243 244 static inline bool have_dtb(const struct arm_boot_info *info) 245 { 246 return info->dtb_filename || info->get_dtb; 247 } 248 249 #define WRITE_WORD(p, value) do { \ 250 address_space_stl_notdirty(&address_space_memory, p, value, \ 251 MEMTXATTRS_UNSPECIFIED, NULL); \ 252 p += 4; \ 253 } while (0) 254 255 static void set_kernel_args(const struct arm_boot_info *info) 256 { 257 int initrd_size = info->initrd_size; 258 hwaddr base = info->loader_start; 259 hwaddr p; 260 261 p = base + KERNEL_ARGS_ADDR; 262 /* ATAG_CORE */ 263 WRITE_WORD(p, 5); 264 WRITE_WORD(p, 0x54410001); 265 WRITE_WORD(p, 1); 266 WRITE_WORD(p, 0x1000); 267 WRITE_WORD(p, 0); 268 /* ATAG_MEM */ 269 /* TODO: handle multiple chips on one ATAG list */ 270 WRITE_WORD(p, 4); 271 WRITE_WORD(p, 0x54410002); 272 WRITE_WORD(p, info->ram_size); 273 WRITE_WORD(p, info->loader_start); 274 if (initrd_size) { 275 /* ATAG_INITRD2 */ 276 WRITE_WORD(p, 4); 277 WRITE_WORD(p, 0x54420005); 278 WRITE_WORD(p, info->initrd_start); 279 WRITE_WORD(p, initrd_size); 280 } 281 if (info->kernel_cmdline && *info->kernel_cmdline) { 282 /* ATAG_CMDLINE */ 283 int cmdline_size; 284 285 cmdline_size = strlen(info->kernel_cmdline); 286 cpu_physical_memory_write(p + 8, info->kernel_cmdline, 287 cmdline_size + 1); 288 cmdline_size = (cmdline_size >> 2) + 1; 289 WRITE_WORD(p, cmdline_size + 2); 290 WRITE_WORD(p, 0x54410009); 291 p += cmdline_size * 4; 292 } 293 if (info->atag_board) { 294 /* ATAG_BOARD */ 295 int atag_board_len; 296 uint8_t atag_board_buf[0x1000]; 297 298 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 299 WRITE_WORD(p, (atag_board_len + 8) >> 2); 300 WRITE_WORD(p, 0x414f4d50); 301 cpu_physical_memory_write(p, atag_board_buf, atag_board_len); 302 p += atag_board_len; 303 } 304 /* ATAG_END */ 305 WRITE_WORD(p, 0); 306 WRITE_WORD(p, 0); 307 } 308 309 static void set_kernel_args_old(const struct arm_boot_info *info) 310 { 311 hwaddr p; 312 const char *s; 313 int initrd_size = info->initrd_size; 314 hwaddr base = info->loader_start; 315 316 /* see linux/include/asm-arm/setup.h */ 317 p = base + KERNEL_ARGS_ADDR; 318 /* page_size */ 319 WRITE_WORD(p, 4096); 320 /* nr_pages */ 321 WRITE_WORD(p, info->ram_size / 4096); 322 /* ramdisk_size */ 323 WRITE_WORD(p, 0); 324 #define FLAG_READONLY 1 325 #define FLAG_RDLOAD 4 326 #define FLAG_RDPROMPT 8 327 /* flags */ 328 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 329 /* rootdev */ 330 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 331 /* video_num_cols */ 332 WRITE_WORD(p, 0); 333 /* video_num_rows */ 334 WRITE_WORD(p, 0); 335 /* video_x */ 336 WRITE_WORD(p, 0); 337 /* video_y */ 338 WRITE_WORD(p, 0); 339 /* memc_control_reg */ 340 WRITE_WORD(p, 0); 341 /* unsigned char sounddefault */ 342 /* unsigned char adfsdrives */ 343 /* unsigned char bytes_per_char_h */ 344 /* unsigned char bytes_per_char_v */ 345 WRITE_WORD(p, 0); 346 /* pages_in_bank[4] */ 347 WRITE_WORD(p, 0); 348 WRITE_WORD(p, 0); 349 WRITE_WORD(p, 0); 350 WRITE_WORD(p, 0); 351 /* pages_in_vram */ 352 WRITE_WORD(p, 0); 353 /* initrd_start */ 354 if (initrd_size) { 355 WRITE_WORD(p, info->initrd_start); 356 } else { 357 WRITE_WORD(p, 0); 358 } 359 /* initrd_size */ 360 WRITE_WORD(p, initrd_size); 361 /* rd_start */ 362 WRITE_WORD(p, 0); 363 /* system_rev */ 364 WRITE_WORD(p, 0); 365 /* system_serial_low */ 366 WRITE_WORD(p, 0); 367 /* system_serial_high */ 368 WRITE_WORD(p, 0); 369 /* mem_fclk_21285 */ 370 WRITE_WORD(p, 0); 371 /* zero unused fields */ 372 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 373 WRITE_WORD(p, 0); 374 } 375 s = info->kernel_cmdline; 376 if (s) { 377 cpu_physical_memory_write(p, s, strlen(s) + 1); 378 } else { 379 WRITE_WORD(p, 0); 380 } 381 } 382 383 /** 384 * load_dtb() - load a device tree binary image into memory 385 * @addr: the address to load the image at 386 * @binfo: struct describing the boot environment 387 * @addr_limit: upper limit of the available memory area at @addr 388 * 389 * Load a device tree supplied by the machine or by the user with the 390 * '-dtb' command line option, and put it at offset @addr in target 391 * memory. 392 * 393 * If @addr_limit contains a meaningful value (i.e., it is strictly greater 394 * than @addr), the device tree is only loaded if its size does not exceed 395 * the limit. 396 * 397 * Returns: the size of the device tree image on success, 398 * 0 if the image size exceeds the limit, 399 * -1 on errors. 400 * 401 * Note: Must not be called unless have_dtb(binfo) is true. 402 */ 403 static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 404 hwaddr addr_limit) 405 { 406 void *fdt = NULL; 407 int size, rc; 408 uint32_t acells, scells; 409 char *nodename; 410 unsigned int i; 411 hwaddr mem_base, mem_len; 412 413 if (binfo->dtb_filename) { 414 char *filename; 415 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 416 if (!filename) { 417 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 418 goto fail; 419 } 420 421 fdt = load_device_tree(filename, &size); 422 if (!fdt) { 423 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 424 g_free(filename); 425 goto fail; 426 } 427 g_free(filename); 428 } else { 429 fdt = binfo->get_dtb(binfo, &size); 430 if (!fdt) { 431 fprintf(stderr, "Board was unable to create a dtb blob\n"); 432 goto fail; 433 } 434 } 435 436 if (addr_limit > addr && size > (addr_limit - addr)) { 437 /* Installing the device tree blob at addr would exceed addr_limit. 438 * Whether this constitutes failure is up to the caller to decide, 439 * so just return 0 as size, i.e., no error. 440 */ 441 g_free(fdt); 442 return 0; 443 } 444 445 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 446 NULL, &error_fatal); 447 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 448 NULL, &error_fatal); 449 if (acells == 0 || scells == 0) { 450 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 451 goto fail; 452 } 453 454 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { 455 /* This is user error so deserves a friendlier error message 456 * than the failure of setprop_sized_cells would provide 457 */ 458 fprintf(stderr, "qemu: dtb file not compatible with " 459 "RAM size > 4GB\n"); 460 goto fail; 461 } 462 463 if (nb_numa_nodes > 0) { 464 /* 465 * Turn the /memory node created before into a NOP node, then create 466 * /memory@addr nodes for all numa nodes respectively. 467 */ 468 qemu_fdt_nop_node(fdt, "/memory"); 469 mem_base = binfo->loader_start; 470 for (i = 0; i < nb_numa_nodes; i++) { 471 mem_len = numa_info[i].node_mem; 472 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 473 qemu_fdt_add_subnode(fdt, nodename); 474 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 475 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 476 acells, mem_base, 477 scells, mem_len); 478 if (rc < 0) { 479 fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename, 480 i); 481 goto fail; 482 } 483 484 qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i); 485 mem_base += mem_len; 486 g_free(nodename); 487 } 488 } else { 489 rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg", 490 acells, binfo->loader_start, 491 scells, binfo->ram_size); 492 if (rc < 0) { 493 fprintf(stderr, "couldn't set /memory/reg\n"); 494 goto fail; 495 } 496 } 497 498 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { 499 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 500 binfo->kernel_cmdline); 501 if (rc < 0) { 502 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 503 goto fail; 504 } 505 } 506 507 if (binfo->initrd_size) { 508 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 509 binfo->initrd_start); 510 if (rc < 0) { 511 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 512 goto fail; 513 } 514 515 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 516 binfo->initrd_start + binfo->initrd_size); 517 if (rc < 0) { 518 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 519 goto fail; 520 } 521 } 522 523 if (binfo->modify_dtb) { 524 binfo->modify_dtb(binfo, fdt); 525 } 526 527 qemu_fdt_dumpdtb(fdt, size); 528 529 /* Put the DTB into the memory map as a ROM image: this will ensure 530 * the DTB is copied again upon reset, even if addr points into RAM. 531 */ 532 rom_add_blob_fixed("dtb", fdt, size, addr); 533 534 g_free(fdt); 535 536 return size; 537 538 fail: 539 g_free(fdt); 540 return -1; 541 } 542 543 static void do_cpu_reset(void *opaque) 544 { 545 ARMCPU *cpu = opaque; 546 CPUState *cs = CPU(cpu); 547 CPUARMState *env = &cpu->env; 548 const struct arm_boot_info *info = env->boot_info; 549 550 cpu_reset(cs); 551 if (info) { 552 if (!info->is_linux) { 553 int i; 554 /* Jump to the entry point. */ 555 uint64_t entry = info->entry; 556 557 switch (info->endianness) { 558 case ARM_ENDIANNESS_LE: 559 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 560 for (i = 1; i < 4; ++i) { 561 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 562 } 563 env->uncached_cpsr &= ~CPSR_E; 564 break; 565 case ARM_ENDIANNESS_BE8: 566 env->cp15.sctlr_el[1] |= SCTLR_E0E; 567 for (i = 1; i < 4; ++i) { 568 env->cp15.sctlr_el[i] |= SCTLR_EE; 569 } 570 env->uncached_cpsr |= CPSR_E; 571 break; 572 case ARM_ENDIANNESS_BE32: 573 env->cp15.sctlr_el[1] |= SCTLR_B; 574 break; 575 case ARM_ENDIANNESS_UNKNOWN: 576 break; /* Board's decision */ 577 default: 578 g_assert_not_reached(); 579 } 580 581 if (!env->aarch64) { 582 env->thumb = info->entry & 1; 583 entry &= 0xfffffffe; 584 } 585 cpu_set_pc(cs, entry); 586 } else { 587 /* If we are booting Linux then we need to check whether we are 588 * booting into secure or non-secure state and adjust the state 589 * accordingly. Out of reset, ARM is defined to be in secure state 590 * (SCR.NS = 0), we change that here if non-secure boot has been 591 * requested. 592 */ 593 if (arm_feature(env, ARM_FEATURE_EL3)) { 594 /* AArch64 is defined to come out of reset into EL3 if enabled. 595 * If we are booting Linux then we need to adjust our EL as 596 * Linux expects us to be in EL2 or EL1. AArch32 resets into 597 * SVC, which Linux expects, so no privilege/exception level to 598 * adjust. 599 */ 600 if (env->aarch64) { 601 env->cp15.scr_el3 |= SCR_RW; 602 if (arm_feature(env, ARM_FEATURE_EL2)) { 603 env->cp15.hcr_el2 |= HCR_RW; 604 env->pstate = PSTATE_MODE_EL2h; 605 } else { 606 env->pstate = PSTATE_MODE_EL1h; 607 } 608 } 609 610 /* Set to non-secure if not a secure boot */ 611 if (!info->secure_boot && 612 (cs != first_cpu || !info->secure_board_setup)) { 613 /* Linux expects non-secure state */ 614 env->cp15.scr_el3 |= SCR_NS; 615 } 616 } 617 618 if (cs == first_cpu) { 619 cpu_set_pc(cs, info->loader_start); 620 621 if (!have_dtb(info)) { 622 if (old_param) { 623 set_kernel_args_old(info); 624 } else { 625 set_kernel_args(info); 626 } 627 } 628 } else { 629 info->secondary_cpu_reset_hook(cpu, info); 630 } 631 } 632 } 633 } 634 635 /** 636 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 637 * by key. 638 * @fw_cfg: The firmware config instance to store the data in. 639 * @size_key: The firmware config key to store the size of the loaded 640 * data under, with fw_cfg_add_i32(). 641 * @data_key: The firmware config key to store the loaded data under, 642 * with fw_cfg_add_bytes(). 643 * @image_name: The name of the image file to load. If it is NULL, the 644 * function returns without doing anything. 645 * @try_decompress: Whether the image should be decompressed (gunzipped) before 646 * adding it to fw_cfg. If decompression fails, the image is 647 * loaded as-is. 648 * 649 * In case of failure, the function prints an error message to stderr and the 650 * process exits with status 1. 651 */ 652 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 653 uint16_t data_key, const char *image_name, 654 bool try_decompress) 655 { 656 size_t size = -1; 657 uint8_t *data; 658 659 if (image_name == NULL) { 660 return; 661 } 662 663 if (try_decompress) { 664 size = load_image_gzipped_buffer(image_name, 665 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 666 } 667 668 if (size == (size_t)-1) { 669 gchar *contents; 670 gsize length; 671 672 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 673 fprintf(stderr, "failed to load \"%s\"\n", image_name); 674 exit(1); 675 } 676 size = length; 677 data = (uint8_t *)contents; 678 } 679 680 fw_cfg_add_i32(fw_cfg, size_key, size); 681 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 682 } 683 684 static int do_arm_linux_init(Object *obj, void *opaque) 685 { 686 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 687 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 688 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 689 struct arm_boot_info *info = opaque; 690 691 if (albifc->arm_linux_init) { 692 albifc->arm_linux_init(albif, info->secure_boot); 693 } 694 } 695 return 0; 696 } 697 698 static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 699 uint64_t *lowaddr, uint64_t *highaddr, 700 int elf_machine) 701 { 702 bool elf_is64; 703 union { 704 Elf32_Ehdr h32; 705 Elf64_Ehdr h64; 706 } elf_header; 707 int data_swab = 0; 708 bool big_endian; 709 uint64_t ret = -1; 710 Error *err = NULL; 711 712 713 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 714 if (err) { 715 return ret; 716 } 717 718 if (elf_is64) { 719 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 720 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 721 : ARM_ENDIANNESS_LE; 722 } else { 723 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 724 if (big_endian) { 725 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 726 info->endianness = ARM_ENDIANNESS_BE8; 727 } else { 728 info->endianness = ARM_ENDIANNESS_BE32; 729 /* In BE32, the CPU has a different view of the per-byte 730 * address map than the rest of the system. BE32 ELF files 731 * are organised such that they can be programmed through 732 * the CPU's per-word byte-reversed view of the world. QEMU 733 * however loads ELF files independently of the CPU. So 734 * tell the ELF loader to byte reverse the data for us. 735 */ 736 data_swab = 2; 737 } 738 } else { 739 info->endianness = ARM_ENDIANNESS_LE; 740 } 741 } 742 743 ret = load_elf(info->kernel_filename, NULL, NULL, 744 pentry, lowaddr, highaddr, big_endian, elf_machine, 745 1, data_swab); 746 if (ret <= 0) { 747 /* The header loaded but the image didn't */ 748 exit(1); 749 } 750 751 return ret; 752 } 753 754 static void arm_load_kernel_notify(Notifier *notifier, void *data) 755 { 756 CPUState *cs; 757 int kernel_size; 758 int initrd_size; 759 int is_linux = 0; 760 uint64_t elf_entry, elf_low_addr, elf_high_addr; 761 int elf_machine; 762 hwaddr entry, kernel_load_offset; 763 static const ARMInsnFixup *primary_loader; 764 ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier, 765 notifier, notifier); 766 ARMCPU *cpu = n->cpu; 767 struct arm_boot_info *info = 768 container_of(n, struct arm_boot_info, load_kernel_notifier); 769 770 /* The board code is not supposed to set secure_board_setup unless 771 * running its code in secure mode is actually possible, and KVM 772 * doesn't support secure. 773 */ 774 assert(!(info->secure_board_setup && kvm_enabled())); 775 776 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 777 778 /* Load the kernel. */ 779 if (!info->kernel_filename || info->firmware_loaded) { 780 781 if (have_dtb(info)) { 782 /* If we have a device tree blob, but no kernel to supply it to (or 783 * the kernel is supposed to be loaded by the bootloader), copy the 784 * DTB to the base of RAM for the bootloader to pick up. 785 */ 786 if (load_dtb(info->loader_start, info, 0) < 0) { 787 exit(1); 788 } 789 } 790 791 if (info->kernel_filename) { 792 FWCfgState *fw_cfg; 793 bool try_decompressing_kernel; 794 795 fw_cfg = fw_cfg_find(); 796 try_decompressing_kernel = arm_feature(&cpu->env, 797 ARM_FEATURE_AARCH64); 798 799 /* Expose the kernel, the command line, and the initrd in fw_cfg. 800 * We don't process them here at all, it's all left to the 801 * firmware. 802 */ 803 load_image_to_fw_cfg(fw_cfg, 804 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 805 info->kernel_filename, 806 try_decompressing_kernel); 807 load_image_to_fw_cfg(fw_cfg, 808 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 809 info->initrd_filename, false); 810 811 if (info->kernel_cmdline) { 812 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 813 strlen(info->kernel_cmdline) + 1); 814 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 815 info->kernel_cmdline); 816 } 817 } 818 819 /* We will start from address 0 (typically a boot ROM image) in the 820 * same way as hardware. 821 */ 822 return; 823 } 824 825 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 826 primary_loader = bootloader_aarch64; 827 kernel_load_offset = KERNEL64_LOAD_ADDR; 828 elf_machine = EM_AARCH64; 829 } else { 830 primary_loader = bootloader; 831 if (!info->write_board_setup) { 832 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 833 } 834 kernel_load_offset = KERNEL_LOAD_ADDR; 835 elf_machine = EM_ARM; 836 } 837 838 if (!info->secondary_cpu_reset_hook) { 839 info->secondary_cpu_reset_hook = default_reset_secondary; 840 } 841 if (!info->write_secondary_boot) { 842 info->write_secondary_boot = default_write_secondary; 843 } 844 845 if (info->nb_cpus == 0) 846 info->nb_cpus = 1; 847 848 /* We want to put the initrd far enough into RAM that when the 849 * kernel is uncompressed it will not clobber the initrd. However 850 * on boards without much RAM we must ensure that we still leave 851 * enough room for a decent sized initrd, and on boards with large 852 * amounts of RAM we must avoid the initrd being so far up in RAM 853 * that it is outside lowmem and inaccessible to the kernel. 854 * So for boards with less than 256MB of RAM we put the initrd 855 * halfway into RAM, and for boards with 256MB of RAM or more we put 856 * the initrd at 128MB. 857 */ 858 info->initrd_start = info->loader_start + 859 MIN(info->ram_size / 2, 128 * 1024 * 1024); 860 861 /* Assume that raw images are linux kernels, and ELF images are not. */ 862 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, 863 &elf_high_addr, elf_machine); 864 if (kernel_size > 0 && have_dtb(info)) { 865 /* If there is still some room left at the base of RAM, try and put 866 * the DTB there like we do for images loaded with -bios or -pflash. 867 */ 868 if (elf_low_addr > info->loader_start 869 || elf_high_addr < info->loader_start) { 870 /* Pass elf_low_addr as address limit to load_dtb if it may be 871 * pointing into RAM, otherwise pass '0' (no limit) 872 */ 873 if (elf_low_addr < info->loader_start) { 874 elf_low_addr = 0; 875 } 876 if (load_dtb(info->loader_start, info, elf_low_addr) < 0) { 877 exit(1); 878 } 879 } 880 } 881 entry = elf_entry; 882 if (kernel_size < 0) { 883 kernel_size = load_uimage(info->kernel_filename, &entry, NULL, 884 &is_linux, NULL, NULL); 885 } 886 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 887 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 888 entry = info->loader_start + kernel_load_offset; 889 kernel_size = load_image_gzipped(info->kernel_filename, entry, 890 info->ram_size - kernel_load_offset); 891 is_linux = 1; 892 } 893 if (kernel_size < 0) { 894 entry = info->loader_start + kernel_load_offset; 895 kernel_size = load_image_targphys(info->kernel_filename, entry, 896 info->ram_size - kernel_load_offset); 897 is_linux = 1; 898 } 899 if (kernel_size < 0) { 900 fprintf(stderr, "qemu: could not load kernel '%s'\n", 901 info->kernel_filename); 902 exit(1); 903 } 904 info->entry = entry; 905 if (is_linux) { 906 uint32_t fixupcontext[FIXUP_MAX]; 907 908 if (info->initrd_filename) { 909 initrd_size = load_ramdisk(info->initrd_filename, 910 info->initrd_start, 911 info->ram_size - 912 info->initrd_start); 913 if (initrd_size < 0) { 914 initrd_size = load_image_targphys(info->initrd_filename, 915 info->initrd_start, 916 info->ram_size - 917 info->initrd_start); 918 } 919 if (initrd_size < 0) { 920 fprintf(stderr, "qemu: could not load initrd '%s'\n", 921 info->initrd_filename); 922 exit(1); 923 } 924 } else { 925 initrd_size = 0; 926 } 927 info->initrd_size = initrd_size; 928 929 fixupcontext[FIXUP_BOARDID] = info->board_id; 930 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 931 932 /* for device tree boot, we pass the DTB directly in r2. Otherwise 933 * we point to the kernel args. 934 */ 935 if (have_dtb(info)) { 936 hwaddr align; 937 hwaddr dtb_start; 938 939 if (elf_machine == EM_AARCH64) { 940 /* 941 * Some AArch64 kernels on early bootup map the fdt region as 942 * 943 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 944 * 945 * Let's play safe and prealign it to 2MB to give us some space. 946 */ 947 align = 2 * 1024 * 1024; 948 } else { 949 /* 950 * Some 32bit kernels will trash anything in the 4K page the 951 * initrd ends in, so make sure the DTB isn't caught up in that. 952 */ 953 align = 4096; 954 } 955 956 /* Place the DTB after the initrd in memory with alignment. */ 957 dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); 958 if (load_dtb(dtb_start, info, 0) < 0) { 959 exit(1); 960 } 961 fixupcontext[FIXUP_ARGPTR] = dtb_start; 962 } else { 963 fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR; 964 if (info->ram_size >= (1ULL << 32)) { 965 fprintf(stderr, "qemu: RAM size must be less than 4GB to boot" 966 " Linux kernel using ATAGS (try passing a device tree" 967 " using -dtb)\n"); 968 exit(1); 969 } 970 } 971 fixupcontext[FIXUP_ENTRYPOINT] = entry; 972 973 write_bootloader("bootloader", info->loader_start, 974 primary_loader, fixupcontext); 975 976 if (info->nb_cpus > 1) { 977 info->write_secondary_boot(cpu, info); 978 } 979 if (info->write_board_setup) { 980 info->write_board_setup(cpu, info); 981 } 982 983 /* Notify devices which need to fake up firmware initialization 984 * that we're doing a direct kernel boot. 985 */ 986 object_child_foreach_recursive(object_get_root(), 987 do_arm_linux_init, info); 988 } 989 info->is_linux = is_linux; 990 991 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { 992 ARM_CPU(cs)->env.boot_info = info; 993 } 994 } 995 996 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 997 { 998 CPUState *cs; 999 1000 info->load_kernel_notifier.cpu = cpu; 1001 info->load_kernel_notifier.notifier.notify = arm_load_kernel_notify; 1002 qemu_add_machine_init_done_notifier(&info->load_kernel_notifier.notifier); 1003 1004 /* CPU objects (unlike devices) are not automatically reset on system 1005 * reset, so we must always register a handler to do so. If we're 1006 * actually loading a kernel, the handler is also responsible for 1007 * arranging that we start it correctly. 1008 */ 1009 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { 1010 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1011 } 1012 } 1013 1014 static const TypeInfo arm_linux_boot_if_info = { 1015 .name = TYPE_ARM_LINUX_BOOT_IF, 1016 .parent = TYPE_INTERFACE, 1017 .class_size = sizeof(ARMLinuxBootIfClass), 1018 }; 1019 1020 static void arm_linux_boot_register_types(void) 1021 { 1022 type_register_static(&arm_linux_boot_if_info); 1023 } 1024 1025 type_init(arm_linux_boot_register_types) 1026