1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/error-report.h" 12 #include "qapi/error.h" 13 #include <libfdt.h> 14 #include "hw/hw.h" 15 #include "hw/arm/boot.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "sysemu/kvm.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/numa.h" 20 #include "hw/boards.h" 21 #include "hw/loader.h" 22 #include "elf.h" 23 #include "sysemu/device_tree.h" 24 #include "qemu/config-file.h" 25 #include "qemu/option.h" 26 #include "exec/address-spaces.h" 27 #include "qemu/units.h" 28 29 /* Kernel boot protocol is specified in the kernel docs 30 * Documentation/arm/Booting and Documentation/arm64/booting.txt 31 * They have different preferred image load offsets from system RAM base. 32 */ 33 #define KERNEL_ARGS_ADDR 0x100 34 #define KERNEL_NOLOAD_ADDR 0x02000000 35 #define KERNEL_LOAD_ADDR 0x00010000 36 #define KERNEL64_LOAD_ADDR 0x00080000 37 38 #define ARM64_TEXT_OFFSET_OFFSET 8 39 #define ARM64_MAGIC_OFFSET 56 40 41 #define BOOTLOADER_MAX_SIZE (4 * KiB) 42 43 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 44 const struct arm_boot_info *info) 45 { 46 /* Return the address space to use for bootloader reads and writes. 47 * We prefer the secure address space if the CPU has it and we're 48 * going to boot the guest into it. 49 */ 50 int asidx; 51 CPUState *cs = CPU(cpu); 52 53 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 54 asidx = ARMASIdx_S; 55 } else { 56 asidx = ARMASIdx_NS; 57 } 58 59 return cpu_get_address_space(cs, asidx); 60 } 61 62 typedef enum { 63 FIXUP_NONE = 0, /* do nothing */ 64 FIXUP_TERMINATOR, /* end of insns */ 65 FIXUP_BOARDID, /* overwrite with board ID number */ 66 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 67 FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */ 68 FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */ 69 FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */ 70 FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */ 71 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 72 FIXUP_BOOTREG, /* overwrite with boot register address */ 73 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 74 FIXUP_MAX, 75 } FixupType; 76 77 typedef struct ARMInsnFixup { 78 uint32_t insn; 79 FixupType fixup; 80 } ARMInsnFixup; 81 82 static const ARMInsnFixup bootloader_aarch64[] = { 83 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 84 { 0xaa1f03e1 }, /* mov x1, xzr */ 85 { 0xaa1f03e2 }, /* mov x2, xzr */ 86 { 0xaa1f03e3 }, /* mov x3, xzr */ 87 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 88 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 89 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ 90 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ 91 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ 92 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ 93 { 0, FIXUP_TERMINATOR } 94 }; 95 96 /* A very small bootloader: call the board-setup code (if needed), 97 * set r0-r2, then jump to the kernel. 98 * If we're not calling boot setup code then we don't copy across 99 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 100 */ 101 102 static const ARMInsnFixup bootloader[] = { 103 { 0xe28fe004 }, /* add lr, pc, #4 */ 104 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 105 { 0, FIXUP_BOARD_SETUP }, 106 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 107 { 0xe3a00000 }, /* mov r0, #0 */ 108 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 109 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 110 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 111 { 0, FIXUP_BOARDID }, 112 { 0, FIXUP_ARGPTR_LO }, 113 { 0, FIXUP_ENTRYPOINT_LO }, 114 { 0, FIXUP_TERMINATOR } 115 }; 116 117 /* Handling for secondary CPU boot in a multicore system. 118 * Unlike the uniprocessor/primary CPU boot, this is platform 119 * dependent. The default code here is based on the secondary 120 * CPU boot protocol used on realview/vexpress boards, with 121 * some parameterisation to increase its flexibility. 122 * QEMU platform models for which this code is not appropriate 123 * should override write_secondary_boot and secondary_cpu_reset_hook 124 * instead. 125 * 126 * This code enables the interrupt controllers for the secondary 127 * CPUs and then puts all the secondary CPUs into a loop waiting 128 * for an interprocessor interrupt and polling a configurable 129 * location for the kernel secondary CPU entry point. 130 */ 131 #define DSB_INSN 0xf57ff04f 132 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 133 134 static const ARMInsnFixup smpboot[] = { 135 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 136 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 137 { 0xe3a01001 }, /* mov r1, #1 */ 138 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 139 { 0xe3a010ff }, /* mov r1, #0xff */ 140 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 141 { 0, FIXUP_DSB }, /* dsb */ 142 { 0xe320f003 }, /* wfi */ 143 { 0xe5901000 }, /* ldr r1, [r0] */ 144 { 0xe1110001 }, /* tst r1, r1 */ 145 { 0x0afffffb }, /* beq <wfi> */ 146 { 0xe12fff11 }, /* bx r1 */ 147 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 148 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 149 { 0, FIXUP_TERMINATOR } 150 }; 151 152 static void write_bootloader(const char *name, hwaddr addr, 153 const ARMInsnFixup *insns, uint32_t *fixupcontext, 154 AddressSpace *as) 155 { 156 /* Fix up the specified bootloader fragment and write it into 157 * guest memory using rom_add_blob_fixed(). fixupcontext is 158 * an array giving the values to write in for the fixup types 159 * which write a value into the code array. 160 */ 161 int i, len; 162 uint32_t *code; 163 164 len = 0; 165 while (insns[len].fixup != FIXUP_TERMINATOR) { 166 len++; 167 } 168 169 code = g_new0(uint32_t, len); 170 171 for (i = 0; i < len; i++) { 172 uint32_t insn = insns[i].insn; 173 FixupType fixup = insns[i].fixup; 174 175 switch (fixup) { 176 case FIXUP_NONE: 177 break; 178 case FIXUP_BOARDID: 179 case FIXUP_BOARD_SETUP: 180 case FIXUP_ARGPTR_LO: 181 case FIXUP_ARGPTR_HI: 182 case FIXUP_ENTRYPOINT_LO: 183 case FIXUP_ENTRYPOINT_HI: 184 case FIXUP_GIC_CPU_IF: 185 case FIXUP_BOOTREG: 186 case FIXUP_DSB: 187 insn = fixupcontext[fixup]; 188 break; 189 default: 190 abort(); 191 } 192 code[i] = tswap32(insn); 193 } 194 195 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 196 197 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 198 199 g_free(code); 200 } 201 202 static void default_write_secondary(ARMCPU *cpu, 203 const struct arm_boot_info *info) 204 { 205 uint32_t fixupcontext[FIXUP_MAX]; 206 AddressSpace *as = arm_boot_address_space(cpu, info); 207 208 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 209 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 210 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 211 fixupcontext[FIXUP_DSB] = DSB_INSN; 212 } else { 213 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 214 } 215 216 write_bootloader("smpboot", info->smp_loader_start, 217 smpboot, fixupcontext, as); 218 } 219 220 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 221 const struct arm_boot_info *info, 222 hwaddr mvbar_addr) 223 { 224 AddressSpace *as = arm_boot_address_space(cpu, info); 225 int n; 226 uint32_t mvbar_blob[] = { 227 /* mvbar_addr: secure monitor vectors 228 * Default unimplemented and unused vectors to spin. Makes it 229 * easier to debug (as opposed to the CPU running away). 230 */ 231 0xeafffffe, /* (spin) */ 232 0xeafffffe, /* (spin) */ 233 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 234 0xeafffffe, /* (spin) */ 235 0xeafffffe, /* (spin) */ 236 0xeafffffe, /* (spin) */ 237 0xeafffffe, /* (spin) */ 238 0xeafffffe, /* (spin) */ 239 }; 240 uint32_t board_setup_blob[] = { 241 /* board setup addr */ 242 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 243 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 244 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 245 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 246 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 247 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 248 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 249 0xe1a0f001, /* mov pc, r1 ;return */ 250 }; 251 252 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 253 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 254 255 /* check that these blobs don't overlap */ 256 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 257 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 258 259 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 260 mvbar_blob[n] = tswap32(mvbar_blob[n]); 261 } 262 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 263 mvbar_addr, as); 264 265 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 266 board_setup_blob[n] = tswap32(board_setup_blob[n]); 267 } 268 rom_add_blob_fixed_as("board-setup", board_setup_blob, 269 sizeof(board_setup_blob), info->board_setup_addr, as); 270 } 271 272 static void default_reset_secondary(ARMCPU *cpu, 273 const struct arm_boot_info *info) 274 { 275 AddressSpace *as = arm_boot_address_space(cpu, info); 276 CPUState *cs = CPU(cpu); 277 278 address_space_stl_notdirty(as, info->smp_bootreg_addr, 279 0, MEMTXATTRS_UNSPECIFIED, NULL); 280 cpu_set_pc(cs, info->smp_loader_start); 281 } 282 283 static inline bool have_dtb(const struct arm_boot_info *info) 284 { 285 return info->dtb_filename || info->get_dtb; 286 } 287 288 #define WRITE_WORD(p, value) do { \ 289 address_space_stl_notdirty(as, p, value, \ 290 MEMTXATTRS_UNSPECIFIED, NULL); \ 291 p += 4; \ 292 } while (0) 293 294 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 295 { 296 int initrd_size = info->initrd_size; 297 hwaddr base = info->loader_start; 298 hwaddr p; 299 300 p = base + KERNEL_ARGS_ADDR; 301 /* ATAG_CORE */ 302 WRITE_WORD(p, 5); 303 WRITE_WORD(p, 0x54410001); 304 WRITE_WORD(p, 1); 305 WRITE_WORD(p, 0x1000); 306 WRITE_WORD(p, 0); 307 /* ATAG_MEM */ 308 /* TODO: handle multiple chips on one ATAG list */ 309 WRITE_WORD(p, 4); 310 WRITE_WORD(p, 0x54410002); 311 WRITE_WORD(p, info->ram_size); 312 WRITE_WORD(p, info->loader_start); 313 if (initrd_size) { 314 /* ATAG_INITRD2 */ 315 WRITE_WORD(p, 4); 316 WRITE_WORD(p, 0x54420005); 317 WRITE_WORD(p, info->initrd_start); 318 WRITE_WORD(p, initrd_size); 319 } 320 if (info->kernel_cmdline && *info->kernel_cmdline) { 321 /* ATAG_CMDLINE */ 322 int cmdline_size; 323 324 cmdline_size = strlen(info->kernel_cmdline); 325 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 326 (const uint8_t *)info->kernel_cmdline, 327 cmdline_size + 1); 328 cmdline_size = (cmdline_size >> 2) + 1; 329 WRITE_WORD(p, cmdline_size + 2); 330 WRITE_WORD(p, 0x54410009); 331 p += cmdline_size * 4; 332 } 333 if (info->atag_board) { 334 /* ATAG_BOARD */ 335 int atag_board_len; 336 uint8_t atag_board_buf[0x1000]; 337 338 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 339 WRITE_WORD(p, (atag_board_len + 8) >> 2); 340 WRITE_WORD(p, 0x414f4d50); 341 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 342 atag_board_buf, atag_board_len); 343 p += atag_board_len; 344 } 345 /* ATAG_END */ 346 WRITE_WORD(p, 0); 347 WRITE_WORD(p, 0); 348 } 349 350 static void set_kernel_args_old(const struct arm_boot_info *info, 351 AddressSpace *as) 352 { 353 hwaddr p; 354 const char *s; 355 int initrd_size = info->initrd_size; 356 hwaddr base = info->loader_start; 357 358 /* see linux/include/asm-arm/setup.h */ 359 p = base + KERNEL_ARGS_ADDR; 360 /* page_size */ 361 WRITE_WORD(p, 4096); 362 /* nr_pages */ 363 WRITE_WORD(p, info->ram_size / 4096); 364 /* ramdisk_size */ 365 WRITE_WORD(p, 0); 366 #define FLAG_READONLY 1 367 #define FLAG_RDLOAD 4 368 #define FLAG_RDPROMPT 8 369 /* flags */ 370 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 371 /* rootdev */ 372 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 373 /* video_num_cols */ 374 WRITE_WORD(p, 0); 375 /* video_num_rows */ 376 WRITE_WORD(p, 0); 377 /* video_x */ 378 WRITE_WORD(p, 0); 379 /* video_y */ 380 WRITE_WORD(p, 0); 381 /* memc_control_reg */ 382 WRITE_WORD(p, 0); 383 /* unsigned char sounddefault */ 384 /* unsigned char adfsdrives */ 385 /* unsigned char bytes_per_char_h */ 386 /* unsigned char bytes_per_char_v */ 387 WRITE_WORD(p, 0); 388 /* pages_in_bank[4] */ 389 WRITE_WORD(p, 0); 390 WRITE_WORD(p, 0); 391 WRITE_WORD(p, 0); 392 WRITE_WORD(p, 0); 393 /* pages_in_vram */ 394 WRITE_WORD(p, 0); 395 /* initrd_start */ 396 if (initrd_size) { 397 WRITE_WORD(p, info->initrd_start); 398 } else { 399 WRITE_WORD(p, 0); 400 } 401 /* initrd_size */ 402 WRITE_WORD(p, initrd_size); 403 /* rd_start */ 404 WRITE_WORD(p, 0); 405 /* system_rev */ 406 WRITE_WORD(p, 0); 407 /* system_serial_low */ 408 WRITE_WORD(p, 0); 409 /* system_serial_high */ 410 WRITE_WORD(p, 0); 411 /* mem_fclk_21285 */ 412 WRITE_WORD(p, 0); 413 /* zero unused fields */ 414 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 415 WRITE_WORD(p, 0); 416 } 417 s = info->kernel_cmdline; 418 if (s) { 419 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 420 (const uint8_t *)s, strlen(s) + 1); 421 } else { 422 WRITE_WORD(p, 0); 423 } 424 } 425 426 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, 427 uint32_t scells, hwaddr mem_len, 428 int numa_node_id) 429 { 430 char *nodename; 431 int ret; 432 433 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 434 qemu_fdt_add_subnode(fdt, nodename); 435 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 436 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base, 437 scells, mem_len); 438 if (ret < 0) { 439 goto out; 440 } 441 442 /* only set the NUMA ID if it is specified */ 443 if (numa_node_id >= 0) { 444 ret = qemu_fdt_setprop_cell(fdt, nodename, 445 "numa-node-id", numa_node_id); 446 } 447 out: 448 g_free(nodename); 449 return ret; 450 } 451 452 static void fdt_add_psci_node(void *fdt) 453 { 454 uint32_t cpu_suspend_fn; 455 uint32_t cpu_off_fn; 456 uint32_t cpu_on_fn; 457 uint32_t migrate_fn; 458 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 459 const char *psci_method; 460 int64_t psci_conduit; 461 int rc; 462 463 psci_conduit = object_property_get_int(OBJECT(armcpu), 464 "psci-conduit", 465 &error_abort); 466 switch (psci_conduit) { 467 case QEMU_PSCI_CONDUIT_DISABLED: 468 return; 469 case QEMU_PSCI_CONDUIT_HVC: 470 psci_method = "hvc"; 471 break; 472 case QEMU_PSCI_CONDUIT_SMC: 473 psci_method = "smc"; 474 break; 475 default: 476 g_assert_not_reached(); 477 } 478 479 /* 480 * If /psci node is present in provided DTB, assume that no fixup 481 * is necessary and all PSCI configuration should be taken as-is 482 */ 483 rc = fdt_path_offset(fdt, "/psci"); 484 if (rc >= 0) { 485 return; 486 } 487 488 qemu_fdt_add_subnode(fdt, "/psci"); 489 if (armcpu->psci_version == 2) { 490 const char comp[] = "arm,psci-0.2\0arm,psci"; 491 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 492 493 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 494 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 495 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 496 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 497 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 498 } else { 499 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 500 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 501 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 502 } 503 } else { 504 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 505 506 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 507 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 508 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 509 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 510 } 511 512 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 513 * to the instruction that should be used to invoke PSCI functions. 514 * However, the device tree binding uses 'method' instead, so that is 515 * what we should use here. 516 */ 517 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 518 519 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 520 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 521 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 522 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 523 } 524 525 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 526 hwaddr addr_limit, AddressSpace *as) 527 { 528 void *fdt = NULL; 529 int size, rc, n = 0; 530 uint32_t acells, scells; 531 unsigned int i; 532 hwaddr mem_base, mem_len; 533 char **node_path; 534 Error *err = NULL; 535 536 if (binfo->dtb_filename) { 537 char *filename; 538 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 539 if (!filename) { 540 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 541 goto fail; 542 } 543 544 fdt = load_device_tree(filename, &size); 545 if (!fdt) { 546 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 547 g_free(filename); 548 goto fail; 549 } 550 g_free(filename); 551 } else { 552 fdt = binfo->get_dtb(binfo, &size); 553 if (!fdt) { 554 fprintf(stderr, "Board was unable to create a dtb blob\n"); 555 goto fail; 556 } 557 } 558 559 if (addr_limit > addr && size > (addr_limit - addr)) { 560 /* Installing the device tree blob at addr would exceed addr_limit. 561 * Whether this constitutes failure is up to the caller to decide, 562 * so just return 0 as size, i.e., no error. 563 */ 564 g_free(fdt); 565 return 0; 566 } 567 568 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 569 NULL, &error_fatal); 570 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 571 NULL, &error_fatal); 572 if (acells == 0 || scells == 0) { 573 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 574 goto fail; 575 } 576 577 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { 578 /* This is user error so deserves a friendlier error message 579 * than the failure of setprop_sized_cells would provide 580 */ 581 fprintf(stderr, "qemu: dtb file not compatible with " 582 "RAM size > 4GB\n"); 583 goto fail; 584 } 585 586 /* nop all root nodes matching /memory or /memory@unit-address */ 587 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 588 if (err) { 589 error_report_err(err); 590 goto fail; 591 } 592 while (node_path[n]) { 593 if (g_str_has_prefix(node_path[n], "/memory")) { 594 qemu_fdt_nop_node(fdt, node_path[n]); 595 } 596 n++; 597 } 598 g_strfreev(node_path); 599 600 if (nb_numa_nodes > 0) { 601 mem_base = binfo->loader_start; 602 for (i = 0; i < nb_numa_nodes; i++) { 603 mem_len = numa_info[i].node_mem; 604 rc = fdt_add_memory_node(fdt, acells, mem_base, 605 scells, mem_len, i); 606 if (rc < 0) { 607 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 608 mem_base); 609 goto fail; 610 } 611 612 mem_base += mem_len; 613 } 614 } else { 615 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start, 616 scells, binfo->ram_size, -1); 617 if (rc < 0) { 618 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 619 binfo->loader_start); 620 goto fail; 621 } 622 } 623 624 rc = fdt_path_offset(fdt, "/chosen"); 625 if (rc < 0) { 626 qemu_fdt_add_subnode(fdt, "/chosen"); 627 } 628 629 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { 630 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 631 binfo->kernel_cmdline); 632 if (rc < 0) { 633 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 634 goto fail; 635 } 636 } 637 638 if (binfo->initrd_size) { 639 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 640 binfo->initrd_start); 641 if (rc < 0) { 642 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 643 goto fail; 644 } 645 646 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 647 binfo->initrd_start + binfo->initrd_size); 648 if (rc < 0) { 649 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 650 goto fail; 651 } 652 } 653 654 fdt_add_psci_node(fdt); 655 656 if (binfo->modify_dtb) { 657 binfo->modify_dtb(binfo, fdt); 658 } 659 660 qemu_fdt_dumpdtb(fdt, size); 661 662 /* Put the DTB into the memory map as a ROM image: this will ensure 663 * the DTB is copied again upon reset, even if addr points into RAM. 664 */ 665 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 666 667 g_free(fdt); 668 669 return size; 670 671 fail: 672 g_free(fdt); 673 return -1; 674 } 675 676 static void do_cpu_reset(void *opaque) 677 { 678 ARMCPU *cpu = opaque; 679 CPUState *cs = CPU(cpu); 680 CPUARMState *env = &cpu->env; 681 const struct arm_boot_info *info = env->boot_info; 682 683 cpu_reset(cs); 684 if (info) { 685 if (!info->is_linux) { 686 int i; 687 /* Jump to the entry point. */ 688 uint64_t entry = info->entry; 689 690 switch (info->endianness) { 691 case ARM_ENDIANNESS_LE: 692 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 693 for (i = 1; i < 4; ++i) { 694 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 695 } 696 env->uncached_cpsr &= ~CPSR_E; 697 break; 698 case ARM_ENDIANNESS_BE8: 699 env->cp15.sctlr_el[1] |= SCTLR_E0E; 700 for (i = 1; i < 4; ++i) { 701 env->cp15.sctlr_el[i] |= SCTLR_EE; 702 } 703 env->uncached_cpsr |= CPSR_E; 704 break; 705 case ARM_ENDIANNESS_BE32: 706 env->cp15.sctlr_el[1] |= SCTLR_B; 707 break; 708 case ARM_ENDIANNESS_UNKNOWN: 709 break; /* Board's decision */ 710 default: 711 g_assert_not_reached(); 712 } 713 714 cpu_set_pc(cs, entry); 715 } else { 716 /* If we are booting Linux then we need to check whether we are 717 * booting into secure or non-secure state and adjust the state 718 * accordingly. Out of reset, ARM is defined to be in secure state 719 * (SCR.NS = 0), we change that here if non-secure boot has been 720 * requested. 721 */ 722 if (arm_feature(env, ARM_FEATURE_EL3)) { 723 /* AArch64 is defined to come out of reset into EL3 if enabled. 724 * If we are booting Linux then we need to adjust our EL as 725 * Linux expects us to be in EL2 or EL1. AArch32 resets into 726 * SVC, which Linux expects, so no privilege/exception level to 727 * adjust. 728 */ 729 if (env->aarch64) { 730 env->cp15.scr_el3 |= SCR_RW; 731 if (arm_feature(env, ARM_FEATURE_EL2)) { 732 env->cp15.hcr_el2 |= HCR_RW; 733 env->pstate = PSTATE_MODE_EL2h; 734 } else { 735 env->pstate = PSTATE_MODE_EL1h; 736 } 737 /* AArch64 kernels never boot in secure mode */ 738 assert(!info->secure_boot); 739 /* This hook is only supported for AArch32 currently: 740 * bootloader_aarch64[] will not call the hook, and 741 * the code above has already dropped us into EL2 or EL1. 742 */ 743 assert(!info->secure_board_setup); 744 } 745 746 if (arm_feature(env, ARM_FEATURE_EL2)) { 747 /* If we have EL2 then Linux expects the HVC insn to work */ 748 env->cp15.scr_el3 |= SCR_HCE; 749 } 750 751 /* Set to non-secure if not a secure boot */ 752 if (!info->secure_boot && 753 (cs != first_cpu || !info->secure_board_setup)) { 754 /* Linux expects non-secure state */ 755 env->cp15.scr_el3 |= SCR_NS; 756 } 757 } 758 759 if (!env->aarch64 && !info->secure_boot && 760 arm_feature(env, ARM_FEATURE_EL2)) { 761 /* 762 * This is an AArch32 boot not to Secure state, and 763 * we have Hyp mode available, so boot the kernel into 764 * Hyp mode. This is not how the CPU comes out of reset, 765 * so we need to manually put it there. 766 */ 767 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw); 768 } 769 770 if (cs == first_cpu) { 771 AddressSpace *as = arm_boot_address_space(cpu, info); 772 773 cpu_set_pc(cs, info->loader_start); 774 775 if (!have_dtb(info)) { 776 if (old_param) { 777 set_kernel_args_old(info, as); 778 } else { 779 set_kernel_args(info, as); 780 } 781 } 782 } else { 783 info->secondary_cpu_reset_hook(cpu, info); 784 } 785 } 786 } 787 } 788 789 /** 790 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 791 * by key. 792 * @fw_cfg: The firmware config instance to store the data in. 793 * @size_key: The firmware config key to store the size of the loaded 794 * data under, with fw_cfg_add_i32(). 795 * @data_key: The firmware config key to store the loaded data under, 796 * with fw_cfg_add_bytes(). 797 * @image_name: The name of the image file to load. If it is NULL, the 798 * function returns without doing anything. 799 * @try_decompress: Whether the image should be decompressed (gunzipped) before 800 * adding it to fw_cfg. If decompression fails, the image is 801 * loaded as-is. 802 * 803 * In case of failure, the function prints an error message to stderr and the 804 * process exits with status 1. 805 */ 806 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 807 uint16_t data_key, const char *image_name, 808 bool try_decompress) 809 { 810 size_t size = -1; 811 uint8_t *data; 812 813 if (image_name == NULL) { 814 return; 815 } 816 817 if (try_decompress) { 818 size = load_image_gzipped_buffer(image_name, 819 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 820 } 821 822 if (size == (size_t)-1) { 823 gchar *contents; 824 gsize length; 825 826 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 827 error_report("failed to load \"%s\"", image_name); 828 exit(1); 829 } 830 size = length; 831 data = (uint8_t *)contents; 832 } 833 834 fw_cfg_add_i32(fw_cfg, size_key, size); 835 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 836 } 837 838 static int do_arm_linux_init(Object *obj, void *opaque) 839 { 840 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 841 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 842 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 843 struct arm_boot_info *info = opaque; 844 845 if (albifc->arm_linux_init) { 846 albifc->arm_linux_init(albif, info->secure_boot); 847 } 848 } 849 return 0; 850 } 851 852 static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 853 uint64_t *lowaddr, uint64_t *highaddr, 854 int elf_machine, AddressSpace *as) 855 { 856 bool elf_is64; 857 union { 858 Elf32_Ehdr h32; 859 Elf64_Ehdr h64; 860 } elf_header; 861 int data_swab = 0; 862 bool big_endian; 863 int64_t ret = -1; 864 Error *err = NULL; 865 866 867 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 868 if (err) { 869 error_free(err); 870 return ret; 871 } 872 873 if (elf_is64) { 874 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 875 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 876 : ARM_ENDIANNESS_LE; 877 } else { 878 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 879 if (big_endian) { 880 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 881 info->endianness = ARM_ENDIANNESS_BE8; 882 } else { 883 info->endianness = ARM_ENDIANNESS_BE32; 884 /* In BE32, the CPU has a different view of the per-byte 885 * address map than the rest of the system. BE32 ELF files 886 * are organised such that they can be programmed through 887 * the CPU's per-word byte-reversed view of the world. QEMU 888 * however loads ELF files independently of the CPU. So 889 * tell the ELF loader to byte reverse the data for us. 890 */ 891 data_swab = 2; 892 } 893 } else { 894 info->endianness = ARM_ENDIANNESS_LE; 895 } 896 } 897 898 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL, 899 pentry, lowaddr, highaddr, big_endian, elf_machine, 900 1, data_swab, as); 901 if (ret <= 0) { 902 /* The header loaded but the image didn't */ 903 exit(1); 904 } 905 906 return ret; 907 } 908 909 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 910 hwaddr *entry, AddressSpace *as) 911 { 912 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 913 uint8_t *buffer; 914 int size; 915 916 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 917 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 918 &buffer); 919 920 if (size < 0) { 921 gsize len; 922 923 /* Load as raw file otherwise */ 924 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 925 return -1; 926 } 927 size = len; 928 } 929 930 /* check the arm64 magic header value -- very old kernels may not have it */ 931 if (size > ARM64_MAGIC_OFFSET + 4 && 932 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 933 uint64_t hdrvals[2]; 934 935 /* The arm64 Image header has text_offset and image_size fields at 8 and 936 * 16 bytes into the Image header, respectively. The text_offset field 937 * is only valid if the image_size is non-zero. 938 */ 939 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 940 if (hdrvals[1] != 0) { 941 kernel_load_offset = le64_to_cpu(hdrvals[0]); 942 943 /* 944 * We write our startup "bootloader" at the very bottom of RAM, 945 * so that bit can't be used for the image. Luckily the Image 946 * format specification is that the image requests only an offset 947 * from a 2MB boundary, not an absolute load address. So if the 948 * image requests an offset that might mean it overlaps with the 949 * bootloader, we can just load it starting at 2MB+offset rather 950 * than 0MB + offset. 951 */ 952 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 953 kernel_load_offset += 2 * MiB; 954 } 955 } 956 } 957 958 *entry = mem_base + kernel_load_offset; 959 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 960 961 g_free(buffer); 962 963 return size; 964 } 965 966 static void arm_setup_direct_kernel_boot(ARMCPU *cpu, 967 struct arm_boot_info *info) 968 { 969 /* Set up for a direct boot of a kernel image file. */ 970 CPUState *cs; 971 AddressSpace *as = arm_boot_address_space(cpu, info); 972 int kernel_size; 973 int initrd_size; 974 int is_linux = 0; 975 uint64_t elf_entry, elf_low_addr, elf_high_addr; 976 int elf_machine; 977 hwaddr entry; 978 static const ARMInsnFixup *primary_loader; 979 980 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 981 primary_loader = bootloader_aarch64; 982 elf_machine = EM_AARCH64; 983 } else { 984 primary_loader = bootloader; 985 if (!info->write_board_setup) { 986 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 987 } 988 elf_machine = EM_ARM; 989 } 990 991 if (!info->secondary_cpu_reset_hook) { 992 info->secondary_cpu_reset_hook = default_reset_secondary; 993 } 994 if (!info->write_secondary_boot) { 995 info->write_secondary_boot = default_write_secondary; 996 } 997 998 if (info->nb_cpus == 0) 999 info->nb_cpus = 1; 1000 1001 /* 1002 * We want to put the initrd far enough into RAM that when the 1003 * kernel is uncompressed it will not clobber the initrd. However 1004 * on boards without much RAM we must ensure that we still leave 1005 * enough room for a decent sized initrd, and on boards with large 1006 * amounts of RAM we must avoid the initrd being so far up in RAM 1007 * that it is outside lowmem and inaccessible to the kernel. 1008 * So for boards with less than 256MB of RAM we put the initrd 1009 * halfway into RAM, and for boards with 256MB of RAM or more we put 1010 * the initrd at 128MB. 1011 */ 1012 info->initrd_start = info->loader_start + 1013 MIN(info->ram_size / 2, 128 * 1024 * 1024); 1014 1015 /* Assume that raw images are linux kernels, and ELF images are not. */ 1016 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, 1017 &elf_high_addr, elf_machine, as); 1018 if (kernel_size > 0 && have_dtb(info)) { 1019 /* 1020 * If there is still some room left at the base of RAM, try and put 1021 * the DTB there like we do for images loaded with -bios or -pflash. 1022 */ 1023 if (elf_low_addr > info->loader_start 1024 || elf_high_addr < info->loader_start) { 1025 /* 1026 * Set elf_low_addr as address limit for arm_load_dtb if it may be 1027 * pointing into RAM, otherwise pass '0' (no limit) 1028 */ 1029 if (elf_low_addr < info->loader_start) { 1030 elf_low_addr = 0; 1031 } 1032 info->dtb_start = info->loader_start; 1033 info->dtb_limit = elf_low_addr; 1034 } 1035 } 1036 entry = elf_entry; 1037 if (kernel_size < 0) { 1038 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; 1039 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, 1040 &is_linux, NULL, NULL, as); 1041 } 1042 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1043 kernel_size = load_aarch64_image(info->kernel_filename, 1044 info->loader_start, &entry, as); 1045 is_linux = 1; 1046 } else if (kernel_size < 0) { 1047 /* 32-bit ARM */ 1048 entry = info->loader_start + KERNEL_LOAD_ADDR; 1049 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1050 info->ram_size - KERNEL_LOAD_ADDR, 1051 as); 1052 is_linux = 1; 1053 } 1054 if (kernel_size < 0) { 1055 error_report("could not load kernel '%s'", info->kernel_filename); 1056 exit(1); 1057 } 1058 info->entry = entry; 1059 if (is_linux) { 1060 uint32_t fixupcontext[FIXUP_MAX]; 1061 1062 if (info->initrd_filename) { 1063 initrd_size = load_ramdisk_as(info->initrd_filename, 1064 info->initrd_start, 1065 info->ram_size - info->initrd_start, 1066 as); 1067 if (initrd_size < 0) { 1068 initrd_size = load_image_targphys_as(info->initrd_filename, 1069 info->initrd_start, 1070 info->ram_size - 1071 info->initrd_start, 1072 as); 1073 } 1074 if (initrd_size < 0) { 1075 error_report("could not load initrd '%s'", 1076 info->initrd_filename); 1077 exit(1); 1078 } 1079 } else { 1080 initrd_size = 0; 1081 } 1082 info->initrd_size = initrd_size; 1083 1084 fixupcontext[FIXUP_BOARDID] = info->board_id; 1085 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1086 1087 /* 1088 * for device tree boot, we pass the DTB directly in r2. Otherwise 1089 * we point to the kernel args. 1090 */ 1091 if (have_dtb(info)) { 1092 hwaddr align; 1093 1094 if (elf_machine == EM_AARCH64) { 1095 /* 1096 * Some AArch64 kernels on early bootup map the fdt region as 1097 * 1098 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1099 * 1100 * Let's play safe and prealign it to 2MB to give us some space. 1101 */ 1102 align = 2 * 1024 * 1024; 1103 } else { 1104 /* 1105 * Some 32bit kernels will trash anything in the 4K page the 1106 * initrd ends in, so make sure the DTB isn't caught up in that. 1107 */ 1108 align = 4096; 1109 } 1110 1111 /* Place the DTB after the initrd in memory with alignment. */ 1112 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1113 align); 1114 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; 1115 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; 1116 } else { 1117 fixupcontext[FIXUP_ARGPTR_LO] = 1118 info->loader_start + KERNEL_ARGS_ADDR; 1119 fixupcontext[FIXUP_ARGPTR_HI] = 1120 (info->loader_start + KERNEL_ARGS_ADDR) >> 32; 1121 if (info->ram_size >= (1ULL << 32)) { 1122 error_report("RAM size must be less than 4GB to boot" 1123 " Linux kernel using ATAGS (try passing a device tree" 1124 " using -dtb)"); 1125 exit(1); 1126 } 1127 } 1128 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; 1129 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; 1130 1131 write_bootloader("bootloader", info->loader_start, 1132 primary_loader, fixupcontext, as); 1133 1134 if (info->nb_cpus > 1) { 1135 info->write_secondary_boot(cpu, info); 1136 } 1137 if (info->write_board_setup) { 1138 info->write_board_setup(cpu, info); 1139 } 1140 1141 /* 1142 * Notify devices which need to fake up firmware initialization 1143 * that we're doing a direct kernel boot. 1144 */ 1145 object_child_foreach_recursive(object_get_root(), 1146 do_arm_linux_init, info); 1147 } 1148 info->is_linux = is_linux; 1149 1150 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1151 ARM_CPU(cs)->env.boot_info = info; 1152 } 1153 } 1154 1155 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) 1156 { 1157 /* Set up for booting firmware (which might load a kernel via fw_cfg) */ 1158 1159 if (have_dtb(info)) { 1160 /* 1161 * If we have a device tree blob, but no kernel to supply it to (or 1162 * the kernel is supposed to be loaded by the bootloader), copy the 1163 * DTB to the base of RAM for the bootloader to pick up. 1164 */ 1165 info->dtb_start = info->loader_start; 1166 } 1167 1168 if (info->kernel_filename) { 1169 FWCfgState *fw_cfg; 1170 bool try_decompressing_kernel; 1171 1172 fw_cfg = fw_cfg_find(); 1173 try_decompressing_kernel = arm_feature(&cpu->env, 1174 ARM_FEATURE_AARCH64); 1175 1176 /* 1177 * Expose the kernel, the command line, and the initrd in fw_cfg. 1178 * We don't process them here at all, it's all left to the 1179 * firmware. 1180 */ 1181 load_image_to_fw_cfg(fw_cfg, 1182 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1183 info->kernel_filename, 1184 try_decompressing_kernel); 1185 load_image_to_fw_cfg(fw_cfg, 1186 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1187 info->initrd_filename, false); 1188 1189 if (info->kernel_cmdline) { 1190 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1191 strlen(info->kernel_cmdline) + 1); 1192 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1193 info->kernel_cmdline); 1194 } 1195 } 1196 1197 /* 1198 * We will start from address 0 (typically a boot ROM image) in the 1199 * same way as hardware. Leave env->boot_info NULL, so that 1200 * do_cpu_reset() knows it does not need to alter the PC on reset. 1201 */ 1202 } 1203 1204 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 1205 { 1206 CPUState *cs; 1207 AddressSpace *as = arm_boot_address_space(cpu, info); 1208 1209 /* 1210 * CPU objects (unlike devices) are not automatically reset on system 1211 * reset, so we must always register a handler to do so. If we're 1212 * actually loading a kernel, the handler is also responsible for 1213 * arranging that we start it correctly. 1214 */ 1215 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1216 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1217 } 1218 1219 /* 1220 * The board code is not supposed to set secure_board_setup unless 1221 * running its code in secure mode is actually possible, and KVM 1222 * doesn't support secure. 1223 */ 1224 assert(!(info->secure_board_setup && kvm_enabled())); 1225 1226 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 1227 info->dtb_limit = 0; 1228 1229 /* Load the kernel. */ 1230 if (!info->kernel_filename || info->firmware_loaded) { 1231 arm_setup_firmware_boot(cpu, info); 1232 } else { 1233 arm_setup_direct_kernel_boot(cpu, info); 1234 } 1235 1236 if (!info->skip_dtb_autoload && have_dtb(info)) { 1237 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { 1238 exit(1); 1239 } 1240 } 1241 } 1242 1243 static const TypeInfo arm_linux_boot_if_info = { 1244 .name = TYPE_ARM_LINUX_BOOT_IF, 1245 .parent = TYPE_INTERFACE, 1246 .class_size = sizeof(ARMLinuxBootIfClass), 1247 }; 1248 1249 static void arm_linux_boot_register_types(void) 1250 { 1251 type_register_static(&arm_linux_boot_if_info); 1252 } 1253 1254 type_init(arm_linux_boot_register_types) 1255