1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/datadir.h" 12 #include "qemu/error-report.h" 13 #include "qapi/error.h" 14 #include <libfdt.h> 15 #include "hw/arm/boot.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "cpu.h" 18 #include "exec/tswap.h" 19 #include "exec/target_page.h" 20 #include "system/kvm.h" 21 #include "system/tcg.h" 22 #include "system/system.h" 23 #include "system/memory.h" 24 #include "system/numa.h" 25 #include "hw/boards.h" 26 #include "system/reset.h" 27 #include "hw/loader.h" 28 #include "elf.h" 29 #include "system/device_tree.h" 30 #include "qemu/config-file.h" 31 #include "qemu/option.h" 32 #include "qemu/units.h" 33 #include "qemu/bswap.h" 34 35 /* Kernel boot protocol is specified in the kernel docs 36 * Documentation/arm/Booting and Documentation/arm64/booting.txt 37 * They have different preferred image load offsets from system RAM base. 38 */ 39 #define KERNEL_ARGS_ADDR 0x100 40 #define KERNEL_NOLOAD_ADDR 0x02000000 41 #define KERNEL_LOAD_ADDR 0x00010000 42 #define KERNEL64_LOAD_ADDR 0x00080000 43 44 #define ARM64_TEXT_OFFSET_OFFSET 8 45 #define ARM64_MAGIC_OFFSET 56 46 47 #define BOOTLOADER_MAX_SIZE (4 * KiB) 48 49 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 50 const struct arm_boot_info *info) 51 { 52 /* Return the address space to use for bootloader reads and writes. 53 * We prefer the secure address space if the CPU has it and we're 54 * going to boot the guest into it. 55 */ 56 int asidx; 57 CPUState *cs = CPU(cpu); 58 59 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 60 asidx = ARMASIdx_S; 61 } else { 62 asidx = ARMASIdx_NS; 63 } 64 65 return cpu_get_address_space(cs, asidx); 66 } 67 68 static const ARMInsnFixup bootloader_aarch64[] = { 69 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 70 { 0xaa1f03e1 }, /* mov x1, xzr */ 71 { 0xaa1f03e2 }, /* mov x2, xzr */ 72 { 0xaa1f03e3 }, /* mov x3, xzr */ 73 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 74 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 75 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ 76 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ 77 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ 78 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ 79 { 0, FIXUP_TERMINATOR } 80 }; 81 82 /* A very small bootloader: call the board-setup code (if needed), 83 * set r0-r2, then jump to the kernel. 84 * If we're not calling boot setup code then we don't copy across 85 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 86 */ 87 88 static const ARMInsnFixup bootloader[] = { 89 { 0xe28fe004 }, /* add lr, pc, #4 */ 90 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 91 { 0, FIXUP_BOARD_SETUP }, 92 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 93 { 0xe3a00000 }, /* mov r0, #0 */ 94 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 95 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 96 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 97 { 0, FIXUP_BOARDID }, 98 { 0, FIXUP_ARGPTR_LO }, 99 { 0, FIXUP_ENTRYPOINT_LO }, 100 { 0, FIXUP_TERMINATOR } 101 }; 102 103 /* Handling for secondary CPU boot in a multicore system. 104 * Unlike the uniprocessor/primary CPU boot, this is platform 105 * dependent. The default code here is based on the secondary 106 * CPU boot protocol used on realview/vexpress boards, with 107 * some parameterisation to increase its flexibility. 108 * QEMU platform models for which this code is not appropriate 109 * should override write_secondary_boot and secondary_cpu_reset_hook 110 * instead. 111 * 112 * This code enables the interrupt controllers for the secondary 113 * CPUs and then puts all the secondary CPUs into a loop waiting 114 * for an interprocessor interrupt and polling a configurable 115 * location for the kernel secondary CPU entry point. 116 */ 117 #define DSB_INSN 0xf57ff04f 118 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 119 120 static const ARMInsnFixup smpboot[] = { 121 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 122 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 123 { 0xe3a01001 }, /* mov r1, #1 */ 124 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 125 { 0xe3a010ff }, /* mov r1, #0xff */ 126 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 127 { 0, FIXUP_DSB }, /* dsb */ 128 { 0xe320f003 }, /* wfi */ 129 { 0xe5901000 }, /* ldr r1, [r0] */ 130 { 0xe1110001 }, /* tst r1, r1 */ 131 { 0x0afffffb }, /* beq <wfi> */ 132 { 0xe12fff11 }, /* bx r1 */ 133 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 134 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 135 { 0, FIXUP_TERMINATOR } 136 }; 137 138 void arm_write_bootloader(const char *name, 139 AddressSpace *as, hwaddr addr, 140 const ARMInsnFixup *insns, 141 const uint32_t *fixupcontext) 142 { 143 /* Fix up the specified bootloader fragment and write it into 144 * guest memory using rom_add_blob_fixed(). fixupcontext is 145 * an array giving the values to write in for the fixup types 146 * which write a value into the code array. 147 */ 148 int i, len; 149 uint32_t *code; 150 151 len = 0; 152 while (insns[len].fixup != FIXUP_TERMINATOR) { 153 len++; 154 } 155 156 code = g_new0(uint32_t, len); 157 158 for (i = 0; i < len; i++) { 159 uint32_t insn = insns[i].insn; 160 FixupType fixup = insns[i].fixup; 161 162 switch (fixup) { 163 case FIXUP_NONE: 164 break; 165 case FIXUP_BOARDID: 166 case FIXUP_BOARD_SETUP: 167 case FIXUP_ARGPTR_LO: 168 case FIXUP_ARGPTR_HI: 169 case FIXUP_ENTRYPOINT_LO: 170 case FIXUP_ENTRYPOINT_HI: 171 case FIXUP_GIC_CPU_IF: 172 case FIXUP_BOOTREG: 173 case FIXUP_DSB: 174 insn = fixupcontext[fixup]; 175 break; 176 default: 177 abort(); 178 } 179 code[i] = tswap32(insn); 180 } 181 182 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 183 184 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 185 186 g_free(code); 187 } 188 189 static void default_write_secondary(ARMCPU *cpu, 190 const struct arm_boot_info *info) 191 { 192 uint32_t fixupcontext[FIXUP_MAX]; 193 AddressSpace *as = arm_boot_address_space(cpu, info); 194 195 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 196 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 197 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 198 fixupcontext[FIXUP_DSB] = DSB_INSN; 199 } else { 200 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 201 } 202 203 arm_write_bootloader("smpboot", as, info->smp_loader_start, 204 smpboot, fixupcontext); 205 } 206 207 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 208 const struct arm_boot_info *info, 209 hwaddr mvbar_addr) 210 { 211 AddressSpace *as = arm_boot_address_space(cpu, info); 212 int n; 213 uint32_t mvbar_blob[] = { 214 /* mvbar_addr: secure monitor vectors 215 * Default unimplemented and unused vectors to spin. Makes it 216 * easier to debug (as opposed to the CPU running away). 217 */ 218 0xeafffffe, /* (spin) */ 219 0xeafffffe, /* (spin) */ 220 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 221 0xeafffffe, /* (spin) */ 222 0xeafffffe, /* (spin) */ 223 0xeafffffe, /* (spin) */ 224 0xeafffffe, /* (spin) */ 225 0xeafffffe, /* (spin) */ 226 }; 227 uint32_t board_setup_blob[] = { 228 /* board setup addr */ 229 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ 230 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ 231 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ 232 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 233 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 234 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 235 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 236 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 237 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 238 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 239 0xe1a0f001, /* mov pc, r1 ;return */ 240 }; 241 242 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 243 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 244 245 /* check that these blobs don't overlap */ 246 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 247 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 248 249 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 250 mvbar_blob[n] = tswap32(mvbar_blob[n]); 251 } 252 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 253 mvbar_addr, as); 254 255 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 256 board_setup_blob[n] = tswap32(board_setup_blob[n]); 257 } 258 rom_add_blob_fixed_as("board-setup", board_setup_blob, 259 sizeof(board_setup_blob), info->board_setup_addr, as); 260 } 261 262 static void default_reset_secondary(ARMCPU *cpu, 263 const struct arm_boot_info *info) 264 { 265 AddressSpace *as = arm_boot_address_space(cpu, info); 266 CPUState *cs = CPU(cpu); 267 268 address_space_stl_notdirty(as, info->smp_bootreg_addr, 269 0, MEMTXATTRS_UNSPECIFIED, NULL); 270 cpu_set_pc(cs, info->smp_loader_start); 271 } 272 273 static inline bool have_dtb(const struct arm_boot_info *info) 274 { 275 return info->dtb_filename || info->get_dtb; 276 } 277 278 #define WRITE_WORD(p, value) do { \ 279 address_space_stl_notdirty(as, p, value, \ 280 MEMTXATTRS_UNSPECIFIED, NULL); \ 281 p += 4; \ 282 } while (0) 283 284 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 285 { 286 int initrd_size = info->initrd_size; 287 hwaddr base = info->loader_start; 288 hwaddr p; 289 290 p = base + KERNEL_ARGS_ADDR; 291 /* ATAG_CORE */ 292 WRITE_WORD(p, 5); 293 WRITE_WORD(p, 0x54410001); 294 WRITE_WORD(p, 1); 295 WRITE_WORD(p, 0x1000); 296 WRITE_WORD(p, 0); 297 /* ATAG_MEM */ 298 /* TODO: handle multiple chips on one ATAG list */ 299 WRITE_WORD(p, 4); 300 WRITE_WORD(p, 0x54410002); 301 WRITE_WORD(p, info->ram_size); 302 WRITE_WORD(p, info->loader_start); 303 if (initrd_size) { 304 /* ATAG_INITRD2 */ 305 WRITE_WORD(p, 4); 306 WRITE_WORD(p, 0x54420005); 307 WRITE_WORD(p, info->initrd_start); 308 WRITE_WORD(p, initrd_size); 309 } 310 if (info->kernel_cmdline && *info->kernel_cmdline) { 311 /* ATAG_CMDLINE */ 312 int cmdline_size; 313 314 cmdline_size = strlen(info->kernel_cmdline); 315 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 316 info->kernel_cmdline, cmdline_size + 1); 317 cmdline_size = (cmdline_size >> 2) + 1; 318 WRITE_WORD(p, cmdline_size + 2); 319 WRITE_WORD(p, 0x54410009); 320 p += cmdline_size * 4; 321 } 322 if (info->atag_board) { 323 /* ATAG_BOARD */ 324 int atag_board_len; 325 uint8_t atag_board_buf[0x1000]; 326 327 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 328 WRITE_WORD(p, (atag_board_len + 8) >> 2); 329 WRITE_WORD(p, 0x414f4d50); 330 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 331 atag_board_buf, atag_board_len); 332 p += atag_board_len; 333 } 334 /* ATAG_END */ 335 WRITE_WORD(p, 0); 336 WRITE_WORD(p, 0); 337 } 338 339 static void set_kernel_args_old(const struct arm_boot_info *info, 340 AddressSpace *as) 341 { 342 hwaddr p; 343 const char *s; 344 int initrd_size = info->initrd_size; 345 hwaddr base = info->loader_start; 346 347 /* see linux/include/asm-arm/setup.h */ 348 p = base + KERNEL_ARGS_ADDR; 349 /* page_size */ 350 WRITE_WORD(p, 4096); 351 /* nr_pages */ 352 WRITE_WORD(p, info->ram_size / 4096); 353 /* ramdisk_size */ 354 WRITE_WORD(p, 0); 355 #define FLAG_READONLY 1 356 #define FLAG_RDLOAD 4 357 #define FLAG_RDPROMPT 8 358 /* flags */ 359 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 360 /* rootdev */ 361 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 362 /* video_num_cols */ 363 WRITE_WORD(p, 0); 364 /* video_num_rows */ 365 WRITE_WORD(p, 0); 366 /* video_x */ 367 WRITE_WORD(p, 0); 368 /* video_y */ 369 WRITE_WORD(p, 0); 370 /* memc_control_reg */ 371 WRITE_WORD(p, 0); 372 /* unsigned char sounddefault */ 373 /* unsigned char adfsdrives */ 374 /* unsigned char bytes_per_char_h */ 375 /* unsigned char bytes_per_char_v */ 376 WRITE_WORD(p, 0); 377 /* pages_in_bank[4] */ 378 WRITE_WORD(p, 0); 379 WRITE_WORD(p, 0); 380 WRITE_WORD(p, 0); 381 WRITE_WORD(p, 0); 382 /* pages_in_vram */ 383 WRITE_WORD(p, 0); 384 /* initrd_start */ 385 if (initrd_size) { 386 WRITE_WORD(p, info->initrd_start); 387 } else { 388 WRITE_WORD(p, 0); 389 } 390 /* initrd_size */ 391 WRITE_WORD(p, initrd_size); 392 /* rd_start */ 393 WRITE_WORD(p, 0); 394 /* system_rev */ 395 WRITE_WORD(p, 0); 396 /* system_serial_low */ 397 WRITE_WORD(p, 0); 398 /* system_serial_high */ 399 WRITE_WORD(p, 0); 400 /* mem_fclk_21285 */ 401 WRITE_WORD(p, 0); 402 /* zero unused fields */ 403 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 404 WRITE_WORD(p, 0); 405 } 406 s = info->kernel_cmdline; 407 if (s) { 408 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1); 409 } else { 410 WRITE_WORD(p, 0); 411 } 412 } 413 414 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, 415 uint32_t scells, hwaddr mem_len, 416 int numa_node_id) 417 { 418 char *nodename; 419 int ret; 420 421 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 422 qemu_fdt_add_subnode(fdt, nodename); 423 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 424 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base, 425 scells, mem_len); 426 if (ret < 0) { 427 goto out; 428 } 429 430 /* only set the NUMA ID if it is specified */ 431 if (numa_node_id >= 0) { 432 ret = qemu_fdt_setprop_cell(fdt, nodename, 433 "numa-node-id", numa_node_id); 434 } 435 out: 436 g_free(nodename); 437 return ret; 438 } 439 440 static void fdt_add_psci_node(void *fdt, ARMCPU *armcpu) 441 { 442 uint32_t cpu_suspend_fn; 443 uint32_t cpu_off_fn; 444 uint32_t cpu_on_fn; 445 uint32_t migrate_fn; 446 const char *psci_method; 447 int64_t psci_conduit; 448 int rc; 449 450 psci_conduit = object_property_get_int(OBJECT(armcpu), 451 "psci-conduit", 452 &error_abort); 453 switch (psci_conduit) { 454 case QEMU_PSCI_CONDUIT_DISABLED: 455 return; 456 case QEMU_PSCI_CONDUIT_HVC: 457 psci_method = "hvc"; 458 break; 459 case QEMU_PSCI_CONDUIT_SMC: 460 psci_method = "smc"; 461 break; 462 default: 463 g_assert_not_reached(); 464 } 465 466 /* 467 * A pre-existing /psci node might specify function ID values 468 * that don't match QEMU's PSCI implementation. Delete the whole 469 * node and put our own in instead. 470 */ 471 rc = fdt_path_offset(fdt, "/psci"); 472 if (rc >= 0) { 473 qemu_fdt_nop_node(fdt, "/psci"); 474 } 475 476 qemu_fdt_add_subnode(fdt, "/psci"); 477 if (armcpu->psci_version >= QEMU_PSCI_VERSION_0_2) { 478 if (armcpu->psci_version < QEMU_PSCI_VERSION_1_0) { 479 const char comp[] = "arm,psci-0.2\0arm,psci"; 480 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 481 } else { 482 const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci"; 483 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 484 } 485 486 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 487 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 488 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 489 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 490 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 491 } else { 492 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 493 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 494 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 495 } 496 } else { 497 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 498 499 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 500 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 501 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 502 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 503 } 504 505 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 506 * to the instruction that should be used to invoke PSCI functions. 507 * However, the device tree binding uses 'method' instead, so that is 508 * what we should use here. 509 */ 510 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 511 512 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 513 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 514 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 515 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 516 } 517 518 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 519 hwaddr addr_limit, AddressSpace *as, MachineState *ms, 520 ARMCPU *cpu) 521 { 522 void *fdt = NULL; 523 int size, rc, n = 0; 524 uint32_t acells, scells; 525 unsigned int i; 526 hwaddr mem_base, mem_len; 527 char **node_path; 528 Error *err = NULL; 529 530 if (binfo->dtb_filename) { 531 char *filename; 532 filename = qemu_find_file(QEMU_FILE_TYPE_DTB, binfo->dtb_filename); 533 if (!filename) { 534 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 535 goto fail; 536 } 537 538 fdt = load_device_tree(filename, &size); 539 if (!fdt) { 540 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 541 g_free(filename); 542 goto fail; 543 } 544 g_free(filename); 545 } else { 546 fdt = binfo->get_dtb(binfo, &size); 547 if (!fdt) { 548 fprintf(stderr, "Board was unable to create a dtb blob\n"); 549 goto fail; 550 } 551 } 552 553 if (addr_limit > addr && size > (addr_limit - addr)) { 554 /* Installing the device tree blob at addr would exceed addr_limit. 555 * Whether this constitutes failure is up to the caller to decide, 556 * so just return 0 as size, i.e., no error. 557 */ 558 g_free(fdt); 559 return 0; 560 } 561 562 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 563 NULL, &error_fatal); 564 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 565 NULL, &error_fatal); 566 if (acells == 0 || scells == 0) { 567 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 568 goto fail; 569 } 570 571 if (scells < 2 && binfo->ram_size >= 4 * GiB) { 572 /* This is user error so deserves a friendlier error message 573 * than the failure of setprop_sized_cells would provide 574 */ 575 fprintf(stderr, "qemu: dtb file not compatible with " 576 "RAM size > 4GB\n"); 577 goto fail; 578 } 579 580 /* nop all root nodes matching /memory or /memory@unit-address */ 581 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 582 if (err) { 583 error_report_err(err); 584 goto fail; 585 } 586 while (node_path[n]) { 587 if (g_str_has_prefix(node_path[n], "/memory")) { 588 qemu_fdt_nop_node(fdt, node_path[n]); 589 } 590 n++; 591 } 592 g_strfreev(node_path); 593 594 /* 595 * We drop all the memory nodes which correspond to empty NUMA nodes 596 * from the device tree, because the Linux NUMA binding document 597 * states they should not be generated. Linux will get the NUMA node 598 * IDs of the empty NUMA nodes from the distance map if they are needed. 599 * This means QEMU users may be obliged to provide command lines which 600 * configure distance maps when the empty NUMA node IDs are needed and 601 * Linux's default distance map isn't sufficient. 602 */ 603 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) { 604 mem_base = binfo->loader_start; 605 for (i = 0; i < ms->numa_state->num_nodes; i++) { 606 mem_len = ms->numa_state->nodes[i].node_mem; 607 if (!mem_len) { 608 continue; 609 } 610 611 rc = fdt_add_memory_node(fdt, acells, mem_base, 612 scells, mem_len, i); 613 if (rc < 0) { 614 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 615 mem_base); 616 goto fail; 617 } 618 619 mem_base += mem_len; 620 } 621 } else { 622 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start, 623 scells, binfo->ram_size, -1); 624 if (rc < 0) { 625 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 626 binfo->loader_start); 627 goto fail; 628 } 629 } 630 631 rc = fdt_path_offset(fdt, "/chosen"); 632 if (rc < 0) { 633 qemu_fdt_add_subnode(fdt, "/chosen"); 634 } 635 636 if (ms->kernel_cmdline && *ms->kernel_cmdline) { 637 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 638 ms->kernel_cmdline); 639 if (rc < 0) { 640 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 641 goto fail; 642 } 643 } 644 645 if (binfo->initrd_size) { 646 rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start", 647 acells, binfo->initrd_start); 648 if (rc < 0) { 649 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 650 goto fail; 651 } 652 653 rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end", 654 acells, 655 binfo->initrd_start + 656 binfo->initrd_size); 657 if (rc < 0) { 658 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 659 goto fail; 660 } 661 } 662 663 fdt_add_psci_node(fdt, cpu); 664 665 if (binfo->modify_dtb) { 666 binfo->modify_dtb(binfo, fdt); 667 } 668 669 /* Put the DTB into the memory map as a ROM image: this will ensure 670 * the DTB is copied again upon reset, even if addr points into RAM. 671 */ 672 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 673 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 674 rom_ptr_for_as(as, addr, size)); 675 676 if (fdt != ms->fdt) { 677 g_free(ms->fdt); 678 ms->fdt = fdt; 679 } 680 681 return size; 682 683 fail: 684 g_free(fdt); 685 return -1; 686 } 687 688 static void do_cpu_reset(void *opaque) 689 { 690 ARMCPU *cpu = opaque; 691 CPUState *cs = CPU(cpu); 692 CPUARMState *env = &cpu->env; 693 const struct arm_boot_info *info = env->boot_info; 694 695 cpu_reset(cs); 696 if (info) { 697 if (!info->is_linux) { 698 int i; 699 /* Jump to the entry point. */ 700 uint64_t entry = info->entry; 701 702 switch (info->endianness) { 703 case ARM_ENDIANNESS_LE: 704 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 705 for (i = 1; i < 4; ++i) { 706 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 707 } 708 env->uncached_cpsr &= ~CPSR_E; 709 break; 710 case ARM_ENDIANNESS_BE8: 711 env->cp15.sctlr_el[1] |= SCTLR_E0E; 712 for (i = 1; i < 4; ++i) { 713 env->cp15.sctlr_el[i] |= SCTLR_EE; 714 } 715 env->uncached_cpsr |= CPSR_E; 716 break; 717 case ARM_ENDIANNESS_BE32: 718 env->cp15.sctlr_el[1] |= SCTLR_B; 719 break; 720 case ARM_ENDIANNESS_UNKNOWN: 721 break; /* Board's decision */ 722 default: 723 g_assert_not_reached(); 724 } 725 726 cpu_set_pc(cs, entry); 727 } else { 728 /* 729 * If we are booting Linux then we might need to do so at: 730 * - AArch64 NS EL2 or NS EL1 731 * - AArch32 Secure SVC (EL3) 732 * - AArch32 NS Hyp (EL2) 733 * - AArch32 NS SVC (EL1) 734 * Configure the CPU in the way boot firmware would do to 735 * drop us down to the appropriate level. 736 */ 737 int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; 738 739 if (env->aarch64) { 740 /* 741 * AArch64 kernels never boot in secure mode, and we don't 742 * support the secure_board_setup hook for AArch64. 743 */ 744 assert(!info->secure_boot); 745 assert(!info->secure_board_setup); 746 } else { 747 if (arm_feature(env, ARM_FEATURE_EL3) && 748 (info->secure_boot || 749 (info->secure_board_setup && cpu == info->primary_cpu))) { 750 /* Start this CPU in Secure SVC */ 751 target_el = 3; 752 } 753 } 754 755 arm_emulate_firmware_reset(cs, target_el); 756 757 if (cpu == info->primary_cpu) { 758 AddressSpace *as = arm_boot_address_space(cpu, info); 759 760 cpu_set_pc(cs, info->loader_start); 761 762 if (!have_dtb(info)) { 763 if (old_param) { 764 set_kernel_args_old(info, as); 765 } else { 766 set_kernel_args(info, as); 767 } 768 } 769 } else if (info->secondary_cpu_reset_hook) { 770 info->secondary_cpu_reset_hook(cpu, info); 771 } 772 } 773 774 if (tcg_enabled()) { 775 arm_rebuild_hflags(env); 776 } 777 } 778 } 779 780 static int do_arm_linux_init(Object *obj, void *opaque) 781 { 782 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 783 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 784 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 785 struct arm_boot_info *info = opaque; 786 787 if (albifc->arm_linux_init) { 788 albifc->arm_linux_init(albif, info->secure_boot); 789 } 790 } 791 return 0; 792 } 793 794 static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 795 uint64_t *lowaddr, uint64_t *highaddr, 796 int elf_machine, AddressSpace *as) 797 { 798 bool elf_is64; 799 union { 800 Elf32_Ehdr h32; 801 Elf64_Ehdr h64; 802 } elf_header; 803 int data_swab = 0; 804 int elf_data_order; 805 ssize_t ret; 806 Error *err = NULL; 807 808 809 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 810 if (err) { 811 /* 812 * If the file is not an ELF file we silently return. 813 * The caller will fall back to try other formats. 814 */ 815 error_free(err); 816 return -1; 817 } 818 819 if (elf_is64) { 820 elf_data_order = elf_header.h64.e_ident[EI_DATA]; 821 info->endianness = elf_data_order == ELFDATA2MSB ? ARM_ENDIANNESS_BE8 822 : ARM_ENDIANNESS_LE; 823 } else { 824 elf_data_order = elf_header.h32.e_ident[EI_DATA]; 825 if (elf_data_order == ELFDATA2MSB) { 826 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 827 info->endianness = ARM_ENDIANNESS_BE8; 828 } else { 829 info->endianness = ARM_ENDIANNESS_BE32; 830 /* In BE32, the CPU has a different view of the per-byte 831 * address map than the rest of the system. BE32 ELF files 832 * are organised such that they can be programmed through 833 * the CPU's per-word byte-reversed view of the world. QEMU 834 * however loads ELF files independently of the CPU. So 835 * tell the ELF loader to byte reverse the data for us. 836 */ 837 data_swab = 2; 838 } 839 } else { 840 info->endianness = ARM_ENDIANNESS_LE; 841 } 842 } 843 844 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL, 845 pentry, lowaddr, highaddr, NULL, elf_data_order, 846 elf_machine, 1, data_swab, as); 847 if (ret <= 0) { 848 /* The header loaded but the image didn't */ 849 error_report("Couldn't load elf '%s': %s", 850 info->kernel_filename, load_elf_strerror(ret)); 851 exit(1); 852 } 853 854 return ret; 855 } 856 857 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 858 hwaddr *entry, AddressSpace *as) 859 { 860 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 861 uint64_t kernel_size = 0; 862 uint8_t *buffer; 863 ssize_t size; 864 865 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 866 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 867 &buffer); 868 869 if (size < 0) { 870 gsize len; 871 872 /* Load as raw file otherwise */ 873 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 874 return -1; 875 } 876 size = len; 877 878 /* Unpack the image if it is a EFI zboot image */ 879 if (unpack_efi_zboot_image(&buffer, &size) < 0) { 880 g_free(buffer); 881 return -1; 882 } 883 } 884 885 /* check the arm64 magic header value -- very old kernels may not have it */ 886 if (size > ARM64_MAGIC_OFFSET + 4 && 887 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 888 uint64_t hdrvals[2]; 889 890 /* The arm64 Image header has text_offset and image_size fields at 8 and 891 * 16 bytes into the Image header, respectively. The text_offset field 892 * is only valid if the image_size is non-zero. 893 */ 894 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 895 896 kernel_size = le64_to_cpu(hdrvals[1]); 897 898 if (kernel_size != 0) { 899 kernel_load_offset = le64_to_cpu(hdrvals[0]); 900 901 /* 902 * We write our startup "bootloader" at the very bottom of RAM, 903 * so that bit can't be used for the image. Luckily the Image 904 * format specification is that the image requests only an offset 905 * from a 2MB boundary, not an absolute load address. So if the 906 * image requests an offset that might mean it overlaps with the 907 * bootloader, we can just load it starting at 2MB+offset rather 908 * than 0MB + offset. 909 */ 910 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 911 kernel_load_offset += 2 * MiB; 912 } 913 } 914 } 915 916 /* 917 * Kernels before v3.17 don't populate the image_size field, and 918 * raw images have no header. For those our best guess at the size 919 * is the size of the Image file itself. 920 */ 921 if (kernel_size == 0) { 922 kernel_size = size; 923 } 924 925 *entry = mem_base + kernel_load_offset; 926 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 927 928 g_free(buffer); 929 930 return kernel_size; 931 } 932 933 static void arm_setup_direct_kernel_boot(ARMCPU *cpu, 934 struct arm_boot_info *info) 935 { 936 /* Set up for a direct boot of a kernel image file. */ 937 CPUState *cs; 938 AddressSpace *as = arm_boot_address_space(cpu, info); 939 ssize_t kernel_size; 940 int initrd_size; 941 int is_linux = 0; 942 uint64_t elf_entry; 943 /* Addresses of first byte used and first byte not used by the image */ 944 uint64_t image_low_addr = 0, image_high_addr = 0; 945 int elf_machine; 946 hwaddr entry; 947 static const ARMInsnFixup *primary_loader; 948 uint64_t ram_end = info->loader_start + info->ram_size; 949 950 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 951 primary_loader = bootloader_aarch64; 952 elf_machine = EM_AARCH64; 953 } else { 954 primary_loader = bootloader; 955 if (!info->write_board_setup) { 956 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 957 } 958 elf_machine = EM_ARM; 959 } 960 961 /* Assume that raw images are linux kernels, and ELF images are not. */ 962 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr, 963 &image_high_addr, elf_machine, as); 964 if (kernel_size > 0 && have_dtb(info)) { 965 /* 966 * If there is still some room left at the base of RAM, try and put 967 * the DTB there like we do for images loaded with -bios or -pflash. 968 */ 969 if (image_low_addr > info->loader_start 970 || image_high_addr < info->loader_start) { 971 /* 972 * Set image_low_addr as address limit for arm_load_dtb if it may be 973 * pointing into RAM, otherwise pass '0' (no limit) 974 */ 975 if (image_low_addr < info->loader_start) { 976 image_low_addr = 0; 977 } 978 info->dtb_start = info->loader_start; 979 info->dtb_limit = image_low_addr; 980 } 981 } 982 entry = elf_entry; 983 if (kernel_size < 0) { 984 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; 985 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, 986 &is_linux, NULL, NULL, as); 987 if (kernel_size >= 0) { 988 image_low_addr = loadaddr; 989 image_high_addr = image_low_addr + kernel_size; 990 } 991 } 992 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 993 kernel_size = load_aarch64_image(info->kernel_filename, 994 info->loader_start, &entry, as); 995 is_linux = 1; 996 if (kernel_size >= 0) { 997 image_low_addr = entry; 998 image_high_addr = image_low_addr + kernel_size; 999 } 1000 } else if (kernel_size < 0) { 1001 /* 32-bit ARM */ 1002 entry = info->loader_start + KERNEL_LOAD_ADDR; 1003 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 1004 ram_end - KERNEL_LOAD_ADDR, as); 1005 is_linux = 1; 1006 if (kernel_size >= 0) { 1007 image_low_addr = entry; 1008 image_high_addr = image_low_addr + kernel_size; 1009 } 1010 } 1011 if (kernel_size < 0) { 1012 error_report("could not load kernel '%s'", info->kernel_filename); 1013 exit(1); 1014 } 1015 1016 if (kernel_size > info->ram_size) { 1017 error_report("kernel '%s' is too large to fit in RAM " 1018 "(kernel size %zd, RAM size %" PRId64 ")", 1019 info->kernel_filename, kernel_size, info->ram_size); 1020 exit(1); 1021 } 1022 1023 info->entry = entry; 1024 1025 /* 1026 * We want to put the initrd far enough into RAM that when the 1027 * kernel is uncompressed it will not clobber the initrd. However 1028 * on boards without much RAM we must ensure that we still leave 1029 * enough room for a decent sized initrd, and on boards with large 1030 * amounts of RAM we must avoid the initrd being so far up in RAM 1031 * that it is outside lowmem and inaccessible to the kernel. 1032 * So for boards with less than 256MB of RAM we put the initrd 1033 * halfway into RAM, and for boards with 256MB of RAM or more we put 1034 * the initrd at 128MB. 1035 * We also refuse to put the initrd somewhere that will definitely 1036 * overlay the kernel we just loaded, though for kernel formats which 1037 * don't tell us their exact size (eg self-decompressing 32-bit kernels) 1038 * we might still make a bad choice here. 1039 */ 1040 info->initrd_start = info->loader_start + 1041 MIN(info->ram_size / 2, 128 * MiB); 1042 if (image_high_addr) { 1043 info->initrd_start = MAX(info->initrd_start, image_high_addr); 1044 } 1045 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); 1046 1047 if (is_linux) { 1048 uint32_t fixupcontext[FIXUP_MAX]; 1049 1050 if (info->initrd_filename) { 1051 1052 if (info->initrd_start >= ram_end) { 1053 error_report("not enough space after kernel to load initrd"); 1054 exit(1); 1055 } 1056 1057 initrd_size = load_ramdisk_as(info->initrd_filename, 1058 info->initrd_start, 1059 ram_end - info->initrd_start, as); 1060 if (initrd_size < 0) { 1061 initrd_size = load_image_targphys_as(info->initrd_filename, 1062 info->initrd_start, 1063 ram_end - 1064 info->initrd_start, 1065 as); 1066 } 1067 if (initrd_size < 0) { 1068 error_report("could not load initrd '%s'", 1069 info->initrd_filename); 1070 exit(1); 1071 } 1072 if (info->initrd_start + initrd_size > ram_end) { 1073 error_report("could not load initrd '%s': " 1074 "too big to fit into RAM after the kernel", 1075 info->initrd_filename); 1076 exit(1); 1077 } 1078 } else { 1079 initrd_size = 0; 1080 } 1081 info->initrd_size = initrd_size; 1082 1083 fixupcontext[FIXUP_BOARDID] = info->board_id; 1084 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1085 1086 /* 1087 * for device tree boot, we pass the DTB directly in r2. Otherwise 1088 * we point to the kernel args. 1089 */ 1090 if (have_dtb(info)) { 1091 hwaddr align; 1092 1093 if (elf_machine == EM_AARCH64) { 1094 /* 1095 * Some AArch64 kernels on early bootup map the fdt region as 1096 * 1097 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1098 * 1099 * Let's play safe and prealign it to 2MB to give us some space. 1100 */ 1101 align = 2 * MiB; 1102 } else { 1103 /* 1104 * Some 32bit kernels will trash anything in the 4K page the 1105 * initrd ends in, so make sure the DTB isn't caught up in that. 1106 */ 1107 align = 4 * KiB; 1108 } 1109 1110 /* Place the DTB after the initrd in memory with alignment. */ 1111 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1112 align); 1113 if (info->dtb_start >= ram_end) { 1114 error_report("Not enough space for DTB after kernel/initrd"); 1115 exit(1); 1116 } 1117 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; 1118 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; 1119 } else { 1120 fixupcontext[FIXUP_ARGPTR_LO] = 1121 info->loader_start + KERNEL_ARGS_ADDR; 1122 fixupcontext[FIXUP_ARGPTR_HI] = 1123 (info->loader_start + KERNEL_ARGS_ADDR) >> 32; 1124 if (info->ram_size >= 4 * GiB) { 1125 error_report("RAM size must be less than 4GB to boot" 1126 " Linux kernel using ATAGS (try passing a device tree" 1127 " using -dtb)"); 1128 exit(1); 1129 } 1130 } 1131 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; 1132 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; 1133 1134 arm_write_bootloader("bootloader", as, info->loader_start, 1135 primary_loader, fixupcontext); 1136 1137 if (info->write_board_setup) { 1138 info->write_board_setup(cpu, info); 1139 } 1140 1141 /* 1142 * Notify devices which need to fake up firmware initialization 1143 * that we're doing a direct kernel boot. 1144 */ 1145 object_child_foreach_recursive(object_get_root(), 1146 do_arm_linux_init, info); 1147 } 1148 info->is_linux = is_linux; 1149 1150 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1151 ARM_CPU(cs)->env.boot_info = info; 1152 } 1153 } 1154 1155 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) 1156 { 1157 /* Set up for booting firmware (which might load a kernel via fw_cfg) */ 1158 1159 if (have_dtb(info)) { 1160 /* 1161 * If we have a device tree blob, but no kernel to supply it to (or 1162 * the kernel is supposed to be loaded by the bootloader), copy the 1163 * DTB to the base of RAM for the bootloader to pick up. 1164 */ 1165 info->dtb_start = info->loader_start; 1166 } 1167 1168 if (info->kernel_filename) { 1169 FWCfgState *fw_cfg; 1170 bool try_decompressing_kernel; 1171 1172 fw_cfg = fw_cfg_find(); 1173 1174 if (!fw_cfg) { 1175 error_report("This machine type does not support loading both " 1176 "a guest firmware/BIOS image and a guest kernel at " 1177 "the same time. You should change your QEMU command " 1178 "line to specify one or the other, but not both."); 1179 exit(1); 1180 } 1181 1182 try_decompressing_kernel = arm_feature(&cpu->env, 1183 ARM_FEATURE_AARCH64); 1184 1185 /* 1186 * Expose the kernel, the command line, and the initrd in fw_cfg. 1187 * We don't process them here at all, it's all left to the 1188 * firmware. 1189 */ 1190 load_image_to_fw_cfg(fw_cfg, 1191 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1192 info->kernel_filename, 1193 try_decompressing_kernel); 1194 load_image_to_fw_cfg(fw_cfg, 1195 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1196 info->initrd_filename, false); 1197 1198 if (info->kernel_cmdline) { 1199 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1200 strlen(info->kernel_cmdline) + 1); 1201 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1202 info->kernel_cmdline); 1203 } 1204 } 1205 1206 /* 1207 * We will start from address 0 (typically a boot ROM image) in the 1208 * same way as hardware. Leave env->boot_info NULL, so that 1209 * do_cpu_reset() knows it does not need to alter the PC on reset. 1210 */ 1211 } 1212 1213 void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) 1214 { 1215 CPUState *cs; 1216 AddressSpace *as = arm_boot_address_space(cpu, info); 1217 int boot_el; 1218 CPUARMState *env = &cpu->env; 1219 int nb_cpus = 0; 1220 1221 /* 1222 * CPU objects (unlike devices) are not automatically reset on system 1223 * reset, so we must always register a handler to do so. If we're 1224 * actually loading a kernel, the handler is also responsible for 1225 * arranging that we start it correctly. 1226 */ 1227 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1228 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1229 nb_cpus++; 1230 } 1231 1232 /* 1233 * The board code is not supposed to set secure_board_setup unless 1234 * running its code in secure mode is actually possible, and KVM 1235 * doesn't support secure. 1236 */ 1237 assert(!(info->secure_board_setup && kvm_enabled())); 1238 info->kernel_filename = ms->kernel_filename; 1239 info->kernel_cmdline = ms->kernel_cmdline; 1240 info->initrd_filename = ms->initrd_filename; 1241 info->dtb_filename = ms->dtb; 1242 info->dtb_limit = 0; 1243 1244 /* We assume the CPU passed as argument is the primary CPU. */ 1245 info->primary_cpu = cpu; 1246 1247 /* Load the kernel. */ 1248 if (!info->kernel_filename || info->firmware_loaded) { 1249 arm_setup_firmware_boot(cpu, info); 1250 } else { 1251 arm_setup_direct_kernel_boot(cpu, info); 1252 } 1253 1254 /* 1255 * Disable the PSCI conduit if it is set up to target the same 1256 * or a lower EL than the one we're going to start the guest code in. 1257 * This logic needs to agree with the code in do_cpu_reset() which 1258 * decides whether we're going to boot the guest in the highest 1259 * supported exception level or in a lower one. 1260 */ 1261 1262 /* 1263 * If PSCI is enabled, then SMC calls all go to the PSCI handler and 1264 * are never emulated to trap into guest code. It therefore does not 1265 * make sense for the board to have a setup code fragment that runs 1266 * in Secure, because this will probably need to itself issue an SMC of some 1267 * kind as part of its operation. 1268 */ 1269 assert(info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED || 1270 !info->secure_board_setup); 1271 1272 /* Boot into highest supported EL ... */ 1273 if (arm_feature(env, ARM_FEATURE_EL3)) { 1274 boot_el = 3; 1275 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 1276 boot_el = 2; 1277 } else { 1278 boot_el = 1; 1279 } 1280 /* ...except that if we're booting Linux we adjust the EL we boot into */ 1281 if (info->is_linux && !info->secure_boot) { 1282 boot_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; 1283 } 1284 1285 if ((info->psci_conduit == QEMU_PSCI_CONDUIT_HVC && boot_el >= 2) || 1286 (info->psci_conduit == QEMU_PSCI_CONDUIT_SMC && boot_el == 3)) { 1287 info->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1288 } 1289 1290 if (info->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1291 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1292 Object *cpuobj = OBJECT(cs); 1293 1294 object_property_set_int(cpuobj, "psci-conduit", info->psci_conduit, 1295 &error_abort); 1296 /* Secondary CPUs start in PSCI powered-down state. */ 1297 if (ARM_CPU(cs) != info->primary_cpu) { 1298 object_property_set_bool(cpuobj, "start-powered-off", true, 1299 &error_abort); 1300 } 1301 } 1302 } 1303 1304 if (info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED && 1305 info->is_linux && nb_cpus > 1) { 1306 /* 1307 * We're booting Linux but not using PSCI, so for SMP we need 1308 * to write a custom secondary CPU boot loader stub, and arrange 1309 * for the secondary CPU reset to make the accompanying initialization. 1310 */ 1311 if (!info->secondary_cpu_reset_hook) { 1312 info->secondary_cpu_reset_hook = default_reset_secondary; 1313 } 1314 if (!info->write_secondary_boot) { 1315 info->write_secondary_boot = default_write_secondary; 1316 } 1317 info->write_secondary_boot(cpu, info); 1318 } else { 1319 /* 1320 * No secondary boot stub; don't use the reset hook that would 1321 * have set the CPU up to call it 1322 */ 1323 info->write_secondary_boot = NULL; 1324 info->secondary_cpu_reset_hook = NULL; 1325 } 1326 1327 /* 1328 * arm_load_dtb() may add a PSCI node so it must be called after we have 1329 * decided whether to enable PSCI and set the psci-conduit CPU properties. 1330 */ 1331 if (!info->skip_dtb_autoload && have_dtb(info)) { 1332 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, 1333 as, ms, cpu) < 0) { 1334 exit(1); 1335 } 1336 } 1337 } 1338 1339 static const TypeInfo arm_linux_boot_if_info = { 1340 .name = TYPE_ARM_LINUX_BOOT_IF, 1341 .parent = TYPE_INTERFACE, 1342 .class_size = sizeof(ARMLinuxBootIfClass), 1343 }; 1344 1345 static void arm_linux_boot_register_types(void) 1346 { 1347 type_register_static(&arm_linux_boot_if_info); 1348 } 1349 1350 type_init(arm_linux_boot_register_types) 1351