1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/error-report.h" 12 #include "qapi/error.h" 13 #include <libfdt.h> 14 #include "hw/hw.h" 15 #include "hw/arm/arm.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "sysemu/kvm.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/numa.h" 20 #include "hw/boards.h" 21 #include "hw/loader.h" 22 #include "elf.h" 23 #include "sysemu/device_tree.h" 24 #include "qemu/config-file.h" 25 #include "qemu/option.h" 26 #include "exec/address-spaces.h" 27 28 /* Kernel boot protocol is specified in the kernel docs 29 * Documentation/arm/Booting and Documentation/arm64/booting.txt 30 * They have different preferred image load offsets from system RAM base. 31 */ 32 #define KERNEL_ARGS_ADDR 0x100 33 #define KERNEL_LOAD_ADDR 0x00010000 34 #define KERNEL64_LOAD_ADDR 0x00080000 35 36 #define ARM64_TEXT_OFFSET_OFFSET 8 37 #define ARM64_MAGIC_OFFSET 56 38 39 typedef enum { 40 FIXUP_NONE = 0, /* do nothing */ 41 FIXUP_TERMINATOR, /* end of insns */ 42 FIXUP_BOARDID, /* overwrite with board ID number */ 43 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ 44 FIXUP_ARGPTR, /* overwrite with pointer to kernel args */ 45 FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */ 46 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ 47 FIXUP_BOOTREG, /* overwrite with boot register address */ 48 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ 49 FIXUP_MAX, 50 } FixupType; 51 52 typedef struct ARMInsnFixup { 53 uint32_t insn; 54 FixupType fixup; 55 } ARMInsnFixup; 56 57 static const ARMInsnFixup bootloader_aarch64[] = { 58 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 59 { 0xaa1f03e1 }, /* mov x1, xzr */ 60 { 0xaa1f03e2 }, /* mov x2, xzr */ 61 { 0xaa1f03e3 }, /* mov x3, xzr */ 62 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 63 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 64 { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */ 65 { 0 }, /* .word @DTB Higher 32-bits */ 66 { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */ 67 { 0 }, /* .word @Kernel Entry Higher 32-bits */ 68 { 0, FIXUP_TERMINATOR } 69 }; 70 71 /* A very small bootloader: call the board-setup code (if needed), 72 * set r0-r2, then jump to the kernel. 73 * If we're not calling boot setup code then we don't copy across 74 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 75 */ 76 77 static const ARMInsnFixup bootloader[] = { 78 { 0xe28fe004 }, /* add lr, pc, #4 */ 79 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 80 { 0, FIXUP_BOARD_SETUP }, 81 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 82 { 0xe3a00000 }, /* mov r0, #0 */ 83 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 84 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 85 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 86 { 0, FIXUP_BOARDID }, 87 { 0, FIXUP_ARGPTR }, 88 { 0, FIXUP_ENTRYPOINT }, 89 { 0, FIXUP_TERMINATOR } 90 }; 91 92 /* Handling for secondary CPU boot in a multicore system. 93 * Unlike the uniprocessor/primary CPU boot, this is platform 94 * dependent. The default code here is based on the secondary 95 * CPU boot protocol used on realview/vexpress boards, with 96 * some parameterisation to increase its flexibility. 97 * QEMU platform models for which this code is not appropriate 98 * should override write_secondary_boot and secondary_cpu_reset_hook 99 * instead. 100 * 101 * This code enables the interrupt controllers for the secondary 102 * CPUs and then puts all the secondary CPUs into a loop waiting 103 * for an interprocessor interrupt and polling a configurable 104 * location for the kernel secondary CPU entry point. 105 */ 106 #define DSB_INSN 0xf57ff04f 107 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 108 109 static const ARMInsnFixup smpboot[] = { 110 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 111 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 112 { 0xe3a01001 }, /* mov r1, #1 */ 113 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 114 { 0xe3a010ff }, /* mov r1, #0xff */ 115 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 116 { 0, FIXUP_DSB }, /* dsb */ 117 { 0xe320f003 }, /* wfi */ 118 { 0xe5901000 }, /* ldr r1, [r0] */ 119 { 0xe1110001 }, /* tst r1, r1 */ 120 { 0x0afffffb }, /* beq <wfi> */ 121 { 0xe12fff11 }, /* bx r1 */ 122 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 123 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 124 { 0, FIXUP_TERMINATOR } 125 }; 126 127 static void write_bootloader(const char *name, hwaddr addr, 128 const ARMInsnFixup *insns, uint32_t *fixupcontext) 129 { 130 /* Fix up the specified bootloader fragment and write it into 131 * guest memory using rom_add_blob_fixed(). fixupcontext is 132 * an array giving the values to write in for the fixup types 133 * which write a value into the code array. 134 */ 135 int i, len; 136 uint32_t *code; 137 138 len = 0; 139 while (insns[len].fixup != FIXUP_TERMINATOR) { 140 len++; 141 } 142 143 code = g_new0(uint32_t, len); 144 145 for (i = 0; i < len; i++) { 146 uint32_t insn = insns[i].insn; 147 FixupType fixup = insns[i].fixup; 148 149 switch (fixup) { 150 case FIXUP_NONE: 151 break; 152 case FIXUP_BOARDID: 153 case FIXUP_BOARD_SETUP: 154 case FIXUP_ARGPTR: 155 case FIXUP_ENTRYPOINT: 156 case FIXUP_GIC_CPU_IF: 157 case FIXUP_BOOTREG: 158 case FIXUP_DSB: 159 insn = fixupcontext[fixup]; 160 break; 161 default: 162 abort(); 163 } 164 code[i] = tswap32(insn); 165 } 166 167 rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr); 168 169 g_free(code); 170 } 171 172 static void default_write_secondary(ARMCPU *cpu, 173 const struct arm_boot_info *info) 174 { 175 uint32_t fixupcontext[FIXUP_MAX]; 176 177 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 178 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 179 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 180 fixupcontext[FIXUP_DSB] = DSB_INSN; 181 } else { 182 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 183 } 184 185 write_bootloader("smpboot", info->smp_loader_start, 186 smpboot, fixupcontext); 187 } 188 189 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 190 const struct arm_boot_info *info, 191 hwaddr mvbar_addr) 192 { 193 int n; 194 uint32_t mvbar_blob[] = { 195 /* mvbar_addr: secure monitor vectors 196 * Default unimplemented and unused vectors to spin. Makes it 197 * easier to debug (as opposed to the CPU running away). 198 */ 199 0xeafffffe, /* (spin) */ 200 0xeafffffe, /* (spin) */ 201 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 202 0xeafffffe, /* (spin) */ 203 0xeafffffe, /* (spin) */ 204 0xeafffffe, /* (spin) */ 205 0xeafffffe, /* (spin) */ 206 0xeafffffe, /* (spin) */ 207 }; 208 uint32_t board_setup_blob[] = { 209 /* board setup addr */ 210 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 211 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 212 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 213 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 214 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 215 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 216 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 217 0xe1a0f001, /* mov pc, r1 ;return */ 218 }; 219 220 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 221 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 222 223 /* check that these blobs don't overlap */ 224 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 225 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 226 227 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 228 mvbar_blob[n] = tswap32(mvbar_blob[n]); 229 } 230 rom_add_blob_fixed("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 231 mvbar_addr); 232 233 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 234 board_setup_blob[n] = tswap32(board_setup_blob[n]); 235 } 236 rom_add_blob_fixed("board-setup", board_setup_blob, 237 sizeof(board_setup_blob), info->board_setup_addr); 238 } 239 240 static void default_reset_secondary(ARMCPU *cpu, 241 const struct arm_boot_info *info) 242 { 243 CPUState *cs = CPU(cpu); 244 245 address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr, 246 0, MEMTXATTRS_UNSPECIFIED, NULL); 247 cpu_set_pc(cs, info->smp_loader_start); 248 } 249 250 static inline bool have_dtb(const struct arm_boot_info *info) 251 { 252 return info->dtb_filename || info->get_dtb; 253 } 254 255 #define WRITE_WORD(p, value) do { \ 256 address_space_stl_notdirty(&address_space_memory, p, value, \ 257 MEMTXATTRS_UNSPECIFIED, NULL); \ 258 p += 4; \ 259 } while (0) 260 261 static void set_kernel_args(const struct arm_boot_info *info) 262 { 263 int initrd_size = info->initrd_size; 264 hwaddr base = info->loader_start; 265 hwaddr p; 266 267 p = base + KERNEL_ARGS_ADDR; 268 /* ATAG_CORE */ 269 WRITE_WORD(p, 5); 270 WRITE_WORD(p, 0x54410001); 271 WRITE_WORD(p, 1); 272 WRITE_WORD(p, 0x1000); 273 WRITE_WORD(p, 0); 274 /* ATAG_MEM */ 275 /* TODO: handle multiple chips on one ATAG list */ 276 WRITE_WORD(p, 4); 277 WRITE_WORD(p, 0x54410002); 278 WRITE_WORD(p, info->ram_size); 279 WRITE_WORD(p, info->loader_start); 280 if (initrd_size) { 281 /* ATAG_INITRD2 */ 282 WRITE_WORD(p, 4); 283 WRITE_WORD(p, 0x54420005); 284 WRITE_WORD(p, info->initrd_start); 285 WRITE_WORD(p, initrd_size); 286 } 287 if (info->kernel_cmdline && *info->kernel_cmdline) { 288 /* ATAG_CMDLINE */ 289 int cmdline_size; 290 291 cmdline_size = strlen(info->kernel_cmdline); 292 cpu_physical_memory_write(p + 8, info->kernel_cmdline, 293 cmdline_size + 1); 294 cmdline_size = (cmdline_size >> 2) + 1; 295 WRITE_WORD(p, cmdline_size + 2); 296 WRITE_WORD(p, 0x54410009); 297 p += cmdline_size * 4; 298 } 299 if (info->atag_board) { 300 /* ATAG_BOARD */ 301 int atag_board_len; 302 uint8_t atag_board_buf[0x1000]; 303 304 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 305 WRITE_WORD(p, (atag_board_len + 8) >> 2); 306 WRITE_WORD(p, 0x414f4d50); 307 cpu_physical_memory_write(p, atag_board_buf, atag_board_len); 308 p += atag_board_len; 309 } 310 /* ATAG_END */ 311 WRITE_WORD(p, 0); 312 WRITE_WORD(p, 0); 313 } 314 315 static void set_kernel_args_old(const struct arm_boot_info *info) 316 { 317 hwaddr p; 318 const char *s; 319 int initrd_size = info->initrd_size; 320 hwaddr base = info->loader_start; 321 322 /* see linux/include/asm-arm/setup.h */ 323 p = base + KERNEL_ARGS_ADDR; 324 /* page_size */ 325 WRITE_WORD(p, 4096); 326 /* nr_pages */ 327 WRITE_WORD(p, info->ram_size / 4096); 328 /* ramdisk_size */ 329 WRITE_WORD(p, 0); 330 #define FLAG_READONLY 1 331 #define FLAG_RDLOAD 4 332 #define FLAG_RDPROMPT 8 333 /* flags */ 334 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 335 /* rootdev */ 336 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 337 /* video_num_cols */ 338 WRITE_WORD(p, 0); 339 /* video_num_rows */ 340 WRITE_WORD(p, 0); 341 /* video_x */ 342 WRITE_WORD(p, 0); 343 /* video_y */ 344 WRITE_WORD(p, 0); 345 /* memc_control_reg */ 346 WRITE_WORD(p, 0); 347 /* unsigned char sounddefault */ 348 /* unsigned char adfsdrives */ 349 /* unsigned char bytes_per_char_h */ 350 /* unsigned char bytes_per_char_v */ 351 WRITE_WORD(p, 0); 352 /* pages_in_bank[4] */ 353 WRITE_WORD(p, 0); 354 WRITE_WORD(p, 0); 355 WRITE_WORD(p, 0); 356 WRITE_WORD(p, 0); 357 /* pages_in_vram */ 358 WRITE_WORD(p, 0); 359 /* initrd_start */ 360 if (initrd_size) { 361 WRITE_WORD(p, info->initrd_start); 362 } else { 363 WRITE_WORD(p, 0); 364 } 365 /* initrd_size */ 366 WRITE_WORD(p, initrd_size); 367 /* rd_start */ 368 WRITE_WORD(p, 0); 369 /* system_rev */ 370 WRITE_WORD(p, 0); 371 /* system_serial_low */ 372 WRITE_WORD(p, 0); 373 /* system_serial_high */ 374 WRITE_WORD(p, 0); 375 /* mem_fclk_21285 */ 376 WRITE_WORD(p, 0); 377 /* zero unused fields */ 378 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 379 WRITE_WORD(p, 0); 380 } 381 s = info->kernel_cmdline; 382 if (s) { 383 cpu_physical_memory_write(p, s, strlen(s) + 1); 384 } else { 385 WRITE_WORD(p, 0); 386 } 387 } 388 389 static void fdt_add_psci_node(void *fdt) 390 { 391 uint32_t cpu_suspend_fn; 392 uint32_t cpu_off_fn; 393 uint32_t cpu_on_fn; 394 uint32_t migrate_fn; 395 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 396 const char *psci_method; 397 int64_t psci_conduit; 398 399 psci_conduit = object_property_get_int(OBJECT(armcpu), 400 "psci-conduit", 401 &error_abort); 402 switch (psci_conduit) { 403 case QEMU_PSCI_CONDUIT_DISABLED: 404 return; 405 case QEMU_PSCI_CONDUIT_HVC: 406 psci_method = "hvc"; 407 break; 408 case QEMU_PSCI_CONDUIT_SMC: 409 psci_method = "smc"; 410 break; 411 default: 412 g_assert_not_reached(); 413 } 414 415 qemu_fdt_add_subnode(fdt, "/psci"); 416 if (armcpu->psci_version == 2) { 417 const char comp[] = "arm,psci-0.2\0arm,psci"; 418 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 419 420 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 421 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 422 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 423 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 424 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 425 } else { 426 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 427 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 428 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 429 } 430 } else { 431 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 432 433 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 434 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 435 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 436 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 437 } 438 439 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 440 * to the instruction that should be used to invoke PSCI functions. 441 * However, the device tree binding uses 'method' instead, so that is 442 * what we should use here. 443 */ 444 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 445 446 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 447 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 448 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 449 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 450 } 451 452 /** 453 * load_dtb() - load a device tree binary image into memory 454 * @addr: the address to load the image at 455 * @binfo: struct describing the boot environment 456 * @addr_limit: upper limit of the available memory area at @addr 457 * 458 * Load a device tree supplied by the machine or by the user with the 459 * '-dtb' command line option, and put it at offset @addr in target 460 * memory. 461 * 462 * If @addr_limit contains a meaningful value (i.e., it is strictly greater 463 * than @addr), the device tree is only loaded if its size does not exceed 464 * the limit. 465 * 466 * Returns: the size of the device tree image on success, 467 * 0 if the image size exceeds the limit, 468 * -1 on errors. 469 * 470 * Note: Must not be called unless have_dtb(binfo) is true. 471 */ 472 static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 473 hwaddr addr_limit) 474 { 475 void *fdt = NULL; 476 int size, rc; 477 uint32_t acells, scells; 478 char *nodename; 479 unsigned int i; 480 hwaddr mem_base, mem_len; 481 482 if (binfo->dtb_filename) { 483 char *filename; 484 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 485 if (!filename) { 486 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 487 goto fail; 488 } 489 490 fdt = load_device_tree(filename, &size); 491 if (!fdt) { 492 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 493 g_free(filename); 494 goto fail; 495 } 496 g_free(filename); 497 } else { 498 fdt = binfo->get_dtb(binfo, &size); 499 if (!fdt) { 500 fprintf(stderr, "Board was unable to create a dtb blob\n"); 501 goto fail; 502 } 503 } 504 505 if (addr_limit > addr && size > (addr_limit - addr)) { 506 /* Installing the device tree blob at addr would exceed addr_limit. 507 * Whether this constitutes failure is up to the caller to decide, 508 * so just return 0 as size, i.e., no error. 509 */ 510 g_free(fdt); 511 return 0; 512 } 513 514 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 515 NULL, &error_fatal); 516 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 517 NULL, &error_fatal); 518 if (acells == 0 || scells == 0) { 519 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 520 goto fail; 521 } 522 523 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { 524 /* This is user error so deserves a friendlier error message 525 * than the failure of setprop_sized_cells would provide 526 */ 527 fprintf(stderr, "qemu: dtb file not compatible with " 528 "RAM size > 4GB\n"); 529 goto fail; 530 } 531 532 if (nb_numa_nodes > 0) { 533 /* 534 * Turn the /memory node created before into a NOP node, then create 535 * /memory@addr nodes for all numa nodes respectively. 536 */ 537 qemu_fdt_nop_node(fdt, "/memory"); 538 mem_base = binfo->loader_start; 539 for (i = 0; i < nb_numa_nodes; i++) { 540 mem_len = numa_info[i].node_mem; 541 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 542 qemu_fdt_add_subnode(fdt, nodename); 543 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 544 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 545 acells, mem_base, 546 scells, mem_len); 547 if (rc < 0) { 548 fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename, 549 i); 550 goto fail; 551 } 552 553 qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i); 554 mem_base += mem_len; 555 g_free(nodename); 556 } 557 } else { 558 Error *err = NULL; 559 560 rc = fdt_path_offset(fdt, "/memory"); 561 if (rc < 0) { 562 qemu_fdt_add_subnode(fdt, "/memory"); 563 } 564 565 if (!qemu_fdt_getprop(fdt, "/memory", "device_type", NULL, &err)) { 566 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 567 } 568 569 rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg", 570 acells, binfo->loader_start, 571 scells, binfo->ram_size); 572 if (rc < 0) { 573 fprintf(stderr, "couldn't set /memory/reg\n"); 574 goto fail; 575 } 576 } 577 578 rc = fdt_path_offset(fdt, "/chosen"); 579 if (rc < 0) { 580 qemu_fdt_add_subnode(fdt, "/chosen"); 581 } 582 583 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { 584 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 585 binfo->kernel_cmdline); 586 if (rc < 0) { 587 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 588 goto fail; 589 } 590 } 591 592 if (binfo->initrd_size) { 593 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 594 binfo->initrd_start); 595 if (rc < 0) { 596 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 597 goto fail; 598 } 599 600 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 601 binfo->initrd_start + binfo->initrd_size); 602 if (rc < 0) { 603 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 604 goto fail; 605 } 606 } 607 608 fdt_add_psci_node(fdt); 609 610 if (binfo->modify_dtb) { 611 binfo->modify_dtb(binfo, fdt); 612 } 613 614 qemu_fdt_dumpdtb(fdt, size); 615 616 /* Put the DTB into the memory map as a ROM image: this will ensure 617 * the DTB is copied again upon reset, even if addr points into RAM. 618 */ 619 rom_add_blob_fixed("dtb", fdt, size, addr); 620 621 g_free(fdt); 622 623 return size; 624 625 fail: 626 g_free(fdt); 627 return -1; 628 } 629 630 static void do_cpu_reset(void *opaque) 631 { 632 ARMCPU *cpu = opaque; 633 CPUState *cs = CPU(cpu); 634 CPUARMState *env = &cpu->env; 635 const struct arm_boot_info *info = env->boot_info; 636 637 cpu_reset(cs); 638 if (info) { 639 if (!info->is_linux) { 640 int i; 641 /* Jump to the entry point. */ 642 uint64_t entry = info->entry; 643 644 switch (info->endianness) { 645 case ARM_ENDIANNESS_LE: 646 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 647 for (i = 1; i < 4; ++i) { 648 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 649 } 650 env->uncached_cpsr &= ~CPSR_E; 651 break; 652 case ARM_ENDIANNESS_BE8: 653 env->cp15.sctlr_el[1] |= SCTLR_E0E; 654 for (i = 1; i < 4; ++i) { 655 env->cp15.sctlr_el[i] |= SCTLR_EE; 656 } 657 env->uncached_cpsr |= CPSR_E; 658 break; 659 case ARM_ENDIANNESS_BE32: 660 env->cp15.sctlr_el[1] |= SCTLR_B; 661 break; 662 case ARM_ENDIANNESS_UNKNOWN: 663 break; /* Board's decision */ 664 default: 665 g_assert_not_reached(); 666 } 667 668 if (!env->aarch64) { 669 env->thumb = info->entry & 1; 670 entry &= 0xfffffffe; 671 } 672 cpu_set_pc(cs, entry); 673 } else { 674 /* If we are booting Linux then we need to check whether we are 675 * booting into secure or non-secure state and adjust the state 676 * accordingly. Out of reset, ARM is defined to be in secure state 677 * (SCR.NS = 0), we change that here if non-secure boot has been 678 * requested. 679 */ 680 if (arm_feature(env, ARM_FEATURE_EL3)) { 681 /* AArch64 is defined to come out of reset into EL3 if enabled. 682 * If we are booting Linux then we need to adjust our EL as 683 * Linux expects us to be in EL2 or EL1. AArch32 resets into 684 * SVC, which Linux expects, so no privilege/exception level to 685 * adjust. 686 */ 687 if (env->aarch64) { 688 env->cp15.scr_el3 |= SCR_RW; 689 if (arm_feature(env, ARM_FEATURE_EL2)) { 690 env->cp15.hcr_el2 |= HCR_RW; 691 env->pstate = PSTATE_MODE_EL2h; 692 } else { 693 env->pstate = PSTATE_MODE_EL1h; 694 } 695 } 696 697 /* Set to non-secure if not a secure boot */ 698 if (!info->secure_boot && 699 (cs != first_cpu || !info->secure_board_setup)) { 700 /* Linux expects non-secure state */ 701 env->cp15.scr_el3 |= SCR_NS; 702 } 703 } 704 705 if (cs == first_cpu) { 706 cpu_set_pc(cs, info->loader_start); 707 708 if (!have_dtb(info)) { 709 if (old_param) { 710 set_kernel_args_old(info); 711 } else { 712 set_kernel_args(info); 713 } 714 } 715 } else { 716 info->secondary_cpu_reset_hook(cpu, info); 717 } 718 } 719 } 720 } 721 722 /** 723 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified 724 * by key. 725 * @fw_cfg: The firmware config instance to store the data in. 726 * @size_key: The firmware config key to store the size of the loaded 727 * data under, with fw_cfg_add_i32(). 728 * @data_key: The firmware config key to store the loaded data under, 729 * with fw_cfg_add_bytes(). 730 * @image_name: The name of the image file to load. If it is NULL, the 731 * function returns without doing anything. 732 * @try_decompress: Whether the image should be decompressed (gunzipped) before 733 * adding it to fw_cfg. If decompression fails, the image is 734 * loaded as-is. 735 * 736 * In case of failure, the function prints an error message to stderr and the 737 * process exits with status 1. 738 */ 739 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 740 uint16_t data_key, const char *image_name, 741 bool try_decompress) 742 { 743 size_t size = -1; 744 uint8_t *data; 745 746 if (image_name == NULL) { 747 return; 748 } 749 750 if (try_decompress) { 751 size = load_image_gzipped_buffer(image_name, 752 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 753 } 754 755 if (size == (size_t)-1) { 756 gchar *contents; 757 gsize length; 758 759 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 760 error_report("failed to load \"%s\"", image_name); 761 exit(1); 762 } 763 size = length; 764 data = (uint8_t *)contents; 765 } 766 767 fw_cfg_add_i32(fw_cfg, size_key, size); 768 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 769 } 770 771 static int do_arm_linux_init(Object *obj, void *opaque) 772 { 773 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 774 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 775 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 776 struct arm_boot_info *info = opaque; 777 778 if (albifc->arm_linux_init) { 779 albifc->arm_linux_init(albif, info->secure_boot); 780 } 781 } 782 return 0; 783 } 784 785 static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 786 uint64_t *lowaddr, uint64_t *highaddr, 787 int elf_machine) 788 { 789 bool elf_is64; 790 union { 791 Elf32_Ehdr h32; 792 Elf64_Ehdr h64; 793 } elf_header; 794 int data_swab = 0; 795 bool big_endian; 796 uint64_t ret = -1; 797 Error *err = NULL; 798 799 800 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 801 if (err) { 802 return ret; 803 } 804 805 if (elf_is64) { 806 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; 807 info->endianness = big_endian ? ARM_ENDIANNESS_BE8 808 : ARM_ENDIANNESS_LE; 809 } else { 810 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; 811 if (big_endian) { 812 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 813 info->endianness = ARM_ENDIANNESS_BE8; 814 } else { 815 info->endianness = ARM_ENDIANNESS_BE32; 816 /* In BE32, the CPU has a different view of the per-byte 817 * address map than the rest of the system. BE32 ELF files 818 * are organised such that they can be programmed through 819 * the CPU's per-word byte-reversed view of the world. QEMU 820 * however loads ELF files independently of the CPU. So 821 * tell the ELF loader to byte reverse the data for us. 822 */ 823 data_swab = 2; 824 } 825 } else { 826 info->endianness = ARM_ENDIANNESS_LE; 827 } 828 } 829 830 ret = load_elf(info->kernel_filename, NULL, NULL, 831 pentry, lowaddr, highaddr, big_endian, elf_machine, 832 1, data_swab); 833 if (ret <= 0) { 834 /* The header loaded but the image didn't */ 835 exit(1); 836 } 837 838 return ret; 839 } 840 841 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 842 hwaddr *entry) 843 { 844 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 845 uint8_t *buffer; 846 int size; 847 848 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 849 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 850 &buffer); 851 852 if (size < 0) { 853 gsize len; 854 855 /* Load as raw file otherwise */ 856 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 857 return -1; 858 } 859 size = len; 860 } 861 862 /* check the arm64 magic header value -- very old kernels may not have it */ 863 if (memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 864 uint64_t hdrvals[2]; 865 866 /* The arm64 Image header has text_offset and image_size fields at 8 and 867 * 16 bytes into the Image header, respectively. The text_offset field 868 * is only valid if the image_size is non-zero. 869 */ 870 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 871 if (hdrvals[1] != 0) { 872 kernel_load_offset = le64_to_cpu(hdrvals[0]); 873 } 874 } 875 876 *entry = mem_base + kernel_load_offset; 877 rom_add_blob_fixed(filename, buffer, size, *entry); 878 879 g_free(buffer); 880 881 return size; 882 } 883 884 static void arm_load_kernel_notify(Notifier *notifier, void *data) 885 { 886 CPUState *cs; 887 int kernel_size; 888 int initrd_size; 889 int is_linux = 0; 890 uint64_t elf_entry, elf_low_addr, elf_high_addr; 891 int elf_machine; 892 hwaddr entry; 893 static const ARMInsnFixup *primary_loader; 894 ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier, 895 notifier, notifier); 896 ARMCPU *cpu = n->cpu; 897 struct arm_boot_info *info = 898 container_of(n, struct arm_boot_info, load_kernel_notifier); 899 900 /* The board code is not supposed to set secure_board_setup unless 901 * running its code in secure mode is actually possible, and KVM 902 * doesn't support secure. 903 */ 904 assert(!(info->secure_board_setup && kvm_enabled())); 905 906 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 907 908 /* Load the kernel. */ 909 if (!info->kernel_filename || info->firmware_loaded) { 910 911 if (have_dtb(info)) { 912 /* If we have a device tree blob, but no kernel to supply it to (or 913 * the kernel is supposed to be loaded by the bootloader), copy the 914 * DTB to the base of RAM for the bootloader to pick up. 915 */ 916 if (load_dtb(info->loader_start, info, 0) < 0) { 917 exit(1); 918 } 919 } 920 921 if (info->kernel_filename) { 922 FWCfgState *fw_cfg; 923 bool try_decompressing_kernel; 924 925 fw_cfg = fw_cfg_find(); 926 try_decompressing_kernel = arm_feature(&cpu->env, 927 ARM_FEATURE_AARCH64); 928 929 /* Expose the kernel, the command line, and the initrd in fw_cfg. 930 * We don't process them here at all, it's all left to the 931 * firmware. 932 */ 933 load_image_to_fw_cfg(fw_cfg, 934 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 935 info->kernel_filename, 936 try_decompressing_kernel); 937 load_image_to_fw_cfg(fw_cfg, 938 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 939 info->initrd_filename, false); 940 941 if (info->kernel_cmdline) { 942 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 943 strlen(info->kernel_cmdline) + 1); 944 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 945 info->kernel_cmdline); 946 } 947 } 948 949 /* We will start from address 0 (typically a boot ROM image) in the 950 * same way as hardware. 951 */ 952 return; 953 } 954 955 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 956 primary_loader = bootloader_aarch64; 957 elf_machine = EM_AARCH64; 958 } else { 959 primary_loader = bootloader; 960 if (!info->write_board_setup) { 961 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 962 } 963 elf_machine = EM_ARM; 964 } 965 966 if (!info->secondary_cpu_reset_hook) { 967 info->secondary_cpu_reset_hook = default_reset_secondary; 968 } 969 if (!info->write_secondary_boot) { 970 info->write_secondary_boot = default_write_secondary; 971 } 972 973 if (info->nb_cpus == 0) 974 info->nb_cpus = 1; 975 976 /* We want to put the initrd far enough into RAM that when the 977 * kernel is uncompressed it will not clobber the initrd. However 978 * on boards without much RAM we must ensure that we still leave 979 * enough room for a decent sized initrd, and on boards with large 980 * amounts of RAM we must avoid the initrd being so far up in RAM 981 * that it is outside lowmem and inaccessible to the kernel. 982 * So for boards with less than 256MB of RAM we put the initrd 983 * halfway into RAM, and for boards with 256MB of RAM or more we put 984 * the initrd at 128MB. 985 */ 986 info->initrd_start = info->loader_start + 987 MIN(info->ram_size / 2, 128 * 1024 * 1024); 988 989 /* Assume that raw images are linux kernels, and ELF images are not. */ 990 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, 991 &elf_high_addr, elf_machine); 992 if (kernel_size > 0 && have_dtb(info)) { 993 /* If there is still some room left at the base of RAM, try and put 994 * the DTB there like we do for images loaded with -bios or -pflash. 995 */ 996 if (elf_low_addr > info->loader_start 997 || elf_high_addr < info->loader_start) { 998 /* Pass elf_low_addr as address limit to load_dtb if it may be 999 * pointing into RAM, otherwise pass '0' (no limit) 1000 */ 1001 if (elf_low_addr < info->loader_start) { 1002 elf_low_addr = 0; 1003 } 1004 if (load_dtb(info->loader_start, info, elf_low_addr) < 0) { 1005 exit(1); 1006 } 1007 } 1008 } 1009 entry = elf_entry; 1010 if (kernel_size < 0) { 1011 kernel_size = load_uimage(info->kernel_filename, &entry, NULL, 1012 &is_linux, NULL, NULL); 1013 } 1014 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 1015 kernel_size = load_aarch64_image(info->kernel_filename, 1016 info->loader_start, &entry); 1017 is_linux = 1; 1018 } else if (kernel_size < 0) { 1019 /* 32-bit ARM */ 1020 entry = info->loader_start + KERNEL_LOAD_ADDR; 1021 kernel_size = load_image_targphys(info->kernel_filename, entry, 1022 info->ram_size - KERNEL_LOAD_ADDR); 1023 is_linux = 1; 1024 } 1025 if (kernel_size < 0) { 1026 error_report("could not load kernel '%s'", info->kernel_filename); 1027 exit(1); 1028 } 1029 info->entry = entry; 1030 if (is_linux) { 1031 uint32_t fixupcontext[FIXUP_MAX]; 1032 1033 if (info->initrd_filename) { 1034 initrd_size = load_ramdisk(info->initrd_filename, 1035 info->initrd_start, 1036 info->ram_size - 1037 info->initrd_start); 1038 if (initrd_size < 0) { 1039 initrd_size = load_image_targphys(info->initrd_filename, 1040 info->initrd_start, 1041 info->ram_size - 1042 info->initrd_start); 1043 } 1044 if (initrd_size < 0) { 1045 error_report("could not load initrd '%s'", 1046 info->initrd_filename); 1047 exit(1); 1048 } 1049 } else { 1050 initrd_size = 0; 1051 } 1052 info->initrd_size = initrd_size; 1053 1054 fixupcontext[FIXUP_BOARDID] = info->board_id; 1055 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1056 1057 /* for device tree boot, we pass the DTB directly in r2. Otherwise 1058 * we point to the kernel args. 1059 */ 1060 if (have_dtb(info)) { 1061 hwaddr align; 1062 hwaddr dtb_start; 1063 1064 if (elf_machine == EM_AARCH64) { 1065 /* 1066 * Some AArch64 kernels on early bootup map the fdt region as 1067 * 1068 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1069 * 1070 * Let's play safe and prealign it to 2MB to give us some space. 1071 */ 1072 align = 2 * 1024 * 1024; 1073 } else { 1074 /* 1075 * Some 32bit kernels will trash anything in the 4K page the 1076 * initrd ends in, so make sure the DTB isn't caught up in that. 1077 */ 1078 align = 4096; 1079 } 1080 1081 /* Place the DTB after the initrd in memory with alignment. */ 1082 dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); 1083 if (load_dtb(dtb_start, info, 0) < 0) { 1084 exit(1); 1085 } 1086 fixupcontext[FIXUP_ARGPTR] = dtb_start; 1087 } else { 1088 fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR; 1089 if (info->ram_size >= (1ULL << 32)) { 1090 error_report("RAM size must be less than 4GB to boot" 1091 " Linux kernel using ATAGS (try passing a device tree" 1092 " using -dtb)"); 1093 exit(1); 1094 } 1095 } 1096 fixupcontext[FIXUP_ENTRYPOINT] = entry; 1097 1098 write_bootloader("bootloader", info->loader_start, 1099 primary_loader, fixupcontext); 1100 1101 if (info->nb_cpus > 1) { 1102 info->write_secondary_boot(cpu, info); 1103 } 1104 if (info->write_board_setup) { 1105 info->write_board_setup(cpu, info); 1106 } 1107 1108 /* Notify devices which need to fake up firmware initialization 1109 * that we're doing a direct kernel boot. 1110 */ 1111 object_child_foreach_recursive(object_get_root(), 1112 do_arm_linux_init, info); 1113 } 1114 info->is_linux = is_linux; 1115 1116 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { 1117 ARM_CPU(cs)->env.boot_info = info; 1118 } 1119 } 1120 1121 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) 1122 { 1123 CPUState *cs; 1124 1125 info->load_kernel_notifier.cpu = cpu; 1126 info->load_kernel_notifier.notifier.notify = arm_load_kernel_notify; 1127 qemu_add_machine_init_done_notifier(&info->load_kernel_notifier.notifier); 1128 1129 /* CPU objects (unlike devices) are not automatically reset on system 1130 * reset, so we must always register a handler to do so. If we're 1131 * actually loading a kernel, the handler is also responsible for 1132 * arranging that we start it correctly. 1133 */ 1134 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { 1135 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1136 } 1137 } 1138 1139 static const TypeInfo arm_linux_boot_if_info = { 1140 .name = TYPE_ARM_LINUX_BOOT_IF, 1141 .parent = TYPE_INTERFACE, 1142 .class_size = sizeof(ARMLinuxBootIfClass), 1143 }; 1144 1145 static void arm_linux_boot_register_types(void) 1146 { 1147 type_register_static(&arm_linux_boot_if_info); 1148 } 1149 1150 type_init(arm_linux_boot_register_types) 1151