1 /* 2 * BCM2838 SoC emulation 3 * 4 * Copyright (C) 2022 Ovchinnikov Vitalii <vitalii.ovchinnikov@auriga.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qapi/error.h" 11 #include "qemu/module.h" 12 #include "hw/arm/raspi_platform.h" 13 #include "hw/sysbus.h" 14 #include "hw/arm/bcm2838.h" 15 #include "trace.h" 16 17 #define GIC400_MAINTENANCE_IRQ 9 18 #define GIC400_TIMER_NS_EL2_IRQ 10 19 #define GIC400_TIMER_VIRT_IRQ 11 20 #define GIC400_LEGACY_FIQ 12 21 #define GIC400_TIMER_S_EL1_IRQ 13 22 #define GIC400_TIMER_NS_EL1_IRQ 14 23 #define GIC400_LEGACY_IRQ 15 24 25 /* Number of external interrupt lines to configure the GIC with */ 26 #define GIC_NUM_IRQS 192 27 28 #define PPI(cpu, irq) (GIC_NUM_IRQS + (cpu) * GIC_INTERNAL + GIC_NR_SGIS + irq) 29 30 #define GIC_BASE_OFS 0x0000 31 #define GIC_DIST_OFS 0x1000 32 #define GIC_CPU_OFS 0x2000 33 #define GIC_VIFACE_THIS_OFS 0x4000 34 #define GIC_VIFACE_OTHER_OFS(cpu) (0x5000 + (cpu) * 0x200) 35 #define GIC_VCPU_OFS 0x6000 36 37 #define VIRTUAL_PMU_IRQ 7 38 39 static void bcm2838_gic_set_irq(void *opaque, int irq, int level) 40 { 41 BCM2838State *s = (BCM2838State *)opaque; 42 43 trace_bcm2838_gic_set_irq(irq, level); 44 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 45 } 46 47 static void bcm2838_init(Object *obj) 48 { 49 BCM2838State *s = BCM2838(obj); 50 51 object_initialize_child(obj, "peripherals", &s->peripherals, 52 TYPE_BCM2838_PERIPHERALS); 53 object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), 54 "board-rev"); 55 object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), 56 "vcram-size"); 57 object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals), 58 "command-line"); 59 60 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); 61 } 62 63 static void bcm2838_realize(DeviceState *dev, Error **errp) 64 { 65 BCM2838State *s = BCM2838(dev); 66 BCM283XBaseState *s_base = BCM283X_BASE(dev); 67 BCM283XBaseClass *bc_base = BCM283X_BASE_GET_CLASS(dev); 68 BCM2838PeripheralState *ps = BCM2838_PERIPHERALS(&s->peripherals); 69 BCMSocPeripheralBaseState *ps_base = 70 BCM_SOC_PERIPHERALS_BASE(&s->peripherals); 71 72 DeviceState *gicdev = NULL; 73 74 if (!bcm283x_common_realize(dev, ps_base, errp)) { 75 return; 76 } 77 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(ps), 1, BCM2838_PERI_LOW_BASE, 1); 78 79 /* bcm2836 interrupt controller (and mailboxes, etc.) */ 80 if (!sysbus_realize(SYS_BUS_DEVICE(&s_base->control), errp)) { 81 return; 82 } 83 sysbus_mmio_map(SYS_BUS_DEVICE(&s_base->control), 0, bc_base->ctrl_base); 84 85 /* Create cores */ 86 for (int n = 0; n < bc_base->core_count; n++) { 87 88 object_property_set_int(OBJECT(&s_base->cpu[n].core), "mp-affinity", 89 (bc_base->clusterid << 8) | n, &error_abort); 90 91 /* set periphbase/CBAR value for CPU-local registers */ 92 object_property_set_int(OBJECT(&s_base->cpu[n].core), "reset-cbar", 93 bc_base->peri_base, &error_abort); 94 95 /* start powered off if not enabled */ 96 object_property_set_bool(OBJECT(&s_base->cpu[n].core), 97 "start-powered-off", 98 n >= s_base->enabled_cpus, &error_abort); 99 100 if (!qdev_realize(DEVICE(&s_base->cpu[n].core), NULL, errp)) { 101 return; 102 } 103 } 104 105 if (!object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp)) { 106 return; 107 } 108 109 if (!object_property_set_uint(OBJECT(&s->gic), "num-cpu", BCM283X_NCPUS, 110 errp)) { 111 return; 112 } 113 114 if (!object_property_set_uint(OBJECT(&s->gic), "num-irq", 115 GIC_NUM_IRQS + GIC_INTERNAL, errp)) { 116 return; 117 } 118 119 if (!object_property_set_bool(OBJECT(&s->gic), 120 "has-virtualization-extensions", true, 121 errp)) { 122 return; 123 } 124 125 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 126 return; 127 } 128 129 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, 130 bc_base->ctrl_base + BCM2838_GIC_BASE + GIC_DIST_OFS); 131 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, 132 bc_base->ctrl_base + BCM2838_GIC_BASE + GIC_CPU_OFS); 133 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, 134 bc_base->ctrl_base + BCM2838_GIC_BASE + GIC_VIFACE_THIS_OFS); 135 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, 136 bc_base->ctrl_base + BCM2838_GIC_BASE + GIC_VCPU_OFS); 137 138 for (int n = 0; n < BCM283X_NCPUS; n++) { 139 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 4 + n, 140 bc_base->ctrl_base + BCM2838_GIC_BASE 141 + GIC_VIFACE_OTHER_OFS(n)); 142 } 143 144 gicdev = DEVICE(&s->gic); 145 146 for (int n = 0; n < BCM283X_NCPUS; n++) { 147 DeviceState *cpudev = DEVICE(&s_base->cpu[n]); 148 149 /* Connect the GICv2 outputs to the CPU */ 150 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n, 151 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 152 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + BCM283X_NCPUS, 153 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 154 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + 2 * BCM283X_NCPUS, 155 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 156 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + 3 * BCM283X_NCPUS, 157 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 158 159 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + 4 * BCM283X_NCPUS, 160 qdev_get_gpio_in(gicdev, 161 PPI(n, GIC400_MAINTENANCE_IRQ))); 162 163 /* Connect timers from the CPU to the interrupt controller */ 164 qdev_connect_gpio_out(cpudev, GTIMER_PHYS, 165 qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_NS_EL1_IRQ))); 166 qdev_connect_gpio_out(cpudev, GTIMER_VIRT, 167 qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_VIRT_IRQ))); 168 qdev_connect_gpio_out(cpudev, GTIMER_HYP, 169 qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_NS_EL2_IRQ))); 170 qdev_connect_gpio_out(cpudev, GTIMER_SEC, 171 qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_S_EL1_IRQ))); 172 /* PMU interrupt */ 173 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 174 qdev_get_gpio_in(gicdev, PPI(n, VIRTUAL_PMU_IRQ))); 175 } 176 177 /* Connect UART0 to the interrupt controller */ 178 sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->uart0), 0, 179 qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_UART0)); 180 181 /* Connect AUX / UART1 to the interrupt controller */ 182 sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->aux), 0, 183 qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_AUX_UART1)); 184 185 /* Connect VC mailbox to the interrupt controller */ 186 sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->mboxes), 0, 187 qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_MBOX)); 188 189 /* Connect SD host to the interrupt controller */ 190 sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->sdhost), 0, 191 qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_SDHOST)); 192 193 /* According to DTS, EMMC and EMMC2 share one irq */ 194 DeviceState *mmc_irq_orgate = DEVICE(&ps->mmc_irq_orgate); 195 196 /* Connect EMMC and EMMC2 to the interrupt controller */ 197 qdev_connect_gpio_out(mmc_irq_orgate, 0, 198 qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_EMMC_EMMC2)); 199 200 /* Connect USB OTG and MPHI to the interrupt controller */ 201 sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->mphi), 0, 202 qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_MPHI)); 203 sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->dwc2), 0, 204 qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_DWC2)); 205 206 /* Connect DMA 0-6 to the interrupt controller */ 207 for (int n = GIC_SPI_INTERRUPT_DMA_0; n <= GIC_SPI_INTERRUPT_DMA_6; n++) { 208 sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->dma), 209 n - GIC_SPI_INTERRUPT_DMA_0, 210 qdev_get_gpio_in(gicdev, n)); 211 } 212 213 /* According to DTS, DMA 7 and 8 share one irq */ 214 DeviceState *dma_7_8_irq_orgate = DEVICE(&ps->dma_7_8_irq_orgate); 215 216 /* Connect DMA 7-8 to the interrupt controller */ 217 qdev_connect_gpio_out(dma_7_8_irq_orgate, 0, 218 qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_DMA_7_8)); 219 220 /* According to DTS, DMA 9 and 10 share one irq */ 221 DeviceState *dma_9_10_irq_orgate = DEVICE(&ps->dma_9_10_irq_orgate); 222 223 /* Connect DMA 9-10 to the interrupt controller */ 224 qdev_connect_gpio_out(dma_9_10_irq_orgate, 0, 225 qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_DMA_9_10)); 226 227 /* Pass through inbound GPIO lines to the GIC */ 228 qdev_init_gpio_in(dev, bcm2838_gic_set_irq, GIC_NUM_IRQS); 229 230 /* Pass through outbound IRQ lines from the GIC */ 231 qdev_pass_gpios(DEVICE(&s->gic), DEVICE(&s->peripherals), NULL); 232 } 233 234 static void bcm2838_class_init(ObjectClass *oc, void *data) 235 { 236 DeviceClass *dc = DEVICE_CLASS(oc); 237 BCM283XBaseClass *bc_base = BCM283X_BASE_CLASS(oc); 238 239 bc_base->cpu_type = ARM_CPU_TYPE_NAME("cortex-a72"); 240 bc_base->core_count = BCM283X_NCPUS; 241 bc_base->peri_base = 0xfe000000; 242 bc_base->ctrl_base = 0xff800000; 243 bc_base->clusterid = 0x0; 244 dc->realize = bcm2838_realize; 245 } 246 247 static const TypeInfo bcm2838_type = { 248 .name = TYPE_BCM2838, 249 .parent = TYPE_BCM283X_BASE, 250 .instance_size = sizeof(BCM2838State), 251 .instance_init = bcm2838_init, 252 .class_size = sizeof(BCM283XBaseClass), 253 .class_init = bcm2838_class_init, 254 }; 255 256 static void bcm2838_register_types(void) 257 { 258 type_register_static(&bcm2838_type); 259 } 260 261 type_init(bcm2838_register_types); 262