1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qemu/module.h" 15 #include "hw/arm/bcm2836.h" 16 #include "hw/arm/raspi_platform.h" 17 #include "hw/sysbus.h" 18 19 struct BCM283XClass { 20 /*< private >*/ 21 DeviceClass parent_class; 22 /*< public >*/ 23 const char *name; 24 const char *cpu_type; 25 unsigned core_count; 26 hwaddr peri_base; /* Peripheral base address seen by the CPU */ 27 hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ 28 int clusterid; 29 }; 30 31 static Property bcm2836_enabled_cores_property = 32 DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0); 33 34 static void bcm2836_init(Object *obj) 35 { 36 BCM283XState *s = BCM283X(obj); 37 BCM283XClass *bc = BCM283X_GET_CLASS(obj); 38 int n; 39 40 for (n = 0; n < bc->core_count; n++) { 41 object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, 42 bc->cpu_type); 43 } 44 if (bc->core_count > 1) { 45 qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property); 46 qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); 47 } 48 49 if (bc->ctrl_base) { 50 object_initialize_child(obj, "control", &s->control, 51 TYPE_BCM2836_CONTROL); 52 } 53 54 object_initialize_child(obj, "peripherals", &s->peripherals, 55 TYPE_BCM2835_PERIPHERALS); 56 object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), 57 "board-rev"); 58 object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals), 59 "command-line"); 60 object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), 61 "vcram-size"); 62 } 63 64 static bool bcm283x_common_realize(DeviceState *dev, Error **errp) 65 { 66 BCM283XState *s = BCM283X(dev); 67 BCM283XClass *bc = BCM283X_GET_CLASS(dev); 68 Object *obj; 69 70 /* common peripherals from bcm2835 */ 71 72 obj = object_property_get_link(OBJECT(dev), "ram", &error_abort); 73 74 object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj); 75 76 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) { 77 return false; 78 } 79 80 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals), 81 "sd-bus"); 82 83 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, 84 bc->peri_base, 1); 85 return true; 86 } 87 88 static void bcm2835_realize(DeviceState *dev, Error **errp) 89 { 90 BCM283XState *s = BCM283X(dev); 91 92 if (!bcm283x_common_realize(dev, errp)) { 93 return; 94 } 95 96 if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) { 97 return; 98 } 99 100 /* Connect irq/fiq outputs from the interrupt controller. */ 101 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, 102 qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ)); 103 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, 104 qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ)); 105 } 106 107 static void bcm2836_realize(DeviceState *dev, Error **errp) 108 { 109 BCM283XState *s = BCM283X(dev); 110 BCM283XClass *bc = BCM283X_GET_CLASS(dev); 111 int n; 112 113 if (!bcm283x_common_realize(dev, errp)) { 114 return; 115 } 116 117 /* bcm2836 interrupt controller (and mailboxes, etc.) */ 118 if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) { 119 return; 120 } 121 122 sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base); 123 124 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, 125 qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); 126 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, 127 qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); 128 129 for (n = 0; n < BCM283X_NCPUS; n++) { 130 /* TODO: this should be converted to a property of ARM_CPU */ 131 s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n; 132 133 /* set periphbase/CBAR value for CPU-local registers */ 134 if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", 135 bc->peri_base, errp)) { 136 return; 137 } 138 139 /* start powered off if not enabled */ 140 if (!object_property_set_bool(OBJECT(&s->cpu[n].core), 141 "start-powered-off", 142 n >= s->enabled_cpus, 143 errp)) { 144 return; 145 } 146 147 if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { 148 return; 149 } 150 151 /* Connect irq/fiq outputs from the interrupt controller. */ 152 qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, 153 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); 154 qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, 155 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); 156 157 /* Connect timers from the CPU to the interrupt controller */ 158 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, 159 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n)); 160 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, 161 qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); 162 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, 163 qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)); 164 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, 165 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)); 166 } 167 } 168 169 static void bcm283x_class_init(ObjectClass *oc, void *data) 170 { 171 DeviceClass *dc = DEVICE_CLASS(oc); 172 173 /* Reason: Must be wired up in code (see raspi_init() function) */ 174 dc->user_creatable = false; 175 } 176 177 static void bcm2835_class_init(ObjectClass *oc, void *data) 178 { 179 DeviceClass *dc = DEVICE_CLASS(oc); 180 BCM283XClass *bc = BCM283X_CLASS(oc); 181 182 bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); 183 bc->core_count = 1; 184 bc->peri_base = 0x20000000; 185 dc->realize = bcm2835_realize; 186 }; 187 188 static void bcm2836_class_init(ObjectClass *oc, void *data) 189 { 190 DeviceClass *dc = DEVICE_CLASS(oc); 191 BCM283XClass *bc = BCM283X_CLASS(oc); 192 193 bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 194 bc->core_count = BCM283X_NCPUS; 195 bc->peri_base = 0x3f000000; 196 bc->ctrl_base = 0x40000000; 197 bc->clusterid = 0xf; 198 dc->realize = bcm2836_realize; 199 }; 200 201 #ifdef TARGET_AARCH64 202 static void bcm2837_class_init(ObjectClass *oc, void *data) 203 { 204 DeviceClass *dc = DEVICE_CLASS(oc); 205 BCM283XClass *bc = BCM283X_CLASS(oc); 206 207 bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); 208 bc->core_count = BCM283X_NCPUS; 209 bc->peri_base = 0x3f000000; 210 bc->ctrl_base = 0x40000000; 211 bc->clusterid = 0x0; 212 dc->realize = bcm2836_realize; 213 }; 214 #endif 215 216 static const TypeInfo bcm283x_types[] = { 217 { 218 .name = TYPE_BCM2835, 219 .parent = TYPE_BCM283X, 220 .class_init = bcm2835_class_init, 221 }, { 222 .name = TYPE_BCM2836, 223 .parent = TYPE_BCM283X, 224 .class_init = bcm2836_class_init, 225 #ifdef TARGET_AARCH64 226 }, { 227 .name = TYPE_BCM2837, 228 .parent = TYPE_BCM283X, 229 .class_init = bcm2837_class_init, 230 #endif 231 }, { 232 .name = TYPE_BCM283X, 233 .parent = TYPE_DEVICE, 234 .instance_size = sizeof(BCM283XState), 235 .instance_init = bcm2836_init, 236 .class_size = sizeof(BCM283XClass), 237 .class_init = bcm283x_class_init, 238 .abstract = true, 239 } 240 }; 241 242 DEFINE_TYPES(bcm283x_types) 243