1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * Jeremy Kerr <jk@ozlabs.org> 6 * 7 * Copyright 2016 IBM Corp. 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qapi/error.h" 15 #include "hw/qdev-properties.h" 16 #include "hw/misc/unimp.h" 17 #include "hw/arm/aspeed_soc.h" 18 #include "hw/char/serial.h" 19 20 21 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) 22 { 23 return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); 24 } 25 26 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp) 27 { 28 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 29 SerialMM *smm; 30 31 for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { 32 smm = &s->uart[i]; 33 34 /* Chardev property is set by the machine. */ 35 qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); 36 qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); 37 qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); 38 qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); 39 if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { 40 return false; 41 } 42 43 sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart)); 44 aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); 45 } 46 47 return true; 48 } 49 50 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) 51 { 52 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 53 int i = dev - ASPEED_DEV_UART1; 54 55 g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num); 56 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); 57 } 58 59 /* 60 * SDMC should be realized first to get correct RAM size and max size 61 * values 62 */ 63 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp) 64 { 65 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 66 ram_addr_t ram_size, max_ram_size; 67 68 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 69 &error_abort); 70 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 71 &error_abort); 72 73 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 74 max_ram_size); 75 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 76 77 /* 78 * Add a memory region beyond the RAM region to let firmwares scan 79 * the address space with load/store and guess how much RAM the 80 * SoC has. 81 */ 82 if (ram_size < max_ram_size) { 83 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 84 85 qdev_prop_set_string(dev, "name", "ram-empty"); 86 qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size); 87 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { 88 return false; 89 } 90 91 memory_region_add_subregion_overlap(&s->dram_container, ram_size, 92 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000); 93 } 94 95 memory_region_add_subregion(s->memory, 96 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 97 return true; 98 } 99 100 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr) 101 { 102 memory_region_add_subregion(s->memory, addr, 103 sysbus_mmio_get_region(dev, n)); 104 } 105 106 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 107 const char *name, hwaddr addr, uint64_t size) 108 { 109 qdev_prop_set_string(DEVICE(dev), "name", name); 110 qdev_prop_set_uint64(DEVICE(dev), "size", size); 111 sysbus_realize(dev, &error_abort); 112 113 memory_region_add_subregion_overlap(s->memory, addr, 114 sysbus_mmio_get_region(dev, 0), -1000); 115 } 116 117 static void aspeed_soc_realize(DeviceState *dev, Error **errp) 118 { 119 AspeedSoCState *s = ASPEED_SOC(dev); 120 121 if (!s->memory) { 122 error_setg(errp, "'memory' link is not set"); 123 return; 124 } 125 } 126 127 static Property aspeed_soc_properties[] = { 128 DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, 129 MemoryRegion *), 130 DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION, 131 MemoryRegion *), 132 DEFINE_PROP_END_OF_LIST(), 133 }; 134 135 static void aspeed_soc_class_init(ObjectClass *oc, void *data) 136 { 137 DeviceClass *dc = DEVICE_CLASS(oc); 138 139 dc->realize = aspeed_soc_realize; 140 device_class_set_props(dc, aspeed_soc_properties); 141 } 142 143 static const TypeInfo aspeed_soc_types[] = { 144 { 145 .name = TYPE_ASPEED_SOC, 146 .parent = TYPE_DEVICE, 147 .instance_size = sizeof(AspeedSoCState), 148 .class_size = sizeof(AspeedSoCClass), 149 .class_init = aspeed_soc_class_init, 150 .abstract = true, 151 }, 152 }; 153 154 DEFINE_TYPES(aspeed_soc_types) 155